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11. 发明申请

US20110298090A1 Capacitors, Systems, and Methods 失效
标题翻译：电容器，系统和方法
公开(公告)号：US20110298090A1
公开(公告)日：2011-12-08
申请号：US12794251
申请日：2010-06-04
申请人： Chanro Park , Sangduk Park , Paul D. Kirsch , David Gilmer , Chang Yong Kang , Joel Barnett
发明人： Chanro Park , Sangduk Park , Paul D. Kirsch , David Gilmer , Chang Yong Kang , Joel Barnett
IPC分类号： H01L29/92 , H01L21/02
CPC分类号： H01L28/40 , H01L28/65
摘要： Capacitors, systems, and methods are disclosed. In one embodiment, the capacitor includes a first electrode. The capacitor may also include a first insulator layer having a positive VCC adjacent to the first electrode. The capacitor may further include a second insulator layer having a negative VCC adjacent to the first insulator layer. The capacitor may also include a third insulator layer having a positive VCC adjacent to the second insulator layer. The capacitor may also include a second electrode adjacent to the third insulator layer.
摘要翻译：公开了电容器，系统和方法。在一个实施例中，电容器包括第一电极。电容器还可以包括具有与第一电极相邻的正VCC的第一绝缘体层。电容器还可以包括具有与第一绝缘体层相邻的负VCC的第二绝缘体层。电容器还可以包括具有与第二绝缘体层相邻的正VCC的第三绝缘体层。电容器还可以包括与第三绝缘体层相邻的第二电极。

12. 发明申请

US20070077698A1 METHOD FOR FABRICATING DUAL-METAL GATE DEVICE 有权
标题翻译：用于制造双金属栅极装置的方法
公开(公告)号：US20070077698A1
公开(公告)日：2007-04-05
申请号：US11530058
申请日：2006-09-08
申请人： David Gilmer , Srikanth Samavedam , Philip Tobin
发明人： David Gilmer , Srikanth Samavedam , Philip Tobin
IPC分类号： H01L21/8238
CPC分类号： H01L21/823842
摘要： A method of fabricating a MOS transistor that comprises a dual-metal gate that is formed from heterotypical metals. A gate dielectric (34), such as HfO2, is deposited on a semiconductor substrate. A sacrificial layer (35), is next deposited over the gate dielectric. The sacrificial layer is patterned so that the gate dielectric over a first (pMOS, for example) area (32) of the substrate is exposed and gate dielectric over a second (nMOS, for example) area (33) of the substrate continues to be protected by the sacrificial layer. A first gate conductor material (51) is deposited over the remaining sacrificial area and over the exposed gate dielectric. The first gate conductor material is patterned so that first gate conductor material over the second area of the substrate is etched away. The sacrificial layer over the second area prevents damage to the underlying dielectric material as the first gate conductor material is removed.
摘要翻译：一种制造包括由异型金属形成的双金属栅极的MOS晶体管的方法。在半导体衬底上沉积诸如HfO 2 N的栅极电介质（34）。牺牲层（35）接着沉积在栅极电介质上。牺牲层被图案化，使得衬底的第一（pMOS，例如）区域（32）上的栅极电介质被暴露，并且衬底的第二（nMOS，例如）区域（33）上的栅极电介质继续是受牺牲层保护。第一栅极导体材料（51）沉积在剩余的牺牲区域上并暴露在栅极电介质上。图案化第一栅极导体材料，使得衬底的第二区域上方的第一栅极导体材料被蚀刻掉。第二区域上的牺牲层防止在去除第一栅极导体材料时损坏下面的介电材料。

13. 发明授权

US08432020B2 Capacitors, systems, and methods 失效
标题翻译：电容器，系统和方法
公开(公告)号：US08432020B2
公开(公告)日：2013-04-30
申请号：US12794251
申请日：2010-06-04
申请人： Chanro Park , Sangduk Park , Paul D. Kirsch , David Gilmer , Chang Yong Kang , Joel Barnett
发明人： Chanro Park , Sangduk Park , Paul D. Kirsch , David Gilmer , Chang Yong Kang , Joel Barnett
IPC分类号： H01L29/92 , H01L21/02
CPC分类号： H01L28/40 , H01L28/65
摘要： Capacitors, systems, and methods are disclosed. In one embodiment, the capacitor includes a first electrode. The capacitor may also include a first insulator layer having a positive VCC adjacent to the first electrode. The capacitor may further include a second insulator layer having a negative VCC adjacent to the first insulator layer. The capacitor may also include a third insulator layer having a positive VCC adjacent to the second insulator layer. The capacitor may also include a second electrode adjacent to the third insulator layer.
摘要翻译：公开了电容器，系统和方法。在一个实施例中，电容器包括第一电极。电容器还可以包括具有与第一电极相邻的正VCC的第一绝缘体层。电容器还可以包括具有邻近第一绝缘体层的负VCC的第二绝缘体层。电容器还可以包括具有与第二绝缘体层相邻的正VCC的第三绝缘体层。电容器还可以包括与第三绝缘体层相邻的第二电极。

14. 发明申请

US20050136633A1 Blocking layer for silicide uniformity in a semiconductor transistor 审中-公开
标题翻译：半导体晶体管中硅化物均匀性的阻挡层
公开(公告)号：US20050136633A1
公开(公告)日：2005-06-23
申请号：US10739684
申请日：2003-12-18
申请人： William Taylor , David Gilmer , Srikanth Samavedam
发明人： William Taylor , David Gilmer , Srikanth Samavedam
IPC分类号： H01L21/28 , H01L21/3205 , H01L21/44 , H01L21/4763 , H01L29/49
CPC分类号： H01L29/4933 , H01L21/28052
摘要： A semiconductor device and fabrication process includes forming a gate dielectric overlying a semiconductor substrate and a gate electrode overlying the gate dielectric. The gate electrode includes an interface between a first portion of the gate electrode and a second portion of the gate electrode. A silicide is then formed overlying the gate electrode. The presence of the gate electrode interface substantially prevents the silicide from spiking into or through the gate electrode to encroach upon or contact the underlying gate dielectric. Forming the gate electrode may include forming a polysilicon first gate electrode layer and forming an amorphous silicon layer over the polysilicon first gate electrode layer. Forming the second gate electrode layer may include forming a SiGe first sublayer and a polysilicon second sublayer.
摘要翻译：半导体器件和制造工艺包括形成覆盖半导体衬底的栅极电介质和覆盖栅极电介质的栅电极。栅电极包括栅电极的第一部分和栅电极的第二部分之间的界面。然后形成覆盖栅电极的硅化物。栅电极界面的存在基本上防止硅化物尖峰进入或穿过栅极电极侵入或接触下面的栅极电介质。形成栅电极可以包括形成多晶硅第一栅电极层，并在多晶硅第一栅电极层上形成非晶硅层。形成第二栅电极层可以包括形成SiGe第一子层和多晶硅第二子层。

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