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11. 发明申请

US20070111412A1 Thin film transistor array panel and method of manufacturing the same 审中-公开
标题翻译：薄膜晶体管阵列面板及其制造方法
公开(公告)号：US20070111412A1
公开(公告)日：2007-05-17
申请号：US11600481
申请日：2006-11-15
申请人： Min-Seok Oh , Jeong-Min Park , Sang-Gab Kim , Hong-Kee Chin , Chang-Oh Jeong , Hong-Sick Park , Shi-Yul Kim
发明人： Min-Seok Oh , Jeong-Min Park , Sang-Gab Kim , Hong-Kee Chin , Chang-Oh Jeong , Hong-Sick Park , Shi-Yul Kim
IPC分类号： H01L21/84
CPC分类号： H01L21/32139 , H01L21/0273 , H01L27/12 , H01L27/124 , H01L27/1288
摘要： In one embodiment, a thin film transistor array display panel and method of manufacturing the same are provided. A method includes forming a gate line on a substrate; forming a gate insulating layer, a semiconductor layer, and an ohmic contact layer on the gate line; forming a data layer on the ohmic contact layer; forming a photosensitive pattern on the data layer; etching the data layer to form a data line including a source electrode and a drain electrode that is opposite to the source electrode; reflowing the photosensitive pattern to cover side surfaces of the source electrode and the drain electrode; and etching the ohmic contact layer using the reflowed photosensitive pattern as a mask.
摘要翻译：在一个实施例中，提供了薄膜晶体管阵列显示面板及其制造方法。一种方法包括在基板上形成栅极线; 在栅极线上形成栅极绝缘层，半导体层和欧姆接触层; 在欧姆接触层上形成数据层; 在数据层上形成感光图案; 蚀刻数据层以形成包括与源电极相对的源电极和漏电极的数据线; 回流感光图案以覆盖源电极和漏电极的侧表面; 并使用回流感光图案作为掩模蚀刻欧姆接触层。

12. 发明申请

US20070102770A1 THIN FILM TRANSISTOR ARRAY PANEL AND MANUFACTURING METHOD THEREOF 审中-公开
标题翻译：薄膜晶体管阵列及其制造方法
公开(公告)号：US20070102770A1
公开(公告)日：2007-05-10
申请号：US11619451
申请日：2007-01-03
申请人： Woo-Geun Lee , Beom-Seok Cho , Je-Hun Lee , Chang-Oh Jeong , Sang-Gab Kim , Min-Seok Oh , Young-Wook Lee , Hee-Hwan Choe
发明人： Woo-Geun Lee , Beom-Seok Cho , Je-Hun Lee , Chang-Oh Jeong , Sang-Gab Kim , Min-Seok Oh , Young-Wook Lee , Hee-Hwan Choe
IPC分类号： H01L29/76
CPC分类号： H01L27/1288 , G02F2001/136236 , H01L21/31144 , H01L21/32139 , H01L27/1214 , H01L27/124 , H01L29/41733
摘要： A method of manufacturing a thin film transistor array panel including forming a gate line on a substrate, forming a gate insulating layer on the gate line, forming a semiconductor layer on the gate insulating layer, forming a data line and a drain electrode on the semiconductor layer, depositing a passivation layer on the data line and the drain electrode, forming a photoresist including a first portion and a second portion, which is thinner than the first portion, on the passivation layer, etching the passivation layer using the photoresist as a mask to expose a portion of the drain electrode, removing the second portion of the photoresist, depositing a conductive film, and removing the first portion of the photoresist to form a pixel electrode on the exposed portion of the drain electrode.
摘要翻译：一种制造薄膜晶体管阵列面板的方法，包括在衬底上形成栅极线，在栅极线上形成栅极绝缘层，在栅极绝缘层上形成半导体层，在半导体上形成数据线和漏电极在所述数据线和所述漏电极上沉积钝化层，在所述钝化层上形成包含比所述第一部分薄的第一部分和第二部分的光致抗蚀剂，使用所述光致抗蚀剂作为掩模蚀刻所述钝化层露出漏极的一部分，去除光致抗蚀剂的第二部分，沉积导电膜，以及去除光致抗蚀剂的第一部分，以在漏电极的暴露部分上形成像素电极。

13. 发明申请

US20050221546A1 Thin film transistor array panel and manufacturing method thereof 有权
标题翻译：薄膜晶体管阵列面板及其制造方法
公开(公告)号：US20050221546A1
公开(公告)日：2005-10-06
申请号：US11082967
申请日：2005-03-18
申请人： Woo-Geun Lee , Beom-Seok Cho , Je-Hun Lee , Chang-Oh Jeong , Sang-Gab Kim , Min-Seok Oh , Young-Wook Lee , Hee-Hwan Choe
发明人： Woo-Geun Lee , Beom-Seok Cho , Je-Hun Lee , Chang-Oh Jeong , Sang-Gab Kim , Min-Seok Oh , Young-Wook Lee , Hee-Hwan Choe
IPC分类号： G02F1/1368 , G09F9/30 , G09G3/36 , G09G3/38 , H01L21/00 , H01L21/311 , H01L21/3213 , H01L21/336 , H01L21/77 , H01L21/84 , H01L27/12 , H01L29/786
CPC分类号： H01L27/1288 , G02F2001/136236 , H01L21/31144 , H01L21/32139 , H01L27/1214 , H01L27/124 , H01L29/41733
摘要： A method of manufacturing a thin film transistor array panel including forming a gate line on a substrate, forming a gate insulating layer on the gate line, forming a semiconductor layer on the gate insulating layer, forming a data line and a drain electrode on the semiconductor layer, depositing a passivation layer on the data line and the drain electrode, forming a photoresist including a first portion and a second portion, which is thinner than the first portion, on the passivation layer, etching the passivation layer using the photoresist as a mask to expose a portion of the drain electrode, removing the second portion of the photoresist, depositing a conductive film, and removing the first portion of the photoresist to form a pixel electrode on the exposed portion of the drain electrode.
摘要翻译：一种制造薄膜晶体管阵列面板的方法，包括在衬底上形成栅极线，在栅极线上形成栅极绝缘层，在栅极绝缘层上形成半导体层，在半导体上形成数据线和漏电极在所述数据线和所述漏电极上沉积钝化层，在所述钝化层上形成包含比所述第一部分薄的第一部分和第二部分的光致抗蚀剂，使用所述光致抗蚀剂作为掩模蚀刻所述钝化层露出漏极的一部分，去除光致抗蚀剂的第二部分，沉积导电膜，以及去除光致抗蚀剂的第一部分，以在漏电极的暴露部分上形成像素电极。

14. 发明授权

US08044398B2 Display substrate 有权
标题翻译：显示基板
公开(公告)号：US08044398B2
公开(公告)日：2011-10-25
申请号：US12331138
申请日：2008-12-09
申请人： Hong-Long Ning , Chang-Oh Jeong , Je-Hun Lee , Yang-Ho Bae , Pil-Sang Yun , Hong-Sick Park , Joo-Ae Youn , Byeong-Beom Kim , Byeong-Jin Lee
发明人： Hong-Long Ning , Chang-Oh Jeong , Je-Hun Lee , Yang-Ho Bae , Pil-Sang Yun , Hong-Sick Park , Joo-Ae Youn , Byeong-Beom Kim , Byeong-Jin Lee
IPC分类号： H01L29/04 , H01L29/15 , H01L27/01 , H01L27/12
CPC分类号： G02F1/136286 , G02F2001/136295 , H01L27/124 , H01L29/41733 , H01L29/42384 , H01L29/4908
摘要： A display substrate includes an insulating substrate, a thin-film transistor (TFT), a pixel electrode, a signal line and a pad part. The insulating substrate has a display region and a peripheral region surrounding the display region. The TFT is in the display region of the insulating substrate. The pixel electrode is in the display region of the insulating substrate and electrically connected to the TFT. The signal line is on the insulating substrate and extends from the peripheral region toward the display region. The pad part is in the peripheral region and electrically connects to the signal line. The pad part is formed in a trench of the insulating substrate and includes a region that extends into the insulating substrate. Therefore, the signal line may be securely attached to the insulating substrate.
摘要翻译：显示基板包括绝缘基板，薄膜晶体管（TFT），像素电极，信号线和焊盘部分。绝缘基板具有显示区域和围绕显示区域的周边区域。 TFT位于绝缘基板的显示区域。像素电极在绝缘基板的显示区域中并与TFT电连接。信号线位于绝缘基板上，并从周边区域向显示区域延伸。焊盘部分在外围区域中并且电连接到信号线。衬垫部分形成在绝缘衬底的沟槽中，并且包括延伸到绝缘衬底中的区域。因此，信号线可以牢固地附接到绝缘基板。

15. 发明申请

US20090181226A1 METHOD FOR MANUFACTURING METAL LINE EMBEDDED IN SUBSTRATE AND METHOD FOR MANUFACTURING DISPLAY PANEL HAVING THE EMBEDDED METAL LINE 审中-公开
标题翻译：用于制造埋在基板中的金属线的方法和用于制造具有嵌入金属线的显示面板的方法
公开(公告)号：US20090181226A1
公开(公告)日：2009-07-16
申请号：US12354484
申请日：2009-01-15
申请人： Hong-Long Ning , Chang-Oh Jeong , Pil-Sang Yun , Byeong-Beom Kim , Je-Hun Lee , Do-Hyun Kim
发明人： Hong-Long Ning , Chang-Oh Jeong , Pil-Sang Yun , Byeong-Beom Kim , Je-Hun Lee , Do-Hyun Kim
IPC分类号： B32B7/00 , H01L21/44 , H01L21/02
CPC分类号： H05K3/1258 , H01L27/124 , H01L27/1292 , H05K1/0269 , H05K1/0306 , H05K3/0023 , H05K3/107 , H05K3/1216 , H05K2201/0108 , H05K2203/0126 , H05K2203/0139 , H05K2203/0557 , H05K2203/1131 , H05K2203/1554 , H05K2203/166 , Y10T428/24917
摘要： A method for manufacturing a metal line embedded in a substrate includes forming a trench in the substrate, bringing a stenciling plate having a through hole corresponding to the trench into contact with the substrate with the through hole being aligned to and exposing the trench, applying a fluidic and solidifiable metallic coating material through the through hole and into the trench, separating the stenciling plate from the substrate and solidifying the metallic coating material in the trench.
摘要翻译：一种嵌入衬底中的金属线的制造方法，包括：在衬底中形成沟槽，使具有对应于沟槽的通孔的模版板与衬底接触，其中通孔与沟槽对准并暴露沟槽，流体和可固化的金属涂层材料通过通孔并进入沟槽，将模板与基底分离并固化沟槽中的金属涂层材料。

16. 发明申请

US20090179203A1 DISPLAY SUBSTRATE 有权
标题翻译：显示基板
公开(公告)号：US20090179203A1
公开(公告)日：2009-07-16
申请号：US12331138
申请日：2008-12-09
申请人： Hong-Long Ning , Chang-Oh Jeong , Je-Hun Lee , Yang-Ho Bae , Pil-Sang Yun , Hong-Sick Park , Joo-Ae Youn , Byeong-Beom Kim , Byeong-Jin Lee
发明人： Hong-Long Ning , Chang-Oh Jeong , Je-Hun Lee , Yang-Ho Bae , Pil-Sang Yun , Hong-Sick Park , Joo-Ae Youn , Byeong-Beom Kim , Byeong-Jin Lee
IPC分类号： H01L33/00 , H01L21/768 , G03F1/00 , G03F7/20
CPC分类号： G02F1/136286 , G02F2001/136295 , H01L27/124 , H01L29/41733 , H01L29/42384 , H01L29/4908
摘要： A display substrate includes an insulating substrate, a thin-film transistor (TFT), a pixel electrode, a signal line and a pad part. The insulating substrate has a display region and a peripheral region surrounding the display region. The TFT is in the display region of the insulating substrate. The pixel electrode is in the display region of the insulating substrate and electrically connected to the TFT. The signal line is on the insulating substrate and extends from the peripheral region toward the display region. The pad part is in the peripheral region and electrically connects to the signal line. The pad part is formed in a trench of the insulating substrate and includes a region that extends into the insulating substrate. Therefore, the signal line may be securely attached to the insulating substrate.
摘要翻译：显示基板包括绝缘基板，薄膜晶体管（TFT），像素电极，信号线和焊盘部分。绝缘基板具有显示区域和围绕显示区域的周边区域。 TFT位于绝缘基板的显示区域。像素电极在绝缘基板的显示区域中并与TFT电连接。信号线位于绝缘基板上，并从周边区域向显示区域延伸。焊盘部分在外围区域中并且电连接到信号线。衬垫部分形成在绝缘衬底的沟槽中，并且包括延伸到绝缘衬底中的区域。因此，信号线可以牢固地附接到绝缘基板。

17. 发明授权

US08551307B2 Sputtering target apparatus 有权
标题翻译：溅射目标仪器
公开(公告)号：US08551307B2
公开(公告)日：2013-10-08
申请号：US12779459
申请日：2010-05-13
申请人： Do-Hyun Kim , Dong-Hoon Lee , Chang-Oh Jeong
发明人： Do-Hyun Kim , Dong-Hoon Lee , Chang-Oh Jeong
IPC分类号： C23C14/34
CPC分类号： C23C14/3407 , C23C14/3464 , H01J37/342 , H01J37/3435
摘要： A sputtering target apparatus is provided. The sputtering target apparatus includes a first target assembly including a first target array having a first target, a second target disposed adjacent to the first target, and a first target dividing region disposed between the first and second targets, the first target assembly extending along a first direction, wherein the first target dividing region has a longitudinal cross-section that is oblique with respect to the first direction.
摘要翻译：提供溅射靶设备。溅射靶设备包括：第一目标组件，其包括具有第一靶的第一靶阵列，与第一靶相邻设置的第二靶;以及设置在第一靶和第二靶之间的第一靶分离区，第一方向，其中第一目标分割区域具有相对于第一方向倾斜的纵向横截面。

18. 发明授权

US08455871B2 Thin film transistor array panel and method for manufacturing the same 有权
公开(公告)号：US08455871B2
公开(公告)日：2013-06-04
申请号：US12859792
申请日：2010-08-20
申请人： Chang-Oh Jeong , Woo-Sung Sohn , Dong-Gyu Kim , Shi-Yul Kim , Ki-Yeup Lee , Jean-Ho Song
发明人： Chang-Oh Jeong , Woo-Sung Sohn , Dong-Gyu Kim , Shi-Yul Kim , Ki-Yeup Lee , Jean-Ho Song
IPC分类号： H01L29/04
CPC分类号： H01L33/16 , H01L27/124 , H01L27/1288
摘要： A thin film transistor array panel is provided and includes a gate line, a gate insulating layer covering the gate line, a semiconductor layer disposed on the gate insulating layer, and a data line and a drain electrode disposed on the semiconductor layer. The data line and the drain electrode have a dual-layered structure including a lower layer and an upper layer with the lower layer having a first portion protruded outside the upper layer and the semiconductor layer having a second portion protruded outside the edge of the lower layer.

19. 发明授权

US08207534B2 Thin film transistor array panel and manufacturing method thereof 有权
标题翻译：薄膜晶体管阵列面板及其制造方法
公开(公告)号：US08207534B2
公开(公告)日：2012-06-26
申请号：US12417280
申请日：2009-04-02
申请人： Je-Hun Lee , Sung-Jin Kim , Hee-Joon Kim , Chang-Oh Jeong
发明人： Je-Hun Lee , Sung-Jin Kim , Hee-Joon Kim , Chang-Oh Jeong
IPC分类号： H01L29/786
CPC分类号： G02F1/13439 , G02F1/13458 , H01L27/12 , H01L27/124 , H01L29/458 , H01L29/4908
摘要： A thin film transistor array panel is provided, which includes a substrate, a plurality of gate line formed on the substrate, a plurality of common electrodes having a transparent conductive layer on the substrate, a gate insulating layer covering the gate lines and the common electrodes, a plurality of semiconductor layers formed on the gate insulating layer, a plurality of data lines including a plurality of source electrodes and formed on the semiconductor layer and the gate insulating layer, a plurality of drain electrodes formed on the semiconductor layer and the gate insulating layer, and a plurality of pixel electrodes overlapping the common electrodes and connected to the drain electrodes. Because the common electrodes are made of ITON, IZON, or a-ITON, or a double layer of ITO/ITON, IZO/IZON, or a-a-ITO/a-ITON, when H2 or SiH4 are injected to form a silicon nitride (SiNX) layer on the common electrodes, the opaque metal Sn or Zn in which the metal component is reduced in the IZO, ITO, or a-ITO is not produced on the surfaces of the common electrode.
摘要翻译：提供薄膜晶体管阵列面板，其包括基板，形成在基板上的多个栅极线，在基板上具有透明导电层的多个公共电极，覆盖栅极线和公共电极的栅极绝缘层形成在所述栅极绝缘层上的多个半导体层，形成在所述半导体层和所述栅极绝缘层上的多个源极电极的多条数据线，形成在所述半导体层上的多个漏电极和所述栅极绝缘体并且与公共电极重叠并连接到漏电极的多个像素电极。由于公共电极由ITON，IZON或者-IONON制成，或者是将双重层的ITO / ITON，IZO / IZON或者a-ITO / a-ITON，当注入H 2或SiH 4以形成氮化硅时 SiNX）层，在公共电极的表面上不产生在IZO，ITO或ITO中还原金属成分的不透明金属Sn或Zn。

20. 发明申请

US20110284857A1 THIN FILM TRANSISTOR ARRAY PANEL AND MANUFACTURING METHOD THEREOF 有权
标题翻译：薄膜晶体管阵列及其制造方法
公开(公告)号：US20110284857A1
公开(公告)日：2011-11-24
申请号：US13204553
申请日：2011-08-05
申请人： Je-Hun LEE , Sung-Jin Kim , Hee-Joon Kim , Chang-Oh Jeong
发明人： Je-Hun LEE , Sung-Jin Kim , Hee-Joon Kim , Chang-Oh Jeong
IPC分类号： H01L27/088 , H01L21/84
CPC分类号： G02F1/13439 , G02F1/13458 , H01L27/12 , H01L27/124 , H01L29/458 , H01L29/4908
摘要： A thin film transistor array panel is provided, which includes a substrate, a plurality of gate line formed on the substrate, a plurality of common electrodes having a transparent conductive layer on the substrate, a gate insulating layer covering the gate lines and the common electrodes, a plurality of semiconductor layers formed on the gate insulating layer, a plurality of data lines including a plurality of source electrodes and formed on the semiconductor layer and the gate insulating layer, a plurality of drain electrodes formed on the semiconductor layer and the gate insulating layer, and a plurality of pixel electrodes overlapping the common electrodes and connected to the drain electrodes. Because the common electrodes are made of ITON, IZON, or a-ITON, or a double layer of ITO/ITON, IZO/IZON, or a-a-ITO/a-ITON, when H2 or SiH4 are injected to form a silicon nitride (SiNX) layer on the common electrodes, the opaque metal Sn or Zn in which the rmetal component is reduced in the IZO, ITO, or a-ITO is not produced on the surfaces of the common electrode.
摘要翻译：提供薄膜晶体管阵列面板，其包括基板，形成在基板上的多个栅极线，在基板上具有透明导电层的多个公共电极，覆盖栅极线和公共电极的栅极绝缘层形成在所述栅极绝缘层上的多个半导体层，形成在所述半导体层和所述栅极绝缘层上的多个源极电极的多条数据线，形成在所述半导体层上的多个漏电极和所述栅极绝缘体并且与公共电极重叠并连接到漏电极的多个像素电极。由于公共电极由ITON，IZON或者-IONON制成，或者是将双重层的ITO / ITON，IZO / IZON或者a-ITO / a-ITON，当注入H 2或SiH 4以形成氮化硅时 SiNX）层，在公共电极的表面上不产生在IZO，ITO或ITO中还原金属成分的不透明金属Sn或Zn。

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