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    • 11. 发明专利
    • DE69535691D1
    • 2008-03-06
    • DE69535691
    • 1995-09-27
    • HITACHI LTD
    • YAMADA TSUTOMUKUROSAWA KENICHIKAMINAGA YASUOMASUI KOUJIOHASHI AKIHIRO
    • G06F13/40G06F1/18
    • There is provided an input/output device having of not exerting any adverse influence on other expansion devices connected to a system bus at the time of insertion or removal. An expansion device 800 comprises an electronic circuit 400 and a MOS switch 300, and is connected to a system bus (BUS) via a connector having long and short pins. The expansion device 800 two power supply systems, namely a stable power supply 250 and an unstable power supply 260. At the time of insertion or removal of the expansion device 800, power is provided to the MOS switch 300 and a high impedance maintaining circuit from the stable power supply via a pair of long pins, so as to reliably place the MOS switch 300 in a high impedance state, inside the expansion device the high impedance maintaining circuit 350 drives an open/close control terminal, and power is provided to the electronic circuit 400 from the unstable power supply 260. At the time of insertion or removal, adverse influence is not exerted on the signal transmission on the system bus, and effects of load variation on the main power supply are reduced.
    • 12. 发明专利
    • DE69535691T2
    • 2009-01-15
    • DE69535691
    • 1995-09-27
    • HITACHI LTD
    • YAMADA TSUTOMUKUROSAWA KENICHIKAMINAGA YASUOMASUI KOUJIOHASHI AKIHIRO
    • G06F13/40G06F1/18
    • There is provided an input/output device having of not exerting any adverse influence on other expansion devices connected to a system bus at the time of insertion or removal. An expansion device 800 comprises an electronic circuit 400 and a MOS switch 300, and is connected to a system bus (BUS) via a connector having long and short pins. The expansion device 800 two power supply systems, namely a stable power supply 250 and an unstable power supply 260. At the time of insertion or removal of the expansion device 800, power is provided to the MOS switch 300 and a high impedance maintaining circuit from the stable power supply via a pair of long pins, so as to reliably place the MOS switch 300 in a high impedance state, inside the expansion device the high impedance maintaining circuit 350 drives an open/close control terminal, and power is provided to the electronic circuit 400 from the unstable power supply 260. At the time of insertion or removal, adverse influence is not exerted on the signal transmission on the system bus, and effects of load variation on the main power supply are reduced.
    • 15. 发明专利
    • DE69032812T2
    • 1999-04-29
    • DE69032812
    • 1990-07-06
    • HITACHI LTD
    • KUROSAWA KENICHITANAKA SHIGEYANAKATSUKA YASUHIROBANDOH TADAAKI
    • G06F9/318G06F9/38G06F12/08G06F15/177
    • The described parallel processing apparatus and method turns a processing state discrimination flag (PE, 116) off, increases a program count by 1 at a time, reads out one instruction, and processes that instruction in an arithmetic unit, when it executes successivc processing of conventional software, and when it executes parallel processing of new software turns the processing state discrimination flag (PE, 116) on, increases the program count by m at a time, reads out m instructions, and exercises parallel processing over m instructions in m arithmetic units. In order to select either of the above described two kinds of processing, a discrimination changeover instruction having function of changing over the processing state discrimination flag (PE, 116) is added. The instructions are processed in one or in m arithmetic unit(s) (108, 109) in accordance with the processing state discrimination flag. In this way, successive processing and parallel processing are provided with compatibility and are selectively executed.
    • 18. 发明专利
    • DE69032812D1
    • 1999-01-21
    • DE69032812
    • 1990-07-06
    • HITACHI LTD
    • KUROSAWA KENICHITANAKA SHIGEYANAKATSUKA YASUHIROBANDOH TADAAKI
    • G06F9/318G06F9/38G06F12/08G06F15/177
    • The described parallel processing apparatus and method turns a processing state discrimination flag (PE, 116) off, increases a program count by 1 at a time, reads out one instruction, and processes that instruction in an arithmetic unit, when it executes successivc processing of conventional software, and when it executes parallel processing of new software turns the processing state discrimination flag (PE, 116) on, increases the program count by m at a time, reads out m instructions, and exercises parallel processing over m instructions in m arithmetic units. In order to select either of the above described two kinds of processing, a discrimination changeover instruction having function of changing over the processing state discrimination flag (PE, 116) is added. The instructions are processed in one or in m arithmetic unit(s) (108, 109) in accordance with the processing state discrimination flag. In this way, successive processing and parallel processing are provided with compatibility and are selectively executed.