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11. 发明申请

US20090140346A1 MATCHED ANALOG CMOS TRANSISTORS WITH EXTENSION WELLS 有权
标题翻译：具有扩展孔的匹配模拟CMOS晶体管
公开(公告)号：US20090140346A1
公开(公告)日：2009-06-04
申请号：US11948172
申请日：2007-11-30
申请人： Henry Litzmann Edwards , Hisashi Shichijo , Tathagata Chatterjee , Shyh-Horng Yang , Lance Stanford Robertson
发明人： Henry Litzmann Edwards , Hisashi Shichijo , Tathagata Chatterjee , Shyh-Horng Yang , Lance Stanford Robertson
IPC分类号： H01L27/092
CPC分类号： H01L21/823892 , H01L21/823814 , H01L27/0928
摘要： One embodiment of the invention relates to an integrated circuit. The integrated circuit includes a first matched transistor comprising: a first source region, a first drain region formed within a first drain well extension, and a first gate electrode having lateral edges about which the first source region and first drain region are laterally disposed. The integrated circuit also includes a second matched transistor comprising: a second source region, a second drain region formed within a second drain well extension, and a second gate electrode having lateral edges about which the second source region and second drain region are laterally disposed. Analog circuitry is associated with the first and second matched transistors, which analog circuitry utilizes a matching characteristic of the first and second matched transistors to facilitate analog functionality. Other devices, methods, and systems are also disclosed.
摘要翻译：本发明的一个实施例涉及集成电路。集成电路包括第一匹配晶体管，包括：第一源极区域，形成在第一漏极阱延伸部内的第一漏极区域和具有横向边缘的第一栅极电极，第一源极区域和第一漏极区域围绕第一源极区域横向设置。集成电路还包括第二匹配晶体管，其包括：第二源极区域，形成在第二漏极阱延伸部内的第二漏极区域和具有横向边缘的第二栅极电极，第二源极区域和第二漏极区域围绕第二源极区域横向设置。模拟电路与第一和第二匹配晶体管相关联，该模拟电路利用第一和第二匹配晶体管的匹配特性来促进模拟功能。还公开了其他装置，方法和系统。

12. 发明授权

US06764892B2 Device and method of low voltage SCR protection for high voltage failsafe ESD applications 有权
标题翻译：低压SCR保护装置和方法，用于高电压故障安全ESD应用
公开(公告)号：US06764892B2
公开(公告)日：2004-07-20
申请号：US10445743
申请日：2003-05-27
申请人： Keith E. Kunz , Charvaka Duvvury , Hisashi Shichijo
发明人： Keith E. Kunz , Charvaka Duvvury , Hisashi Shichijo
IPC分类号： H01L218238
CPC分类号： H01L27/0262 , H01L29/87
摘要： A semiconductor circuit for multi-voltage operation having built-in electrostatic discharge (ESD) protection is described, comprising a drain extended nMOS transistor and a pnpn silicon controlled rectifier (SCR) merged with the transistor so that a dual npn structure is created and both the source of the transistor and the cathode of the SCR are connected to electrical ground potential, forming a dual cathode, whereby the ESD protection is enhanced. The rectifier has a diffusion region, forming an abrupt junction, resistively coupled to the drain, whereby the electrical breakdown-to-substrate of the SCR can be triggered prior to the breakdown of the nMOS transistor drain. The SCR has anode and cathode regions spaced apart by semiconductor surface regions and insulating layers positioned over the surface regions with a thickness suitable for high voltage operation and ESD protection.
摘要翻译：描述了具有内置静电放电（ESD）保护的多电压操作的半导体电路，包括与晶体管合并的漏极扩展nMOS晶体管和pnpn可控硅整流器（SCR），从而产生双重npn结构，晶体管的源极和SCR的阴极连接到电接地电位，形成双阴极，从而增强了ESD保护。整流器具有形成突起结的扩散区，电阻耦合到漏极，由此可以在nMOS晶体管漏极击穿之前触发SCR的电击穿到衬底。 SCR具有由半导体表面区域隔开的阳极和阴极区域，并且位于表面区域上方的绝缘层具有适合于高电压操作和ESD保护的厚度。

13. 发明授权

US06753202B2 CMOS photodiode having reduced dark current and improved light sensitivity and responsivity 有权
标题翻译： CMOS光电二极管具有降低的暗电流和改善的光敏度和响应性
公开(公告)号：US06753202B2
公开(公告)日：2004-06-22
申请号：US10446910
申请日：2003-05-28
申请人： Zhiliang J. Chen , Kuok Y. Ling , Hisashi Shichijo , Katsuo Komatsuzaki , Chin-Yu Tsai
发明人： Zhiliang J. Chen , Kuok Y. Ling , Hisashi Shichijo , Katsuo Komatsuzaki , Chin-Yu Tsai
IPC分类号： H01L2100
CPC分类号： H01L31/1126 , H01L27/14643 , H01L27/148
摘要： A method for the fabrication of a light-sensing diode in a high-resistivity semiconductor substrate. A high-energy implant of ions into the substrate is patterned to form an annular well of the same conductivity type as the substrate; followed by a second high-energy implant of the opposite conductivity type, within the center of the annulus; followed by a third implant, of lower energy and high dosage, to form a region of the first conductivity type extending laterally near the substrate surface. The resulting diode junction is thereby patterned to include two planes near the substrate surface, allowing incident light to traverse the junction twice.
摘要翻译：一种在高电阻率半导体衬底中制造感光二极管的方法。将高能量离子注入到衬底中被图案化以形成与衬底相同的导电类型的环形阱; 之后是相对导电类型的第二高能量植入在环的中心内; 随后是较低能量和高剂量的第三种植入物，以形成在衬底表面附近横向延伸的第一导电类型的区域。由此形成的二极管结被图案化以包括靠近衬底表面的两个平面，允许入射光穿过接合两次。

14. 发明授权

US5595925A Method for fabricating a multiple well structure for providing multiple substrate bias for DRAM device formed therein 失效
标题翻译：制造用于为其中形成的DRAM器件提供多个衬底偏置的多阱结构的方法
公开(公告)号：US5595925A
公开(公告)日：1997-01-21
申请号：US236745
申请日：1994-04-29
申请人： Ih-Chin Chen , Hisashi Shichijo , Clarence W. Teng
发明人： Ih-Chin Chen , Hisashi Shichijo , Clarence W. Teng
IPC分类号： H01L21/8238 , H01L21/8226 , H01L21/8242 , H01L27/082 , H01L27/092 , H01L27/105 , H01L27/108 , H01L21/70 , H01L27/00
CPC分类号： H01L27/10805 , H01L27/105
摘要： A dynamic random access memory device (10) includes three separate sections--an input/output section (12), a peripheral transistor section (14), and a memory array section (16), all formed on a p- type substrate layer (18). The dynamic random access memory device (10) can employ separate substrate bias voltages for each section. The input/output section (12) has a p- type region (22) that is isolated from the p- type substrate layer (18) by an n-type well region (20). The peripheral transistor section (14) has a p- type region (36) that can be isolated from the p- type substrate layer (18) by an optional n- type well region (40) for those devices which require a different substrate bias voltage between the peripheral transistor section (14) and the memory array section (16).
摘要翻译：动态随机存取存储器件（10）包括三个单独的部分 - 输入/输出部分（12），外围晶体管部分（14）和存储器阵列部分（16），全部形成在p型衬底层 18）。动态随机存取存储器件（10）可以为每个部分采用单独的衬底偏置电压。输入/输出部分（12）具有通过n型阱区域（20）与p-型衬底层（18）隔离的p-型区域（22）。外围晶体管部分（14）具有p型区域（36），其可以通过可选的n型阱区域（40）与p型衬底层（18）隔离，用于那些需要不同衬底偏置的器件外围晶体管部分（14）和存储器阵列部分（16）之间的电压。

15. 发明授权

US4910164A Method of making planarized heterostructures using selective epitaxial growth 失效
标题翻译：使用选择性外延生长制作平面化异质结构的方法
公开(公告)号：US4910164A
公开(公告)日：1990-03-20
申请号：US224965
申请日：1988-07-27
申请人： Hisashi Shichijo
发明人： Hisashi Shichijo
IPC分类号： H01L21/302 , H01L21/20 , H01L21/31 , H01L21/338 , H01L29/812
CPC分类号： H01L21/02664 , H01L21/02381 , H01L21/0243 , H01L21/02546 , H01L21/02636 , Y10S148/026 , Y10S148/072 , Y10S148/10 , Y10S438/933 , Y10S438/951
摘要： A lift-off method for forming regions of a first semiconductor such as GaAs (104) in recesses in a substrate of a second semiconductor such as silicon (102) with the surface of the first semiconductor region (104) coplanar with the surface of the second semiconductor layer (102). Also, interconnected devices in both regions. Preferred embodiment methods include growth by molecular beam epitaxy of a layer of the first semiconductor on a masked and recessed substrate of the second semiconductor followed by photolithographic removal of the grown layer outside of a neighborhood of the recesses and lift-off (by mask etching) of the remainder of the grown layer outside of the recesses.

16. 发明授权

US07915905B2 Process and temperature insensitive flicker noise monitor circuit 有权
标题翻译：过程和温度不敏感的闪烁噪声监测电路
公开(公告)号：US07915905B2
公开(公告)日：2011-03-29
申请号：US12761544
申请日：2010-04-16
申请人： Baher S. Haroun , Gaurav Chandra , Vijaya Bhaskar Rentala , Venkatesh Srinivasan , Hisashi Shichijo , Krishnaswamy Nagaraj
发明人： Baher S. Haroun , Gaurav Chandra , Vijaya Bhaskar Rentala , Venkatesh Srinivasan , Hisashi Shichijo , Krishnaswamy Nagaraj
IPC分类号： G01R31/00
CPC分类号： H03M3/35 , H01L22/34 , H03M3/43 , H03M3/438
摘要： In an apparatus and method for monitoring defects in wafers, a monitoring circuit is fabricated on an area of each one of the wafers. The monitoring circuit includes representative devices that replicate similar devices located in a die area of the wafers. Defects if present in the representative devices contribute to a generation of a noise, thereby causing an imbalance in a differential signal measurable across selected ones of the representative devices. A digitizing circuit that uses a common mode voltage as a reference to measure the imbalance digitizes the differential signal to a digital signal, the digital signal being indicative of the noise generated by the defects. The digital signal is stored over a configurable time interval to form a digital bit stream. The digital bit stream is compared to a reference to determine whether the defeats are within an allowable range.
摘要翻译：在用于监测晶片中的缺陷的装置和方法中，在每个晶片的区域上制造监视电路。监测电路包括代表位于晶片的管芯区域中的类似器件的代表性器件。如果存在于代表性装置中的缺陷有助于产生噪声，从而导致在所选代表装置中可测量的差分信号的不平衡。使用共模电压作为参考来测量不平衡的数字化电路将差分信号数字化为数字信号，数字信号表示由缺陷产生的噪声。数字信号以可配置的时间间隔存储以形成数字比特流。将数字比特流与参考进行比较，以确定失败是否在允许的范围内。

17. 发明申请

US20090251164A1 PROCESS AND TEMPERATURE INSENSITIVE FLICKER NOISE MONITOR CIRCUIT 有权
标题翻译：过程和温度敏感型闪烁噪声监测电路
公开(公告)号：US20090251164A1
公开(公告)日：2009-10-08
申请号：US12061409
申请日：2008-04-02
申请人： Baher S. Haroun , Gaurav Chandra , Vijaya Bhaskar Rentala , Venkatesh Srinivasan , Hisashi Shichijo , Krishnaswamy Nagaraj
发明人： Baher S. Haroun , Gaurav Chandra , Vijaya Bhaskar Rentala , Venkatesh Srinivasan , Hisashi Shichijo , Krishnaswamy Nagaraj
IPC分类号： H01L21/66 , H03M3/00
CPC分类号： H03M3/35 , H01L22/34 , H03M3/43 , H03M3/438
摘要： In an apparatus and method for monitoring defects in wafers, a monitoring circuit is fabricated on an area of each one of the wafers. The monitoring circuit includes representative devices that replicate similar devices located in a die area of the wafers. Defects if present in the representative devices contribute to a generation of a noise, thereby causing an imbalance in a differential signal measurable across selected ones of the representative devices. A digitizing circuit that uses a common mode voltage as a reference to measure the imbalance digitizes the differential signal to a digital signal, the digital signal being indicative of the noise generated by the defects. The digital signal is stored over a configurable time interval to form a digital bit stream. The digital bit stream is compared to a reference to determine whether the defects are within an allowable range.
摘要翻译：在用于监测晶片中的缺陷的装置和方法中，在每个晶片的区域上制造监视电路。监测电路包括代表位于晶片的管芯区域中的类似器件的代表性器件。如果存在于代表性装置中的缺陷有助于产生噪声，从而导致在所选代表装置中可测量的差分信号的不平衡。使用共模电压作为参考来测量不平衡的数字化电路将差分信号数字化为数字信号，数字信号表示由缺陷产生的噪声。数字信号以可配置的时间间隔存储以形成数字比特流。将数字位流与参考值进行比较，以确定缺陷是否在允许范围内。

18. 发明授权

US06621064B2 CMOS photodiode having reduced dark current and improved light sensitivity and responsivity 有权
标题翻译： CMOS光电二极管具有降低的暗电流和改善的光敏度和响应性
公开(公告)号：US06621064B2
公开(公告)日：2003-09-16
申请号：US09848637
申请日：2001-05-03
申请人： Zhiliang J. Chen , Kuok Y. Ling , Hisashi Shichijo , Katsuo Komatsuzaki , Chin-Yu Tsai
发明人： Zhiliang J. Chen , Kuok Y. Ling , Hisashi Shichijo , Katsuo Komatsuzaki , Chin-Yu Tsai
IPC分类号： H01L3100
CPC分类号： H01L31/1126 , H01L27/14643 , H01L27/148
摘要： A light-sensing diode having improved efficiency due to an extended junction geometry that provides more than one level of interaction with the light input.
摘要翻译：一种感光二极管，由于延长的接合几何形状而提高了效率，提供了与光输入不止一个层次的交互作用。

19. 发明授权

US06576959B2 Device and method of low voltage SCR protection for high voltage failsafe ESD applications 有权
公开(公告)号：US06576959B2
公开(公告)日：2003-06-10
申请号：US09947272
申请日：2001-09-05
申请人： Keith E. Kunz , Charvaka Duvvury , Hisashi Shichijo
发明人： Keith E. Kunz , Charvaka Duvvury , Hisashi Shichijo
IPC分类号： H01L2362
CPC分类号： H01L27/0262
摘要： A semiconductor circuit for multi-voltage operation having built-in electrostatic discharge (ESD) protection is described, comprising a drain extended nMOS transistor and a pnpn silicon controlled rectifier (SCR) merged with the transistor so that a dual npn structure is created and both the source of the transistor and the cathode of the SCR are connected to electrical ground potential, forming a dual cathode, whereby the ESD protection is enhanced. The rectifier has a diffusion region, forming an abrupt junction, resistively coupled to the drain, whereby the electrical breakdown-to-substrate of the SCR can be triggered prior to the breakdown of the nMOS transistor drain. The SCR has anode and cathode regions spaced apart by semiconductor surface regions and insulating layers positioned over the surface regions with a thickness suitable for high voltage operation and ESD protection.

20. 发明授权

US5164917A Vertical one-transistor DRAM with enhanced capacitance and process for fabricating 失效
标题翻译：具有增强的电容和制造工艺的垂直单晶体管DRAM
公开(公告)号：US5164917A
公开(公告)日：1992-11-17
申请号：US741197
申请日：1991-07-30
申请人： Hisashi Shichijo
发明人： Hisashi Shichijo
IPC分类号： H01L21/8242 , H01L27/108
CPC分类号： H01L27/10876 , H01L27/10838 , Y10S257/906
摘要： One embodiment of the present invention is a one transistor DRAM cell having enhanced capacitance and minimized soft error rate by providing an ungrounded cell capacitor plate which is insulated from the substrate. The structure includes a vertical transistor on the sides of a vertical depression or trench in a substrate. In the bottom of the trench, a memory cell capacitor is fabricated. This capacitor includes a conductive polycrystalline silicon post through the middle of the capacitor, thereby increasing the surface area of the capacitor plates. This increases the capacitance of the memory cell capacitor.The ungrounded plate of the memory cell capacitor is fabricated in the trench and is insulated from the substrate. This ungrounded plate is connected to the vertical transistor via a polycrystalline silicone plug. Thus this embodiment of the present invention reduces soft error rate by providing a fully insulated ungrounded memory cell capacitor plate.
摘要翻译：本发明的一个实施例是通过提供与衬底绝缘的未接地单元电容器板，其具有增强的电容和最小化的软错误率的单晶体管DRAM单元。该结构包括在基板中的垂直凹陷或沟槽的侧面上的垂直晶体管。在沟槽的底部，制造存储单元电容器。该电容器包括穿过电容器中间的导电多晶硅柱，从而增加电容器板的表面积。这增加了存储单元电容器的电容。存储单元电容器的未接地板制造在沟槽中并与衬底绝缘。该未接地板通过多晶硅插头连接到垂直晶体管。因此，本发明的该实施例通过提供完全绝缘的非接地存储单元电容器板来降低软错误率。

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