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11. 发明申请

US20100140614A1 OXIDE SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME AND ACTIVE MATRIX SUBSTRATE 失效
标题翻译：氧化物半导体器件及其制造方法和有源矩阵衬底
公开(公告)号：US20100140614A1
公开(公告)日：2010-06-10
申请号：US12633577
申请日：2009-12-08
申请人： Hiroyuki Uchiyama , Tetsufumi Kawamura , Hironori Wakana
发明人： Hiroyuki Uchiyama , Tetsufumi Kawamura , Hironori Wakana
IPC分类号： H01L29/24 , H01L21/36
CPC分类号： H01L29/7869 , H01L21/02554 , H01L21/02565 , H01L21/02617 , H01L21/28291 , H01L27/10873 , H01L27/112 , H01L27/11206 , H01L27/1225 , H01L27/3262 , H01L51/5206
摘要： A phenomenon of change of a contact resistance between an oxide semiconductor and a metal depending on an oxygen content ratio in introduced gas upon depositing an oxide semiconductor film made of indium gallium zinc oxide, zinc tin oxide, or others in an oxide semiconductor thin-film transistor. A contact layer is formed with an oxygen content ratio of 10% or higher in a region from a surface, where the metal and the oxide semiconductor are contacted, down to at least 3 nm deep in depth direction, and a region to be a main channel layer is further formed with an oxygen content ratio of 10% or lower, so that a multilayered structure is formed, and both of ohmic characteristics to the electrode metal and reliability such as the suppression of threshold potential shift are achieved.
摘要翻译：在氧化物半导体薄膜中沉积由铟镓锌氧化物，氧化锌锡等制成的氧化物半导体膜时，导入气体中的氧含量比的氧化物半导体与金属之间的接触电阻发生变化的现象晶体管。在从金属和氧化物半导体接触的表面的区域的氧含量比为10％以上形成接触层，深度为深度至少3nm以下的区域进一步形成具有10％或更低的氧含量比的沟道层，从而形成多层结构，并且实现了与电极金属的欧姆特性和诸如抑制阈值电位移动之类的可靠性。

12. 发明授权

US07732273B2 Semiconductor device manufacturing method and semiconductor device 失效
标题翻译：半导体器件制造方法和半导体器件
公开(公告)号：US07732273B2
公开(公告)日：2010-06-08
申请号：US12213624
申请日：2008-06-23
申请人： Hiroyuki Uchiyama
发明人： Hiroyuki Uchiyama
IPC分类号： H01L21/8242 , H01L21/20
CPC分类号： H01L28/40 , H01L27/10852
摘要： A manufacturing method of a semiconductor device having a highly reliable capacitor, and the semiconductor device are provided. The semiconductor device manufacturing method according to the present invention includes: a first step of forming a first electrode of a capacitor on a semiconductor substrate; a second step of forming a capacitor insulating film on the whole surface including a side surface and an upper surface of the first electrode; a third step of forming a protection insulating film made of a material different from that of the capacitor insulating film, on the capacitor insulating film; a fourth step of removing the protection insulating film and the capacitor insulating film from the upper surface of the first electrode, by anisotropically etching the protection insulating film and the capacitor insulating film; a fifth step of removing the protection insulating film that remains on the side surface of the first electrode; and a sixth step of forming a second electrode of the capacitor on the capacitor insulating film, after removing the protection insulating film.
摘要翻译：提供具有高可靠性电容器的半导体器件的制造方法和半导体器件。根据本发明的半导体器件制造方法包括：在半导体衬底上形成电容器的第一电极的第一步骤; 在包括第一电极的侧表面和上表面的整个表面上形成电容器绝缘膜的第二步骤; 在电容器绝缘膜上形成由不同于电容器绝缘膜的材料制成的保护绝缘膜的第三步骤; 通过各向异性蚀刻保护绝缘膜和电容器绝缘膜，从第一电极的上表面去除保护绝缘膜和电容器绝缘膜的第四步骤; 去除保留在第一电极的侧表面上的保护绝缘膜的第五步骤; 以及在除去保护绝缘膜之后，在电容器绝缘膜上形成电容器的第二电极的第六步骤。

13. 发明申请

US20090261325A1 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20090261325A1
公开(公告)日：2009-10-22
申请号：US12423053
申请日：2009-04-14
申请人： Tetsufumi Kawamura , Takeshi Sato , Mutsuko Hatano , Hiroyuki Uchiyama
发明人： Tetsufumi Kawamura , Takeshi Sato , Mutsuko Hatano , Hiroyuki Uchiyama
IPC分类号： H01L29/786 , H01L21/336
CPC分类号： H01L27/1225 , H01L27/1214 , H01L27/127 , H01L29/7869
摘要： A metallic oxide semiconductor device with high performance and small variations. It is a field effect transistor using a metallic oxide film for the channel, which includes a channel region and a source region and comprises a drain region with a lower oxygen content than the channel region in the metallic oxide, in which the channel region exhibits semiconductor characteristics and the oxygen content decreases with depth below the surface.
摘要翻译：具有高性能和小变化的金属氧化物半导体器件。它是一种使用金属氧化物膜作为沟道的场效应晶体管，其包括沟道区和源极区，并且包括具有比金属氧化物中的沟道区更低的氧含量的漏区，其中沟道区表现出半导体特性和氧含量随着表面深度的减小而减小。

14. 发明申请

US20090121283A1 Semiconductor device and fabrication method of the same 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20090121283A1
公开(公告)日：2009-05-14
申请号：US12289372
申请日：2008-10-27
申请人： Hiroyuki Uchiyama
发明人： Hiroyuki Uchiyama
IPC分类号： H01L21/336 , H01L29/78
CPC分类号： H01L29/78642 , H01L27/12
摘要： A semiconductor device includes a substrate; a first insulating layer provided on the substrate; a conductive layer buried in the first insulating layer; a semiconductor pillar including a lower diffusion layer provided immediately above the conductive layer, the lower diffusion layer being electrically connected to the conductive layer, a semiconductor layer on the lower diffusion layer, and an upper diffusion layer on the semiconductor layer; a gate insulating film provided on a peripheral side surface of the semiconductor layer; a gate electrode provided on the gate insulating film; and a second insulating layer provided such that the gate electrode and a circumference of the semiconductor pillar are buried in the second insulating layer.
摘要翻译：半导体器件包括衬底; 设置在所述基板上的第一绝缘层; 埋入第一绝缘层中的导电层; 半导体柱，包括紧邻导电层上方的下扩散层，下扩散层与导电层电连接，下扩散层上的半导体层和半导体层上的上扩散层; 设置在所述半导体层的周边侧面上的栅极绝缘膜; 设置在所述栅极绝缘膜上的栅电极; 以及设置成使得栅电极和半导体柱的周边被埋在第二绝缘层中的第二绝缘层。

15. 发明授权

US07417291B2 Method for manufacturing semiconductor integrated circuit device 有权
标题翻译：半导体集成电路器件的制造方法
公开(公告)号：US07417291B2
公开(公告)日：2008-08-26
申请号：US11785463
申请日：2007-04-18
申请人： Hiroshi Kujirai , Kousuke Okuyama , Kazuhiro Hata , Kiyonori Oyu , Ryo Nagai , Hiroyuki Uchiyama , Takahiro Kumauchi , Teruhisa Ichise
发明人： Hiroshi Kujirai , Kousuke Okuyama , Kazuhiro Hata , Kiyonori Oyu , Ryo Nagai , Hiroyuki Uchiyama , Takahiro Kumauchi , Teruhisa Ichise
IPC分类号： H01L29/76
CPC分类号： H01L29/4983 , H01L21/28061 , H01L21/28247 , H01L21/76897 , H01L27/10811 , H01L27/10814 , H01L27/10873 , H01L29/4941
摘要： Disclosed is a technique for reducing the leak current by reducing contamination of metal composing a polymetal gate of a MISFET. Of a polycrystalline silicon film, a WN film, a W film, and a cap insulating film formed on a gate insulating film on a p-type well (semiconductor substrate), the cap insulating film, the W film, and the WN film are etched and the over-etching of the polycrystalline silicon film below them is performed. Then, a sidewall film is formed on sidewalls of these films. Thereafter, after etching the polycrystalline silicon film with using the sidewall film as a mask, a thermal treatment is performed in an oxidation atmosphere, by which a light oxide film is formed on the sidewall of the polycrystalline silicon film. As a result, the contamination on the gate insulating film due to the W and the W oxide can be reduced, and also, the diffusion of these materials into the semiconductor substrate (p-type well) and the resultant increase of the leak current can be prevented.
摘要翻译：公开了通过减少组成MISFET的多金属栅极的金属的污染来减少泄漏电流的技术。在p型阱（半导体衬底），帽绝缘膜，W膜和WN膜上的栅绝缘膜上形成的多晶硅膜，WN膜，W膜和帽绝缘膜是进行蚀刻，并对其下面的多晶硅膜进行过蚀刻。然后，在这些膜的侧壁上形成侧壁膜。此后，在以侧壁膜为掩模蚀刻多晶硅膜之后，在氧化气氛中进行热处理，在多晶硅膜的侧壁上形成有氧化膜。结果，可以减少由W和W氧化物引起的栅绝缘膜上的污染，并且这些材料向半导体衬底（p型阱）的扩散以及由此导致的漏电流的增加被阻止

16. 发明申请

US20080070394A1 Mos transistor in an active region 审中-公开
标题翻译： Mos晶体管在有源区
公开(公告)号：US20080070394A1
公开(公告)日：2008-03-20
申请号：US11976669
申请日：2007-10-26
申请人： Hiroyuki Uchiyama
发明人： Hiroyuki Uchiyama
IPC分类号： H01L21/3205
CPC分类号： H01L29/66583 , H01L27/10855 , H01L27/10873 , H01L27/10888 , H01L27/10891 , H01L29/66553
摘要： After an isolation region is formed using a field-forming silicon nitride film, this silicon nitride film is patterned, thereby a gate trench is formed. Next, a gate electrode material is buried into the gate trench, and this is etched back. Thereafter, the silicon nitride is removed, thereby a contact hole is formed. A contact plug is buried into this contact hole. With this arrangement, the contact plug can be formed without using a diffusion layer contact pattern. At the same time, the periphery of the contact plug substantially coincides with a boundary between the element isolation region and the active region. Accordingly, the active region can be reduced.
摘要翻译：在使用场致发射氮化硅膜形成隔离区之后，对该氮化硅膜进行构图，从而形成栅极沟槽。接下来，将栅极电极材料埋入栅极沟槽中，并将其蚀刻回来。此后，除去氮化硅，从而形成接触孔。接触塞被埋入该接触孔中。通过这种布置，可以在不使用扩散层接触图案的情况下形成接触插塞。同时，接触插塞的周边基本上与元件隔离区域和有源区域之间的边界一致。因此，能够减少有源区域。

17. 发明申请

US20070187783A1 Method for manufacturing semiconductor integrated circuit device 有权
标题翻译：半导体集成电路器件的制造方法
公开(公告)号：US20070187783A1
公开(公告)日：2007-08-16
申请号：US11785463
申请日：2007-04-18
申请人： Hiroshi Kujirai , Kousuke Okuyama , Kazuhiro Hata , Kiyonori Oyu , Ryo Nagai , Hiroyuki Uchiyama , Takahiro Kumauchi , Teruhisa Ichise
发明人： Hiroshi Kujirai , Kousuke Okuyama , Kazuhiro Hata , Kiyonori Oyu , Ryo Nagai , Hiroyuki Uchiyama , Takahiro Kumauchi , Teruhisa Ichise
IPC分类号： H01L29/94
CPC分类号： H01L29/4983 , H01L21/28061 , H01L21/28247 , H01L21/76897 , H01L27/10811 , H01L27/10814 , H01L27/10873 , H01L29/4941
摘要： Disclosed is a technique for reducing the leak current by reducing contamination of metal composing a polymetal gate of a MISFET. Of a polycrystalline silicon film, a WN film, a W film, and a cap insulating film formed on a gate insulating film on a p-type well (semiconductor substrate), the cap insulating film, the W film, and the WN film are etched and the over-etching of the polycrystalline silicon film below them is performed. Then, a sidewall film is formed on sidewalls of these films. Thereafter, after etching the polycrystalline silicon film with using the sidewall film as a mask, a thermal treatment is performed in an oxidation atmosphere, by which a light oxide film is formed on the sidewall of the polycrystalline silicon film. As a result, the contamination on the gate insulating film due to the W and the W oxide can be reduced, and also, the diffusion of these materials into the semiconductor substrate (p-type well) and the resultant increase of the leak current can be prevented.
摘要翻译：公开了通过减少组成MISFET的多金属栅极的金属的污染来减少泄漏电流的技术。在p型阱（半导体衬底），帽绝缘膜，W膜和WN膜上的栅绝缘膜上形成的多晶硅膜，WN膜，W膜和帽绝缘膜是进行蚀刻，并对其下面的多晶硅膜进行过蚀刻。然后，在这些膜的侧壁上形成侧壁膜。此后，在以侧壁膜为掩模蚀刻多晶硅膜之后，在氧化气氛中进行热处理，在多晶硅膜的侧壁上形成有氧化膜。结果，可以减少由W和W氧化物引起的栅绝缘膜上的污染，并且这些材料向半导体衬底（p型阱）的扩散以及由此导致的漏电流的增加被阻止

18. 发明申请

US20070063315A1 Semiconductor integrated circuit device and process for manufacturing the same 有权
标题翻译：半导体集成电路器件及其制造方法
公开(公告)号：US20070063315A1
公开(公告)日：2007-03-22
申请号：US11602178
申请日：2006-11-21
申请人： Hiroyuki Uchiyama , Hiraku Chakihara , Teruhisa Ichise , Michimoto Kaminaga
发明人： Hiroyuki Uchiyama , Hiraku Chakihara , Teruhisa Ichise , Michimoto Kaminaga
IPC分类号： H01L23/544
CPC分类号： H01L23/544 , G03F9/7076 , H01L21/30625 , H01L21/31053 , H01L21/76229 , H01L21/76819 , H01L21/78 , H01L22/34 , H01L23/585 , H01L27/0207 , H01L29/78 , H01L2223/54453 , H01L2924/0002 , H01L2924/00
摘要： A large area dummy pattern DL is formed in a layer underneath a target T2 region formed in a scribe region SR of a wafer. A small area dummy pattern in a lower layer and a small area dummy pattern Ds2 in an upper layer are disposed in a region where the inter-pattern space of a pattern (active regions L1, L2, L3, gate electrode 17), which functions as an element of a product region PR and scribe region SR, is wide. The small area dummy pattern Ds2 in the upper layer is offset by ½ pitch relative to the small area dummy pattern Ds in the lower layer.
摘要翻译：在形成在晶片的划片区域SR中的目标T 2区域下方的层中形成大面积的虚设图案DL。下层的小区域虚拟图案和上层的小区域虚设图案Ds 2设置在图案的图案间空间（有源区域L 1，L 2，L 3，栅极电极17 ）作为产品区域PR和划片区域SR的元素而起作用。上层中的小区域虚拟图案Ds 2相对于下层中的小区域虚拟图案Ds偏移1/2节距。

19. 发明授权

US07144766B2 Method of manufacturing semiconductor integrated circuit device having polymetal gate electrode 有权
标题翻译：具有多金属栅电极的半导体集成电路器件的制造方法
公开(公告)号：US07144766B2
公开(公告)日：2006-12-05
申请号：US11198858
申请日：2005-08-08
申请人： Naoki Yamamoto , Hiroyuki Uchiyama , Norio Suzuki , Eisuke Nishitani , Shin'ichiro Kimura , Kazuyuki Hozawa
发明人： Naoki Yamamoto , Hiroyuki Uchiyama , Norio Suzuki , Eisuke Nishitani , Shin'ichiro Kimura , Kazuyuki Hozawa
IPC分类号： H01L22/336 , H01L22/8234
CPC分类号： H01L21/28194 , H01L21/02057 , H01L21/02068 , H01L21/02071 , H01L21/0217 , H01L21/02211 , H01L21/0223 , H01L21/02238 , H01L21/02255 , H01L21/02271 , H01L21/28061 , H01L21/28176 , H01L21/28247 , H01L21/31662 , H01L21/67115 , H01L21/76838 , H01L21/823437 , H01L21/84 , H01L27/10814 , H01L27/10873 , H01L27/10894 , H01L27/1214 , H01L29/4941 , H01L29/518
摘要： When an oxidation treatment for regenerating a gate insulating film 6 is performed after forming gate electrodes 7A of a polymetal structure in which a WNx film and a W film are stacked on a polysilicon film, a wafer 1 is heated and cooled under conditions for reducing a W oxide 27 on the sidewall of each gate electrode 7A. As a result, the amount of the W oxide 27 to be deposited on the surface of the wafer 1 is reduced.
摘要翻译：当在多晶硅膜上堆叠WN薄膜和W膜的多金属结构的栅极电极7A之后进行用于再生栅极绝缘膜6的氧化处理时，晶片1 在用于还原每个栅电极7A的侧壁上的W氧化物27的条件下被加热和冷却。结果，沉积在晶片1的表面上的W氧化物27的量减少。

20. 发明申请

US20060097314A1 Semiconductor device and method of manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US20060097314A1
公开(公告)日：2006-05-11
申请号：US11264092
申请日：2005-11-02
申请人： Hiroyuki Uchiyama
发明人： Hiroyuki Uchiyama
IPC分类号： H01L29/94
CPC分类号： H01L27/10891 , H01L21/28061 , H01L27/10855 , H01L27/10876 , H01L27/10888 , H01L29/66621 , H01L29/7834
摘要： After an element isolation region is formed using a field-forming silicon nitride film, the silicon nitride film and a semiconductor substrate are patterned. Thereafter, the silicon nitride film and the semiconductor substrate are patterned, thereby forming a gate trench reaching the semiconductor substrate in an active region. Next, after a gate electrode is formed within a gate trench, the silicon nitride film is removed, thereby forming a contact hole. A contact plug is buried into this contact hole. Accordingly, a diffusion layer contact pattern becomes unnecessary, and the active region can be reduced. Because a gate electrode is buried in the gate trench, a gate length is increased, and a sub-threshold current can be reduced.
摘要翻译：在使用场致发射氮化硅膜形成元件隔离区之后，对氮化硅膜和半导体衬底进行图案化。此后，对氮化硅膜和半导体衬底进行构图，从而在活性区域形成到达半导体衬底的栅极沟槽。接下来，在栅极沟槽中形成栅电极之后，去除氮化硅膜，从而形成接触孔。接触塞被埋入该接触孔中。因此，不需要扩散层接触图案，可以减少有源区域。因为栅电极被埋在栅极沟槽中，栅极长度增加，并且可以减小次级阈值电流。

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