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11. 发明申请

US20080212370A1 NONVOLATILE SEMICONDUCTOR STORAGE DEVICE, NONVOLATILE SEMICONDUCTOR STORAGE SYSTEM AND METHOD OF MANAGING OF DEFECTIVE COLUMN IN NONVOLATILE SEMICONDUCTOR STORAGE SYSTEM 有权
标题翻译：非易失性半导体存储器件，非易失性半导体存储系统和非易失性半导体存储系统中缺陷管的管理方法
公开(公告)号：US20080212370A1
公开(公告)日：2008-09-04
申请号：US12040155
申请日：2008-02-29
申请人： Naoya Tokiwa
发明人： Naoya Tokiwa
IPC分类号： G11C16/06
CPC分类号： G11C16/06
摘要： A nonvolatile semiconductor storage device is disclosed, which includes a memory cell array in which nonvolatile memory cells are arranged, a first data holding circuit which temporarily holds a collective processing unit of read or write data to be simultaneously read from or written to the memory cells, a circuit which takes out the data held in the first data holding circuit from the device, and a second data holding circuit in which data is automatically set at a time when power supply is turned on and in which the data is changeable based on a command input to the device, wherein the collective processing unit is equal to a sum of the number of units used within the device and the maximum number of units continuously output from the device to outside or input to the device from outside.
摘要翻译：公开了一种非易失性半导体存储装置，其包括其中布置非易失性存储器单元的存储单元阵列，暂时保持要同时从存储单元读取或写入存储单元的读或写数据的集合处理单元的第一数据保持电路，从设备取出保存在第一数据保持电路中的数据的电路，以及第二数据保持电路，其中在电源接通时自动设置数据，并且其中数据可基于命令输入到所述设备，其中所述集体处理单元等于在所述设备内使用的单元数量与从所述设备连续输出到所述设备的外部或从外部输入到所述设备的单元的最大数量之和。

12. 发明申请

US20050201156A1 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE 失效
标题翻译：非易失性半导体存储器件
公开(公告)号：US20050201156A1
公开(公告)日：2005-09-15
申请号：US10874361
申请日：2004-06-24
申请人： Naoya Tokiwa
发明人： Naoya Tokiwa
IPC分类号： G11C16/02 , G11C16/06
CPC分类号： G11C16/22
摘要： A nonvolatile semiconductor memory device with a function of executing a verify operation for write data that is input from outside includes a memory cell array including memory cells arranged in a matrix, and a password storage area for storing password data, an input buffer that receives data input from outside, a first retaining circuit that retains input password data or write data, which is input to the input buffer, a verify sense amplifier that detects, at a time of the verify operation, the password data that is read out of the password storage area or data that is read out of the memory cell array, and a coincidence determination circuit that determines whether the input password data coincides with the read-out password data, or determines whether the write data coincides with the read-out data.
摘要翻译：具有执行从外部输入的写入数据的验证操作的功能的非易失性半导体存储器件包括：存储单元阵列，包括以矩阵形式排列的存储单元;以及用于存储密码数据的密码存储区域;接收数据的输入缓冲器来自外部的输入，保持输入到输入缓冲器的输入密码数据或写入数据的第一保持电路，在验证操作时检测从密码读出的密码数据的验证读出放大器存储区域或从存储单元阵列读出的数据，以及一致确定电路，其确定输入的密码数据是否与读出的密码数据一致，或者确定写入数据是否与读出的数据一致。

13. 发明授权

US06937524B2 Nonvolatile semiconductor memory device having a write control circuit 有权
标题翻译：具有写入控制电路的非易失性半导体存储器件
公开(公告)号：US06937524B2
公开(公告)日：2005-08-30
申请号：US10461995
申请日：2003-06-11
申请人： Hitoshi Shiga , Naoya Tokiwa
发明人： Hitoshi Shiga , Naoya Tokiwa
IPC分类号： G11C16/02 , G11C16/10 , G11C16/16 , G11C16/34 , G11C16/04
CPC分类号： G11C16/10 , G11C16/16 , G11C16/3436 , G11C2216/14
摘要： A non-volatile semiconductor memory device capable of performing page programming at high speeds is provided. This nonvolatile memory device includes a cell array with a matrix of rows and columns of electrically writable and erasable nonvolatile memory cells, and a write control circuit which writes or “programs” one-page data into this cell array at a plurality of addresses within one page. The write control circuit is operable to iteratively perform iteration of a write operation for the plurality of addresses corresponding to one page and iteration of a verify-read operation of the plurality of addresses after writing until verify-read check is passed with respect to every address involved. Regarding an address or addresses with no cells to be written any more, the write control circuit skips the write operation and the after-write verify-read operation.
摘要翻译：提供能够高速执行页面编程的非易失性半导体存储器件。这种非易失性存储器件包括具有电可写和可擦除非易失性存储单元的行和列的矩阵的单元阵列，以及一个写入控制电路，其在一个位置内的多个地址中将一页数据写入或“编程”到该单元阵列页。写入控制电路可操作以迭代地执行对应于一页的多个地址的写入操作和写入之后多个地址的验证读取操作的迭代，直到相对于每个地址通过验证读取检查涉及。关于不再写入单元的地址或地址，写入控制电路跳过写入操作和写入后验证读取操作。

14. 发明申请

US20120113719A1 NONVOLATILE SEMICONDUCTOR STORAGE DEVICE, NONVOLATILE SEMICONDUCTOR STORAGE SYSTEM AND METHOD OF MANAGING OF DEFECTIVE COLUMN IN NONVOLATILE SEMICONDUCTOR STORAGE SYSTEM 有权
标题翻译：非易失性半导体存储器件，非易失性半导体存储系统和非易失性半导体存储系统中缺陷管的管理方法
公开(公告)号：US20120113719A1
公开(公告)日：2012-05-10
申请号：US13353047
申请日：2012-01-18
申请人： Naoya Tokiwa
发明人： Naoya Tokiwa
IPC分类号： G11C16/06
CPC分类号： G11C16/06
摘要： A nonvolatile semiconductor storage device is disclosed, which includes a memory cell array in which nonvolatile memory cells are arranged, a first data holding circuit which temporarily holds a collective processing unit of read or write data to be simultaneously read from or written to the memory cells, a circuit which takes out the data held in the first data holding circuit from the device, and a second data holding circuit in which data is automatically set at a time when power supply is turned on and in which the data is changeable based on a command input to the device, wherein the collective processing unit is equal to a sum of the number of units used within the device and the maximum number of units continuously output from the device to outside or input to the device from outside.
摘要翻译：公开了一种非易失性半导体存储装置，其包括其中布置非易失性存储器单元的存储单元阵列，暂时保持要同时从存储单元读取或写入存储单元的读或写数据的集合处理单元的第一数据保持电路，从设备取出保存在第一数据保持电路中的数据的电路，以及第二数据保持电路，其中在电源接通时自动设置数据，并且其中数据可基于命令输入到所述设备，其中所述集体处理单元等于在所述设备内使用的单元数量与从所述设备连续输出到所述设备的外部或从外部输入到所述设备的单元的最大数量之和。

15. 发明授权

US08120957B2 Nonvolatile semiconductor storage device, nonvolatile semiconductor storage system and method of managing of defective column in nonvolatile semiconductor storage system 有权
标题翻译：非易失性半导体存储装置，非易失性半导体存储系统以及非易失性半导体存储系统中的有缺陷的列的管理方法
公开(公告)号：US08120957B2
公开(公告)日：2012-02-21
申请号：US12957466
申请日：2010-12-01
申请人： Naoya Tokiwa
发明人： Naoya Tokiwa
IPC分类号： G11C11/34 , G11C16/04
CPC分类号： G11C16/06
摘要： A nonvolatile semiconductor storage device is disclosed, which includes a memory cell array in which nonvolatile memory cells are arranged, a first data holding circuit which temporarily holds a collective processing unit of read or write data to be simultaneously read from or written to the memory cells, a circuit which takes out the data held in the first data holding circuit from the device, and a second data holding circuit in which data is automatically set at a time when power supply is turned on and in which the data is changeable based on a command input to the device, wherein the collective processing unit is equal to a sum of the number of units used within the device and the maximum number of units continuously output from the device to outside or input to the device from outside.
摘要翻译：公开了一种非易失性半导体存储装置，其包括其中布置非易失性存储器单元的存储单元阵列，暂时保持要同时从存储单元读取或写入存储单元的读或写数据的集合处理单元的第一数据保持电路，从设备取出保存在第一数据保持电路中的数据的电路，以及第二数据保持电路，其中在电源接通时自动设置数据，并且其中数据可基于命令输入到所述设备，其中所述集体处理单元等于在所述设备内使用的单元数量与从所述设备连续输出到所述设备的外部或从外部输入到所述设备的单元的最大数量之和。

16. 发明申请

US20110103135A1 NON-VOLATILE MEMORY DEVICE AND METHOD FOR WRITING DATA THERETO 有权
标题翻译：非易失性存储器件及其数据写入方法
公开(公告)号：US20110103135A1
公开(公告)日：2011-05-05
申请号：US13005582
申请日：2011-01-13
申请人： Toshiaki EDAHIRO , Kazushige Kanda , Naoya Tokiwa , Takuya Futatsuyama , Koji Hosono , Shigeo Ohshima
发明人： Toshiaki EDAHIRO , Kazushige Kanda , Naoya Tokiwa , Takuya Futatsuyama , Koji Hosono , Shigeo Ohshima
IPC分类号： G11C11/00
CPC分类号： H01L27/101 , G11C13/0007 , G11C13/004 , G11C13/0069 , G11C2013/0054 , G11C2013/009 , G11C2213/32 , G11C2213/72
摘要： The present invention provides a method for writing data to a non-volatile memory device having first wirings and second wirings intersecting one another and memory cells arranged at each intersection therebetween, each of the memory cells having a variable resistive element and a rectifying element connected in series. According to the method, the second wirings are charged to a certain voltage not less than a rectifying-element threshold value, prior to a rise in a selected first wiring. Then, a selected first wiring is charged to a voltage required for writing or erasing, after which a selected second wiring is discharged.
摘要翻译：本发明提供一种将数据写入非易失性存储器件的方法，该非易失性存储器件具有彼此相交的第一布线和第二布线以及布置在其间的每个交叉处的存储单元，每个存储单元具有可变电阻元件和整流元件系列。根据该方法，在所选择的第一布线中升高之前，将第二布线充电至不小于整流元件阈值的一定电压。然后，将所选择的第一布线充电到写入或擦除所需的电压，之后放电所选择的第二布线。

17. 发明授权

US07911845B2 Non-volatile semiconductor memory device 失效
标题翻译：非易失性半导体存储器件
公开(公告)号：US07911845B2
公开(公告)日：2011-03-22
申请号：US12350398
申请日：2009-01-08
申请人： Naoya Tokiwa , Masanobu Shirakawa
发明人： Naoya Tokiwa , Masanobu Shirakawa
IPC分类号： G11C16/04
CPC分类号： G11C29/12 , G11C16/04 , G11C16/10 , G11C29/1201 , G11C2029/2602
摘要： A non-volatile semiconductor memory device includes: a memory cell array having electrically rewritable and non-volatile memory cells arranged; a data register circuit configured to hold write data to be written into the memory cell array; and an address decode circuit configured to decode a write address signal and control the write data-loading in the data register circuit, the address decode circuit being settable in such a multiple selection mode that the same write data is loaded in multiple registers in the data register circuit in correspondence to multiple addresses.
摘要翻译：非易失性半导体存储器件包括：具有布置的电可重写和非易失性存储单元的存储单元阵列; 数据寄存器电路，被配置为保持要写入存储单元阵列的写入数据; 以及地址解码电路，被配置为对写入地址信号进行解码并且控制数据寄存器电路中的写入数据加载，地址解码电路可以以相同的写入数据被加载到数据中的多个寄存器的多重选择模式中被设置寄存器电路对应于多个地址。

18. 发明授权

US07800935B2 Resistance change memory device 有权
标题翻译：电阻变化记忆装置
公开(公告)号：US07800935B2
公开(公告)日：2010-09-21
申请号：US12252675
申请日：2008-10-16
申请人： Hiroshi Maejima , Katsuaki Isobe , Naoya Tokiwa , Satoru Takase , Yasuyuki Fukuda , Hideo Mukai , Tsuneo Inaba
发明人： Hiroshi Maejima , Katsuaki Isobe , Naoya Tokiwa , Satoru Takase , Yasuyuki Fukuda , Hideo Mukai , Tsuneo Inaba
IPC分类号： G11C11/00
CPC分类号： G11C13/0009 , G11C11/56 , G11C11/5678 , G11C13/0004 , G11C13/004 , G11C13/0064 , G11C13/0069 , G11C2211/5642 , G11C2213/11 , G11C2213/34 , G11C2213/56 , G11C2213/72
摘要： A resistance change memory device including memory cells arranged, the memory cell having a stable state with a high resistance value and storing in a non-volatile manner such multi-level data that at least three resistance values, R0, R1 and R2 (R0 ΔR2.
摘要翻译：一种包括存储单元的电阻变化存储器件，所述存储器单元具有具有高电阻值的稳定状态并且以非易失性方式存储这样的多电平数据：至少三个电阻值R0，R1和R2（R0 < R1 ＆Dgr; R2的关系。

19. 发明申请

US20100188920A1 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US20100188920A1
公开(公告)日：2010-07-29
申请号：US12693824
申请日：2010-01-26
申请人： Takuya FUTATSUYAMA , Naoya Tokiwa
发明人： Takuya FUTATSUYAMA , Naoya Tokiwa
IPC分类号： G11C5/14
CPC分类号： G11C5/147 , G11C16/30
摘要： A nonvolatile semiconductor memory device has an internal step-down power generation circuit and a memory circuit. The internal step-down power generation circuit generates a first internal power supply voltage from an external power supply voltage in an active state, and generates a second internal power supply voltage different from the first internal power supply voltage from the external power supply voltage in a standby state. The memory circuit includes a cell array containing a nonvolatile memory cell and a sense amplifier detecting data read from the cell array. The sense amplifier is supplied with a voltage generated by the internal step-down power generation circuit as an internal power supply voltage.
摘要翻译：非易失性半导体存储器件具有内部降压发电电路和存储电路。内部降压发电电路从活动状态的外部电源电压产生第一内部电源电压，并且从外部电源电压生成与第一内部电源电压不同的第二内部电源电压待机状态。存储电路包括一个包含非易失性存储单元的单元阵列和一个检测从该单元阵列读出的数据的读出放大器。感测放大器被提供有由内部降压发电电路产生的电压作为内部电源电压。

20. 发明授权

US07724573B2 Nonvolatile semiconductor storage device, nonvolatile semiconductor storage system and method of managing of defective column in nonvolatile semiconductor storage system 有权
标题翻译：非易失性半导体存储装置，非易失性半导体存储系统以及非易失性半导体存储系统中的有缺陷的列的管理方法
公开(公告)号：US07724573B2
公开(公告)日：2010-05-25
申请号：US12040155
申请日：2008-02-29
申请人： Naoya Tokiwa
发明人： Naoya Tokiwa
IPC分类号： G11C11/34 , G11C16/04
CPC分类号： G11C16/06
摘要： A nonvolatile semiconductor storage device is disclosed, which includes a memory cell array in which nonvolatile memory cells are arranged, a first data holding circuit which temporarily holds a collective processing unit of read or write data to be simultaneously read from or written to the memory cells, a circuit which takes out the data held in the first data holding circuit from the device, and a second data holding circuit in which data is automatically set at a time when power supply is turned on and in which the data is changeable based on a command input to the device, wherein the collective processing unit is equal to a sum of the number of units used within the device and the maximum number of units continuously output from the device to outside or input to the device from outside.
摘要翻译：公开了一种非易失性半导体存储装置，其包括其中布置非易失性存储器单元的存储单元阵列，暂时保持要同时从存储单元读取或写入存储单元的读或写数据的集合处理单元的第一数据保持电路，从设备取出保存在第一数据保持电路中的数据的电路，以及第二数据保持电路，其中在电源接通时自动设置数据，并且其中数据可基于命令输入到所述设备，其中所述集体处理单元等于在所述设备内使用的单元数量与从所述设备连续输出到所述设备的外部或从外部输入到所述设备的单元的最大数量之和。

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