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11. 发明授权

US5898608A Method for operating a ferroelectric memory 失效
标题翻译：用于操作铁电存储器的方法
公开(公告)号：US5898608A
公开(公告)日：1999-04-27
申请号：US787833
申请日：1997-01-23
申请人： Hiroshige Hirano , Tatsumi Sumi , Nobuyuki Moriwaki
发明人： Hiroshige Hirano , Tatsumi Sumi , Nobuyuki Moriwaki
IPC分类号： G11C11/22
CPC分类号： G11C11/22
摘要： In a ferroelectric memory of 1T1C configuration in which a memory cell consists of 1 transistor and 1 capacitor per bit, the capacitance of a dummy memory cell capacitor, i.e., the area occupied by the dummy memory cell capacitor is determined based on the capacitive characteristic of a main memory cell capacitor obtained when the main memory cell capacitor was repeatedly operated with both positive voltage and negative voltage until its capacitive characteristic presented no more change. Moreover, not only the main memory cell capacitor but also the dummy memory cell capacitor are operated with both positive voltage and negative voltage by using a power-source voltage, not a ground voltage, as a voltage for resetting the dummy memory cell capacitor. Consequently, the effect of an imprint on the ferroelectric capacitor is reduced, thereby preventing the malfunction of the ferroelectric memory.
摘要翻译：在1T1C配置的铁电存储器中，其中存储单元由1个晶体管和1个电容器组成，虚拟存储单元电容器的电容，即，由虚设存储单元电容器占据的面积是基于当主存储单元电容器以正电压和负电压重复操作直到其电容特性呈现不再改变时获得的主存储单元电容器。此外，不仅主存储单元电容器而且虚拟存储单元电容器都通过使用电源电压（而不是接地电压）作为用于复位虚拟存储单元电容器的电压而以正电压和负电压工作。因此，压电对铁电电容器的影响降低，从而防止铁电存储器的故障。

12. 再颁专利

USRE41879E1 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：USRE41879E1
公开(公告)日：2010-10-26
申请号：US12155392
申请日：2008-06-03
申请人： Shunichi Iwanari , Masahiko Sakagami , Hiroshige Hirano , Tetsuji Nakakuma , Takashi Miki , Yasushi Gohou , Kunisato Yamaoka , Yasuo Murakuki
发明人： Shunichi Iwanari , Masahiko Sakagami , Hiroshige Hirano , Tetsuji Nakakuma , Takashi Miki , Yasushi Gohou , Kunisato Yamaoka , Yasuo Murakuki
IPC分类号： G11C16/06
CPC分类号： G11C11/4076 , G11C7/1051 , G11C7/1063 , G11C2207/229
摘要： Provided is a semiconductor memory device compatible with a SRAM and capable of a high-speed data transfer operation while maintaining data reliability. An access to a memory core 6 starts when an external chip enable signal XCE performs a falling transition. Simultaneously, an external write enable signal XWE and an external address signal ADD are received, and a memory cell 1, in the memory core 6, corresponding to the received external address signal ADD is selected. When a data read-out from the memory cell 1 or a data write-in to the memory cell 1 is complete, a rewrite timer 7 is activated in accordance with a rising transition of an external chip enable signal XCE or a rising transition of the external write enable signal XWE for performing a data rewrite for the memory cell 1.
摘要翻译：提供了与SRAM兼容的半导体存储器件，并且能够在保持数据可靠性的同时进行高速数据传输操作。当外部芯片使能信号XCE执行下降转换时，对存储器核心6的访问开始。同时，接收外部写入使能信号XWE和外部地址信号ADD，并且选择与存储器核心6中对应于所接收的外部地址信号ADD的存储单元1。当从存储器单元1读出的数据或对存储器单元1的数据写入完成时，根据外部芯片使能信号XCE的上升转变或者上升沿的转换激活重写定时器7 用于对存储单元1执行数据重写的外部写使能信号XWE。

13. 发明授权

US07136313B2 Semiconductor storage device 有权
标题翻译：半导体存储设备
公开(公告)号：US07136313B2
公开(公告)日：2006-11-14
申请号：US11121939
申请日：2005-05-05
申请人： Yasuo Murakuki , Hiroshige Hirano , Yasushi Gohou , Masahiko Sakagami , Kunisato Yamaoka , Shunichi Iwanari , Tetsuji Nakakuma , Takashi Miki
发明人： Yasuo Murakuki , Hiroshige Hirano , Yasushi Gohou , Masahiko Sakagami , Kunisato Yamaoka , Shunichi Iwanari , Tetsuji Nakakuma , Takashi Miki
IPC分类号： G11C7/00 , G11C8/00
CPC分类号： G11C29/816 , G11C11/22 , G11C29/789 , G11C2029/4402
摘要： To provide a semiconductor storage device which can adapt to assembly processes involving different treatment temperatures, can become unrewritable when rewriting of data by the user is prohibited, negates the necessity for developing different semiconductor storage devices, and lowers development cost.A semiconductor storage device is provided with, as areas for storing faulty address information indicating a faulty area and operation mode setting information about the semiconductor storage device, a first setting function storage area 103 formed from electrically-rewritable nonvolatile memory and a second setting function storage area 102 formed from once-rewritable nonvolatile memory. Transfer of faulty address information to a faulty address register 111 and transfer of operation mode setting information to an operation mode register 110 are selectively performed.
摘要翻译：为了提供可以适应涉及不同处理温度的装配过程的半导体存储装置，当用户重写数据被禁止时，可以变得不可改变，否定了开发不同的半导体存储装置的必要性，并且降低了开发成本。半导体存储装置设置有用于存储指示故障区域的有缺陷的地址信息和关于半导体存储装置的操作模式设置信息的区域，由可重写非易失性存储器和第二设置功能存储器形成的第一设置功能存储区域103 区域102由一次性可重写的非易失性存储器形成。选择性地执行将故障地址信息传送到故障地址寄存器111和将操作模式设置信息传送到操作模式寄存器110。

14. 发明授权

US5751650A Electric signal supply circuit and semiconductor memory device 失效
标题翻译：电信号电路和半导体存储器件
公开(公告)号：US5751650A
公开(公告)日：1998-05-12
申请号：US724664
申请日：1996-10-01
申请人： Hiroshige Hirano , Tetsuji Nakakuma
发明人： Hiroshige Hirano , Tetsuji Nakakuma
IPC分类号： G11C5/06 , G11C11/22
CPC分类号： G11C11/22 , G11C5/063
摘要： In an electric signal supply circuit, a signal generating source and a plurality of circuit cells are connected to each other by a wire line through resistors. Signal wire lines from the signal generating source to the respective circuit cells are formed in the form of a pyramid, and therefore, delay time differences to the circuit cells are reduced. Since delay time differences in a signal to the circuit cells from the signal generating source which is disposed at ends of the plurality of circuit cells are smaller, a circuit operation is stable.
摘要翻译：在电信号供给电路中，信号发生源和多个电路单元通过电阻线通过有线线连接。从信号发生源到各个电路单元的信号线以金字塔的形式形成，因此减小了对电路单元的延迟时间差。由于设置在多个电路单元的端部的来自信号发生源的电路单元的信号的延迟时间差较小，电路操作稳定。

15. 发明授权

US07184344B2 Semiconductor device comprising a differential sense amplifier, a write column selection switch and a read column selection switch 有权
标题翻译：半导体器件包括差分读出放大器，写入列选择开关和读取列选择开关
公开(公告)号：US07184344B2
公开(公告)日：2007-02-27
申请号：US11062826
申请日：2005-02-23
申请人： Tetsuji Nakakuma , Hiroshige Hirano
发明人： Tetsuji Nakakuma , Hiroshige Hirano
IPC分类号： G11C7/00
CPC分类号： G11C7/12 , G11C7/065 , G11C11/419 , G11C2207/002 , H01L27/105 , H01L27/1052 , H01L27/10897
摘要： A semiconductor device includes a differential sense amplifier connected to a bit line, and a data transfer circuit including a column selection switch for turning ON/OFF the connection between a data line and the bit line. The semiconductor device incorporates one of the following features: the on-state resistance of the column selection switch being higher than that of a transistor array of the differential sense amplifier; separate provision of two column selection switches, one for read operation and the other for write operation; provision of a bit line additional capacitance and a connection control switch therefor; and provision of a data line dividing switch.
摘要翻译：一种半导体器件包括连接到位线的差分读出放大器，以及数据传输电路，包括用于接通/断开数据线与位线之间的连接的列选择开关。半导体器件包含以下特征之一：列选择开关的导通电阻高于差分读出放大器的晶体管阵列的导通电阻; 单独提供两个列选择开关，一个用于读操作，另一个用于写操作; 提供位线附加电容及其连接控制开关; 并提供数据线分割开关。

16. 发明申请

US20050265090A1 Semiconductor storage device 有权
标题翻译：半导体存储设备
公开(公告)号：US20050265090A1
公开(公告)日：2005-12-01
申请号：US11121939
申请日：2005-05-05
申请人： Yasuo Murakuki , Hiroshige Hirano , Yasushi Gohou , Masahiko Sakagami , Kunisato Yamaoka , Shunichi Iwanari , Tetsuji Nakakuma , Takashi Miki
发明人： Yasuo Murakuki , Hiroshige Hirano , Yasushi Gohou , Masahiko Sakagami , Kunisato Yamaoka , Shunichi Iwanari , Tetsuji Nakakuma , Takashi Miki
IPC分类号： G11C11/22 , G11C7/00 , G11C29/00 , G11C29/12
CPC分类号： G11C29/816 , G11C11/22 , G11C29/789 , G11C2029/4402
摘要： To provide a semiconductor storage device which can adapt to assembly processes involving different treatment temperatures, can become unrewritable when rewriting of data by the user is prohibited, negates the necessity for developing different semiconductor storage devices, and lowers development cost. A semiconductor storage device is provided with, as areas for storing faulty address information indicating a faulty area and operation mode setting information about the semiconductor storage device, a first setting function storage area 103 formed from electrically-rewritable nonvolatile memory and a second setting function storage area 102 formed from once-rewritable nonvolatile memory. Transfer of faulty address information to a faulty address register 111 and transfer of operation mode setting information to an operation mode register 110 are selectively performed.
摘要翻译：为了提供可以适应涉及不同处理温度的装配过程的半导体存储装置，当用户重写数据被禁止时，可以变得不可改变，否定了开发不同的半导体存储装置的必要性，并且降低了开发成本。半导体存储装置设置有用于存储指示故障区域的有缺陷的地址信息和关于半导体存储装置的操作模式设置信息的区域，由可重写非易失性存储器和第二设置功能存储器形成的第一设置功能存储区域103 区域102由一次性可重写的非易失性存储器形成。选择性地执行将故障地址信息传送到故障地址寄存器111和将操作模式设置信息传送到操作模式寄存器110。

17. 发明申请

US20050141307A1 Semiconductor device comprising a differential sense amplifier, a write column selection switch and a read column selection switch 有权
公开(公告)号：US20050141307A1
公开(公告)日：2005-06-30
申请号：US11062826
申请日：2005-02-23
申请人： Tetsuji Nakakuma , Hiroshige Hirano
发明人： Tetsuji Nakakuma , Hiroshige Hirano
IPC分类号： H01L21/8242 , G11C7/06 , G11C11/407 , G11C11/409 , G11C11/419 , H01L21/8239 , H01L27/105 , H01L27/108 , G11C11/34
CPC分类号： G11C7/12 , G11C7/065 , G11C11/419 , G11C2207/002 , H01L27/105 , H01L27/1052 , H01L27/10897
摘要： A semiconductor device includes a differential sense amplifier connected to a bit line, and a data transfer circuit including a column selection switch for turning ON/OFF the connection between a data line and the bit line. The semiconductor device incorporates one of the following features: the on-state resistance of the column selection switch being higher than that of a transistor array of the differential sense amplifier; separate provision of two column selection switches, one for read operation and the other for write operation; provision of a bit line additional capacitance and a connection control switch therefor; and provision of a data line dividing switch.

18. 发明授权

US07307866B2 Ferroelectric memory and method for reading data from the ferroelectric memory 有权
标题翻译：铁电存储器和从铁电存储器读取数据的方法
公开(公告)号：US07307866B2
公开(公告)日：2007-12-11
申请号：US11132196
申请日：2005-05-19
申请人： Kunisato Yamaoka , Hiroshige Hirano , Yasushi Gohou , Shunichi Iwanari , Yasuo Murakuki , Masahiko Sakagami , Tetsuji Nakakuma , Takashi Miki
发明人： Kunisato Yamaoka , Hiroshige Hirano , Yasushi Gohou , Shunichi Iwanari , Yasuo Murakuki , Masahiko Sakagami , Tetsuji Nakakuma , Takashi Miki
IPC分类号： G11C11/22 , G11C11/42 , G11C5/14 , G11C7/00 , G11C7/02
CPC分类号： G11C11/22
摘要： A ferroelectric memory of the present invention comprises: a plurality of normal cells, each of which includes a first ferroelectric capacitor for holding data and a first transistor connected to a first electrode of the first ferroelectric capacitor; a first bit line connected to the first transistor; a first bit line precharge circuit which is a switch circuit provided between the first bit line and a ground; and a word line connected to a gate of the first transistor. The word line is deactivated to disconnect the first ferroelectric capacitor from the first bit line before the first bit line precharge circuit is driven to discharge a potential of the first bit line.
摘要翻译：本发明的铁电存储器包括：多个正常单元，每个单元包括用于保持数据的第一铁电电容器和连接到第一铁电电容器的第一电极的第一晶体管; 连接到第一晶体管的第一位线; 第一位线预充电电路，其是设置在第一位线和地之间的开关电路; 以及连接到第一晶体管的栅极的字线。在驱动第一位线预充电电路以放电第一位线的电位之前，字线被去激活以将第一铁电电容器与第一位线断开。

19. 发明授权

US07280406B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US07280406B2
公开(公告)日：2007-10-09
申请号：US11344199
申请日：2006-02-01
申请人： Shunichi Iwanari , Masahiko Sakagami , Hiroshige Hirano , Tetsuji Nakakuma , Takashi Miki , Yasushi Gohou , Kunisato Yamaoka , Yasuo Murakuki
发明人： Shunichi Iwanari , Masahiko Sakagami , Hiroshige Hirano , Tetsuji Nakakuma , Takashi Miki , Yasushi Gohou , Kunisato Yamaoka , Yasuo Murakuki
IPC分类号： G11C16/06
CPC分类号： G11C11/4076 , G11C7/1051 , G11C7/1063 , G11C2207/229
摘要： Provided is a semiconductor memory device compatible with a SRAM and capable of a high-speed data transfer operation while maintaining data reliability. An access to a memory core 6 starts when an external chip enable signal XCE performs a falling transition. Simultaneously, an external write enable signal XWE and an external address signal ADD are received, and a memory cell 1, in the memory core 6, corresponding to the received external address signal ADD is selected. When a data read-out from the memory cell 1 or a data write-in to the memory cell 1 is complete, a rewrite timer 7 is activated in accordance with a rising transition of an external chip enable signal XCE or a rising transition of the external write enable signal XWE for performing a data rewrite for the memory cell 1.
摘要翻译：提供了与SRAM兼容的半导体存储器件，并且能够在保持数据可靠性的同时进行高速数据传输操作。当外部芯片使能信号XCE执行下降转换时，对存储器核心6的访问开始。同时，接收外部写入使能信号XWE和外部地址信号ADD，并且选择与存储器核心6中对应于所接收的外部地址信号ADD的存储单元1。当从存储器单元1读出的数据或对存储器单元1的数据写入完成时，根据外部芯片使能信号XCE的上升转变或者上升沿的转换激活重写定时器7 用于对存储单元1执行数据重写的外部写使能信号XWE。

20. 发明授权

US06888759B2 Semiconductor device comprising a differential sense amplifier, a write column selection switch and a read column selection switch 有权
标题翻译：半导体器件包括差分读出放大器，写入列选择开关和读取列选择开关
公开(公告)号：US06888759B2
公开(公告)日：2005-05-03
申请号：US10644744
申请日：2003-08-21
申请人： Tetsuji Nakakuma , Hiroshige Hirano
发明人： Tetsuji Nakakuma , Hiroshige Hirano
IPC分类号： H01L21/8242 , G11C7/06 , G11C11/407 , G11C11/409 , G11C11/419 , H01L21/8239 , H01L27/105 , H01L27/108 , G11C7/00
CPC分类号： G11C7/12 , G11C7/065 , G11C11/419 , G11C2207/002 , H01L27/105 , H01L27/1052 , H01L27/10897
摘要： A semiconductor device includes a differential sense amplifier connected to a bit line, and a data transfer circuit including a column selection switch for turning ON/OFF the connection between a data line and the bit line. The semiconductor device incorporates one of the following features: the on-state resistance of the column selection switch being higher than that of a transistor array of the differential sense amplifier; separate provision of two column selection switches, one for read operation and the other for write operation; provision of a bit line additional capacitance and a connection control switch therefor; and provision of a data line dividing switch.
摘要翻译：一种半导体器件包括连接到位线的差分读出放大器，以及数据传输电路，包括用于接通/断开数据线与位线之间的连接的列选择开关。半导体器件包含以下特征之一：列选择开关的导通电阻高于差分读出放大器的晶体管阵列的导通电阻; 单独提供两个列选择开关，一个用于读操作，另一个用于写操作; 提供位线附加电容及其连接控制开关; 并提供数据线分割开关。

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