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11. 发明授权

US06674675B2 Semiconductor device with flexible redundancy system 失效
标题翻译：具有灵活冗余系统的半导体器件
公开(公告)号：US06674675B2
公开(公告)日：2004-01-06
申请号：US10348964
申请日：2003-01-23
申请人： Satoru Takase
发明人： Satoru Takase
IPC分类号： G11C700
CPC分类号： G11C29/808 , G11C29/812
摘要： A memory cell array includes spare elements for saving a defective cell. Fuse sets each contain a defective address and mapping information indicative of the relationship between the fuse sets and the spare elements. When the defective address matches an input address, each fuse set outputs a signal for activating a corresponding spare element. The number of the fuse sets within a chip is smaller than the number of the spare elements.
摘要翻译：存储单元阵列包括用于保存有缺陷单元的备用元件。熔丝组每个都包含有缺陷的地址和指示熔丝组与备用元件之间的关系的映射信息。当缺陷地址与输入地址相匹配时，每个保险丝组输出用于激活相应备用元件的信号。芯片内的熔丝组数量小于备用元件的数量。

12. 发明授权

US06542420B2 Semiconductor device with flexible redundancy system 失效
公开(公告)号：US06542420B2
公开(公告)日：2003-04-01
申请号：US09953307
申请日：2001-09-17
申请人： Satoru Takase
发明人： Satoru Takase
IPC分类号： G11C700
CPC分类号： G11C29/808 , G11C29/812
摘要： A memory cell array includes spare elements for saving a defective cell. Fuse sets each contain a defective address and mapping information indicative of the relationship between the fuse sets and the spare elements. When the defective address matches an input address, each fuse set outputs a signal for activating a corresponding spare element. The number of the fuse sets within a chip is smaller than the number of the spare elements.

13. 发明授权

US5500815A Semiconductor memory 失效
标题翻译：半导体存储器
公开(公告)号：US5500815A
公开(公告)日：1996-03-19
申请号：US981541
申请日：1992-11-25
申请人： Satoru Takase , Tohru Furuyama
发明人： Satoru Takase , Tohru Furuyama
IPC分类号： G11C11/401 , G11C11/404 , G11C11/405 , G11C11/56 , H01L21/8242 , H01L27/10 , H01L27/108 , G11C11/24 , G11C11/40
CPC分类号： G11C11/565 , G11C11/404 , H01L27/10805
摘要： A semiconductor memory cell comprises a first cascade gate, formed on a semiconductor substrate, having its end connected to a first node, and a plurality of MOS transistors which are connected in cascade, a plurality of data storage capacitors, formed on the semiconductor substrate, each of which has its end connected to that end of a corresponding one of the MOS transistors which is opposite to the first node, and a device isolation MOS transistor formed between the memory cell and another semiconductor memory cell which are arranged side by side on the semiconductor substrate.
摘要翻译：半导体存储单元包括形成在半导体衬底上的第一级联栅极，其端部连接到第一节点，以及串联连接的多个MOS晶体管，形成在半导体衬底上的多个数据存储电容器，其每个端部连接到与第一节点相对的相应的一个MOS晶体管的端部，以及形成在存储单元和另一半导体存储单元之间的器件隔离MOS晶体管，它们并排布置在半导体衬底。

14. 发明授权

US08446749B2 Resistance change memory device 有权
标题翻译：电阻变化记忆装置
公开(公告)号：US08446749B2
公开(公告)日：2013-05-21
申请号：US13407001
申请日：2012-02-28
申请人： Satoru Takase
发明人： Satoru Takase
IPC分类号： G11C5/02
CPC分类号： G11C13/0007 , G11C7/12 , G11C13/0023 , G11C13/0026 , G11C13/0038 , G11C13/0069 , G11C2013/0088 , G11C2213/32 , G11C2213/71 , G11C2213/72 , H01L27/101
摘要： A resistance change memory device including: a cell array having a resistance change type of memory cells disposed at the cross-points of word lines and bit lines, the resistance value of the memory cell being reversibly settable; a word line driver circuit configured to apply a selecting drive voltage to one selected in the word lines; and a bit line driver circuit configured to drive multiple bit lines in such a manner that a set mode and a reset mode are set simultaneously for multiple memory cells selected by the selected word line, the set mode being for changing a selected memory cell from a first resistance state into a second resistance state while the reset mode is for changing a selected memory cell from the second resistance state into the first resistance state.
摘要翻译：一种电阻变化存储装置，包括：具有设置在字线和位线的交叉点的存储单元的电阻变化型的单元阵列，可逆地设定存储单元的电阻值; 字线驱动器电路，被配置为向所述字线中选择的一个施加选择驱动电压; 以及位线驱动电路，其被配置为以这样的方式驱动多个位线，使得对于由所选择的字线选择的多个存储器单元同时设置设置模式和复位模式，所述设置模式用于将选择的存储器单元从第一电阻状态变为第二电阻状态，而复位模式用于将所选择的存储单元从第二电阻状态改变为第一电阻状态。

15. 发明授权

US07800967B2 Semiconductor memory device and driving method thereof 有权
标题翻译：半导体存储器件及其驱动方法
公开(公告)号：US07800967B2
公开(公告)日：2010-09-21
申请号：US12324953
申请日：2008-11-28
申请人： Satoru Takase , Shigeo Ohshima
发明人： Satoru Takase , Shigeo Ohshima
IPC分类号： G11C7/00
CPC分类号： G11C16/10 , G11C7/06 , G11C11/5628 , G11C11/5642 , G11C16/0483 , G11C16/26 , G11C16/3418
摘要： This disclosure concerns a memory including: word lines extending to a first direction; bit lines extending to a second direction crossing the first direction; a memory cell array including cell blocks each including memory cells respectively provided corresponding to intersection points of the word lines and the bit lines; and sense amplifiers provided corresponding to the bit lines, wherein the sense amplifiers copies existing data stored in a first cell block within the memory cell array to a plurality of memory cells, the memory cells being included in second and third cell blocks different from the first cell block, and alternately arranged in an extension direction of the word lines and also alternately arranged in an extension direction of the bit lines, and the sense amplifiers reads data from the second cell block or the third cell block, at a time of outputting data to outside of the sense amplifiers.
摘要翻译：本公开涉及一种存储器，包括：延伸到第一方向的字线; 位线延伸到与第一方向交叉的第二方向; 包括单元块的存储单元阵列，每个单元块包括分别对应于字线和位线的交点提供的存储单元; 以及对应于所述位线的感测放大器，其中所述感测放大器将存储在所述存储单元阵列内的第一单元块中的现有数据复制到多个存储器单元，所述存储单元包括在与所述第一和第三单元块不同的第二和第三单元块中并且在字线的延伸方向上交替布置，并且还在位线的延伸方向上交替布置，并且读出放大器在输出数据时从第二单元块或第三单元块读取数据到感应放大器外面。

16. 发明申请

US20100091551A1 SEMICONDUCTOR STORAGE DEVICE 有权
标题翻译：半导体存储设备
公开(公告)号：US20100091551A1
公开(公告)日：2010-04-15
申请号：US12556272
申请日：2009-09-09
申请人： Koji Hosono , Satoru Takase
发明人： Koji Hosono , Satoru Takase
IPC分类号： G11C11/00 , G11C7/06
CPC分类号： G11C13/0064 , G11C13/0004 , G11C13/0011 , G11C13/0069 , G11C2013/0078 , G11C2213/71 , G11C2213/72
摘要： A semiconductor storage device includes: a memory cell array having memory cells; and a control circuit configured to apply a first voltage to a selected one of first wirings as well as a second voltage to a selected one of second wirings. The control circuit includes: a signal output circuit configured to output a first signal based on a first current flowing through a selected memory cell and a reference current; and a current retaining circuit configured to retain a second current flowing through the first wirings or a wiring electrically connected to the first wirings during a certain period of time. The signal output circuit is configured to determine the first current based on the second current retained by the current retaining circuit. The control circuit is configured to stop application of the first voltage to the first wirings based on the first signal.
摘要翻译：半导体存储装置包括：具有存储单元的存储单元阵列; 以及控制电路，被配置为将第一电压施加到所选择的第一布线中的一个，以及将第二电压施加到所选择的第二布线中的一个。控制电路包括：信号输出电路，被配置为基于流过所选择的存储单元的第一电流和参考电流来输出第一信号; 以及电流保持电路，其被配置为在一定时间段期间保持流过所述第一布线的第二电流或电连接到所述第一布线的布线。信号输出电路被配置为基于由电流保持电路保持的第二电流来确定第一电流。控制电路被配置为基于第一信号停止将第一电压施加到第一布线。

17. 发明授权

US07492649B2 Systems and methods for improving memory reliability by selectively enabling word line signals 有权
标题翻译：通过选择性地启用字线信号来提高存储器可靠性的系统和方法
公开(公告)号：US07492649B2
公开(公告)日：2009-02-17
申请号：US11558045
申请日：2006-11-09
申请人： Satoru Takase
发明人： Satoru Takase
IPC分类号： G11C7/00
CPC分类号： G11C5/143 , G11C8/08 , G11C11/417
摘要： Systems and methods for reducing instability and writability problems arising from relative variations between a memory cell voltage (Vcell) and a logic voltage (Vdd) by inhibiting assertion of word line signals that enable accesses to the memory cells when the voltages are not within an acceptable operating range. One embodiment comprises a system having a critical condition detector configured to monitor the voltages and to determine whether the voltages are within an acceptable range. When the voltages are not within the acceptable range, the system inhibits assertion of the word lines to the memory cells. Memory accesses which fail because of the inhibited word line signals are retried by a memory controller when the critical conditions that caused the signals to be inhibited no longer exist.
摘要翻译：用于通过禁止当电压不在可接受的范围内访问存储器单元的字线信号的断言来减少由存储器单元电压（Vcell）和逻辑电压（Vdd）之间的相对变化引起的不稳定性和可编写性问题的系统和方法工作范围。一个实施例包括具有临界状态检测器的系统，其被配置为监视电压并确定电压是否在可接受的范围内。当电压不在可接受范围内时，系统禁止对存储单元的字线断言。当导致信号被禁止的关键条件不再存在时，由存储器控制器重试由于禁止字线信号而失败的存储器访问。

18. 发明授权

US07400213B2 System and method for configuring conductors within an integrated circuit to reduce impedance variation caused by connection bumps 失效
标题翻译：用于在集成电路内配置导体以减少由连接凸起引起的阻抗变化的系统和方法
公开(公告)号：US07400213B2
公开(公告)日：2008-07-15
申请号：US11137296
申请日：2005-05-25
申请人： Satoru Takase
发明人： Satoru Takase
IPC分类号： H03H7/38
CPC分类号： H01L23/64 , H01L23/5286 , H01L2924/0002 , H01L2924/3011 , H01P5/02 , H01L2924/00
摘要： Systems and methods for improved semiconductor device performance are disclosed. In particular, presented are improved semiconductor systems and methods for configuring conductors to reduce impedance variation caused by proximity and/or density and/or operation of connection-bumps. The invention includes adding impedance-reducing conductive features which add no additional functionality to the semiconductor device. The added features may be arranged in areas of sparse connection-bump density. Impedance-reducing conductive features may include metal lines added between functional metal lines, where placement between adjacent functional lines may vary. Impedance-reducing conductive features may be added to any one or combination of conductive layers, and added features may act upon any one or combination of functional features. Further, added features may be electrically active and responsive to semiconductor device operation. Also, methods for determining connection-bump density, which methods may be automated.
摘要翻译：公开了用于改善半导体器件性能的系统和方法。具体地，提出了改进的半导体系统和用于配置导体以减少由接近和/或密度和/或连接凸块的操作引起的阻抗变化的方法。本发明包括增加阻抗减小的导电特征，其不对半导体器件增加额外的功能。附加的特征可以布置在稀疏连接 - 凸起密度的区域中。阻抗减小的导电特征可以包括在功能金属线之间添加的金属线，其中相邻功能线之间的放置可以变化。阻抗减小的导电特征可以被添加到导电层的任何一个或组合，并且附加的特征可以作用于功能特征的任何一个或组合。此外，附加的特征可以是电活动的并且响应于半导体器件操作。另外，用于确定连接凸块密度的方法，哪些方法可以是自动化的。

19. 发明授权

US07366044B2 Systems and methods for data transfers between memory cells 有权
标题翻译：存储单元之间数据传输的系统和方法
公开(公告)号：US07366044B2
公开(公告)日：2008-04-29
申请号：US11425438
申请日：2006-06-21
申请人： Satoru Takase
发明人： Satoru Takase
IPC分类号： G11C7/00 , G11C11/34 , G11C5/06 , G11C7/10
CPC分类号： G11C7/1048 , G11C5/063 , G11C7/065 , G11C11/4091 , G11C11/4093
摘要： Systems and methods for reducing the latency of data transfers between memory cells by enabling data to be transferred directly between sense amplifiers in the memory system. In one embodiment, a memory system uses a conventional DRAM memory structure having a pair of first-level sense amplifiers, a second-level sense amplifier and control logic for the sense amplifiers. Each of the sense amplifiers is configured to be selectively coupled to a data line. In a direct data transfer mode, the control logic generates control signals that cause the sense amplifiers to transfer data from a first one of the first-level sense amplifiers (a source sense amplifier) to the second-level sense amplifier, and from there to a second one of the first-level sense amplifiers (a destination sense amplifier.) The structure of these sense amplifiers is conventional, and the operation of the system is enabled by modified control logic.
摘要翻译：通过使数据能够在存储器系统中的读出放大器之间直接传输来减少存储器单元之间的数据传输的延迟的系统和方法。在一个实施例中，存储器系统使用具有一对第一电平读出放大器，第二电平读出放大器和用于读出放大器的控制逻辑的常规DRAM存储器结构。每个读出放大器被配置为选择性地耦合到数据线。在直接数据传输模式中，控制逻辑产生控制信号，使得读出放大器将数据从第一级读出放大器（源读出放大器）的第一级传输到第二级读出放大器，第一级读出放大器（目标读出放大器）中的第二级。这些读出放大器的结构是常规的，并且系统的操作由修改的控制逻辑实现。

20. 发明授权

US07183862B2 System and method for phase-locked loop leak compensation 失效
标题翻译：锁相环泄漏补偿系统及方法
公开(公告)号：US07183862B2
公开(公告)日：2007-02-27
申请号：US11136817
申请日：2005-05-25
申请人： Satoru Takase
发明人： Satoru Takase
IPC分类号： H03L7/089
CPC分类号： H03L7/0891 , H03L7/18
摘要： Phased-lock loop (PLL) system and method for compensating current leakage where current leakage may include gate-leak current attributable to a gate capacitor. In particular, providing a compensation current to an input node of a voltage-controlled oscillator (VCO) to substantially compensate current leakage and therefore reduce PLL jitter. The PLL circuit includes a compensation charge pump which receives input from a counter and in turn provides a counter-value-proportional compensation current. The counter value increments and decrements according to up and down inputs from a phase frequency detector. The counter value is fixed when the PLL circuit is locked. The PLL circuit is driven to lock by the compensation charge pump, with or without the aid of another charge pump. While the PLL is locked, the compensation charge pump may provide a fixed counter-value-proportional compensation current.
摘要翻译：用于补偿电流泄漏的相位锁定环路（PLL）系统和方法，其中电流泄漏可能包括归属于栅极电容器的栅极漏电流。特别地，向压控振荡器（VCO）的输入节点提供补偿电流，以基本上补偿电流泄漏并因此降低PLL抖动。 PLL电路包括补偿电荷泵，其接收来自计数器的输入，并且进而提供反值比例补偿电流。计数器值根据相位频率检测器的上下输入递增和递减。 PLL电路锁定时，计数器值固定。驱动PLL电路由补偿电荷泵锁定，无论是否使用另一个电荷泵。当PLL被锁定时，补偿电荷泵可以提供固定的反值比例补偿电流。

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