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    • 11. 发明授权
    • Method for improving pin compatibility in microcomputer emulation equipment
    • 提高微机仿真设备引脚兼容性的方法
    • US06799157B1
    • 2004-09-28
    • US09532514
    • 2000-03-21
    • Makoto KudoHirofumi TerasawaYoshiyuki Miyayama
    • Makoto KudoHirofumi TerasawaYoshiyuki Miyayama
    • G06E760
    • G06F17/5022
    • An objective is to provide a microcomputer, electronic equipment and emulation method which can realize the optimum circumstance of evaluation while saving the number of terminals. An external bus is shared between external and emulation memories. In the emulation mode, the access of CPU to an internal ROM is switched to the access of CPU to the emulation memory through an external bus. The emulation mode is turned ON or OFF through a mode selection terminal or mode selection register. The emulation memory is controlled by a control signal CNT2 different from a control signal CNT1 which controls the external memory. A memory read signal in CNT2 become active at a timing earlier than that of a memory read signal in CNT1. Thus, the instruction is fetched and decoded within one clock cycle. A mode selection terminal is further provided for selecting a mode of performing the boot from the emulation memory, internal ROM or external memory and a made of selecting OPT mode.
    • 目的是提供一种微电脑,电子设备和仿真方法,可以在节省终端数量的同时实现最佳的评估环境。 外部总线在外部和仿真存储器之间共享。 在仿真模式下,CPU对内部ROM的访问通过外部总线切换到CPU对仿真存储器的访问。 仿真模式通过模式选择端子或模式选择寄存器打开或关闭。 仿真存储器由与控制外部存储器的控制信号CNT1不同的控制信号CNT2控制。 CNT2中的存储器读取信号比在CNT1中的存储器读取信号的时间早一个时间被激活。 因此,指令在一个时钟周期内获取和解码。 还提供一种模式选择终端,用于从仿真存储器,内部ROM或外部存储器中选择执行引导的模式,并且选择OPT模式。
    • 13. 发明申请
    • MICROCOMPUTER
    • US20080244138A1
    • 2008-10-02
    • US12053194
    • 2008-03-21
    • Hirofumi Terasawa
    • Hirofumi Terasawa
    • G06F13/24
    • G06F13/24
    • A microcomputer includes a plurality of processing circuits for executing a plurality of interrupt processes each corresponding to one of a first plurality of causes) a cause register circuit for representing whether each of the first plurality of causes has been solved or unsolved, a processing circuit selection register for defining a plurality of correspondences each between one of the first plurality of causes and one of the plurality of processing circuits responsible to execute one the interrupt processes corresponding to the one of the first plurality of causes, and for outputting, in response to occurrence of one of the causes, to the plurality of processing circuits an interrupt signal representing that one of the interrupt processes should be executed, a vector signal indicating an area in which a content of the one of the interrupt processes corresponding to the one of the causes, and a first selection signal representing which one of the processing circuits should execute the one of the interrupt processes corresponding to the one of the causes, and a processing circuit selection circuit for outputting, in response to the first selection signal, to the processing circuit indicated by the first selection signal, a second selection signal representing that the processing circuit is selected.
    • 微计算机包括多个处理电路,用于执行各自对应于第一多个原因中的一个的多个中断处理)用于表示第一多个原因中的每一个是否已被解决或未解决的原因寄存器电路,处理电路选择 注册用于在多个原因中的一个原因和多个处理电路中的一个处理电路之间定义多个对应关系,负责执行与第一多个原因之一相对应的中断处理,并且响应于发生而输出 其中一个原因是向多个处理电路发送一个表示应该执行中断处理中的一个中断信号的向量信号,指示其中一个中断处理的内容对应于其中一个原因的区域 以及表示哪个处理电路应该执行t的第一选择信号 它是与原因之一相对应的一个中断处理,以及一个处理电路选择电路,用于响应于第一选择信号,向由第一选择信号指示的处理电路输出表示处理的第二选择信号 选择电路。