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11. 发明授权

US07622776B2 Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US07622776B2
公开(公告)日：2009-11-24
申请号：US11839219
申请日：2007-08-15
申请人： Hisao Kawasaki
发明人： Hisao Kawasaki
IPC分类号： H01L23/62
CPC分类号： H01L29/4175 , H01L29/4238 , H01L29/778 , H01L29/812 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device includes: a substrate including a compound semiconductor, a semiconductor layer formed on a surface of the substrate, a plurality of gate electrodes formed on the semiconductor layer, a plurality of source electrodes formed on the semiconductor layer, a plurality of drain electrodes formed on the semiconductor layer, a via hole configured to extend from a substrate side of the semiconductor layer to a rear surface of the source electrode, a ground electrode which is formed on an inner wall of the via hole and on the rear surface of the substrate and connects the plurality of source electrodes, and a first air bridge interconnection which is formed on a surface side of the source electrode and connects the plurality of source electrodes.
摘要翻译：半导体器件包括：包括化合物半导体的衬底，形成在衬底的表面上的半导体层，形成在半导体层上的多个栅电极，形成在半导体层上的多个源电极，多个漏电极形成在所述半导体层上的通孔，所述通孔被配置为从所述半导体层的衬底侧延伸到所述源电极的后表面;接地电极，其形成在所述通孔的内壁上，基板并连接多个源极，以及形成在源电极的表面侧并连接多个源电极的第一空气桥互连。

12. 发明授权

US5623166A Al-Ni-Cr conductive layer for semiconductor devices 失效
标题翻译：用于半导体器件的Al-Ni-Cr导电层
公开(公告)号：US5623166A
公开(公告)日：1997-04-22
申请号：US349219
申请日：1994-12-05
申请人： Johnson O. Olowolafe , Hisao Kawasaki , Chii-Chang Lee
发明人： Johnson O. Olowolafe , Hisao Kawasaki , Chii-Chang Lee
IPC分类号： H01L21/28 , H01L21/3205 , H01L21/768 , H01L23/52 , H01L23/522 , H01L23/532
CPC分类号： H01L21/76838 , H01L23/53223 , H01L2924/0002 , Y10S257/915 , Y10S438/927
摘要： An aluminum-nickel-chromium (Al-Ni-Cr) layer used as an interconnect within a semiconductor device is disclosed. The Al-Ni-Cr layer has about 0.1-0.5 weight percent nickel and about 0.02-0.1 weight percent chromium. Usually, the nickel or chromium concentrations are no greater than 0.5 weight percent. The layer is resistant to electromigration and corrosion. The low nickel and chromium concentrations allow the layer to be deposited and patterned similar to most aluminum-based layers.
摘要翻译：公开了用作半导体器件内的互连的铝 - 镍 - 铬（Al-Ni-Cr）层。 Al-Ni-Cr层具有约0.1-0.5重量％的镍和约0.02-0.1重量％的铬。通常，镍或铬的浓度不大于0.5重量％。该层耐电迁移和腐蚀。低镍和铬的浓度使得该层与大多数铝基层相似地沉积和图案化。

13. 发明授权

US5358901A Process for forming an intermetallic layer 失效
标题翻译：用于形成金属间层的方法
公开(公告)号：US5358901A
公开(公告)日：1994-10-25
申请号：US24042
申请日：1993-03-01
申请人： Robert W. Fiordalice , Stanley M. Filipiak , Johnson O. Olowolafe , Hisao Kawasaki
发明人： Robert W. Fiordalice , Stanley M. Filipiak , Johnson O. Olowolafe , Hisao Kawasaki
IPC分类号： H01L21/285 , H01L21/28 , H01L21/3205 , H01L21/321 , H01L21/768 , H01L23/52 , H01L23/522 , H01L21/44
CPC分类号： H01L21/76852 , H01L21/32051 , H01L21/321 , H01L21/76843 , H01L21/76846 , H01L21/76867 , H01L21/76886 , H01L23/53223 , H01L2924/0002 , Y10S257/915
摘要： The present invention includes a process for forming an intermetallic layer and a device formed by the process. The process includes a reaction step where a metal-containing layer reacts with a metal-containing gas, wherein the metals of the layer and gas are different. In one embodiment of the present invention, titanium aluminide may be formed on the sides of an interconnect. The process may be performed in a variety of equipment, such as a furnace, a rapid thermal processor, a plasma etcher, and a sputter deposition machine. The reaction to form the intermetallic layer is typically performed while the substrate is at a temperature no more than 700 degrees Celsius.
摘要翻译：本发明包括形成金属间化合物的方法和通过该方法形成的装置。该方法包括其中含金属层与含金属气体反应的反应步骤，其中该层和气体的金属是不同的。在本发明的一个实施方案中，可以在互连的侧面上形成铝化铝。该方法可以在各种设备中进行，例如炉，快速热处理器，等离子体蚀刻器和溅射沉积机。形成金属间化合物的反应通常在基板处于不超过700摄氏度的温度下进行。

14. 发明授权

US08587094B2 Semiconductor device using a compound semiconductor subtrate 失效
标题翻译：使用化合物半导体微量元件的半导体器件
公开(公告)号：US08587094B2
公开(公告)日：2013-11-19
申请号：US13115251
申请日：2011-05-25
申请人： Hisao Kawasaki
发明人： Hisao Kawasaki
IPC分类号： H01L29/66
CPC分类号： H01L27/0605 , H01L21/8252 , H01L27/0629 , H01L28/60
摘要： A semiconductor device having an active element and an MIM capacitor and a structure capable of reducing the number of the manufacturing steps thereof and a manufacturing method therefor are provided. The semiconductor device has a structure that the active element having an ohmic electrode and the MIM capacitor having a dielectric layer arranged between a lower electrode and an upper electrode are formed on a semiconductor substrate, wherein the lower electrode and ohmic electrode have the same structure. In an MMIC 100 in which an FET as an active element and the MIM capacitor are formed on a GaAs substrate 10, for example, a source electrode 16a and a drain electrode 16b, which are ohmic electrodes of the FET, are manufactured simultaneously with a lower electrode 16c of the MIM capacitor. Here the electrodes are formed with the same metal.
摘要翻译：提供一种具有有源元件和MIM电容器以及能够减少其制造步骤数量的结构的半导体器件及其制造方法。半导体器件具有在半导体衬底上形成具有欧姆电极的有源元件和布置在下电极和上电极之间的介电层的MIM电容器，其中下电极和欧姆电极具有相同的结构。在其中作为有源元件的FET和MIM电容器形成在GaAs衬底10上的例如作为FET的欧姆电极的源电极16a和漏电极16b的MMIC100中，与 MIM电容器的下电极16c。这里，电极由相同的金属形成。

15. 发明授权

US08307319B2 Integrated circuit reliability 有权
标题翻译：集成电路可靠性的改进或与之有关
公开(公告)号：US08307319B2
公开(公告)日：2012-11-06
申请号：US12599152
申请日：2007-05-15
申请人： Hisao Kawasaki , David Ney
发明人： Hisao Kawasaki , David Ney
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G06F2217/12 , H01L27/0203 , Y02P90/265
摘要： A method of manufacturing an integrated circuit having minimized electromigration effect, wherein the integrated circuit comprises one or more interconnect, said the or each interconnect comprising a dielectric layer having an intrinsic parameter at a first defined value, characterized in that said method comprises: identifying one or more characteristics of the or each interconnect; determining a minimal process distance from the or each interconnect for the application of one or more first metal elements; calculating a required correction parameter which can correct the intrinsic parameter at said first defined value; calculating a required number of the first metal elements which have the intrinsic parameter at a second defined value, such that the second defined value provides the required correction parameter for the first defined value; applying a plurality of said first metal elements around the interconnect at said minimum process distance to overcome the problem of electromigration caused by the intrinsic parameter at the first defined value.
摘要翻译：一种制造具有最小化电迁移效应的集成电路的方法，其中所述集成电路包括一个或多个互连，所述所述或每个互连包括具有第一限定值的固有参数的介电层，其特征在于，所述方法包括：识别一个或更多的特征; 确定用于施加一个或多个第一金属元件的所述互连或每个互连的最小工艺距离; 计算可以校正所述第一定义值的内在参数的所需校正参数; 计算具有第二定义值的固有参数的第一金属元件的所需数量，使得第二定义值为第一定义值提供所需的校正参数; 以所述最小处理距离在所述互连件周围施加多个所述第一金属元件，以克服由所述固有参数在所述第一限定值引起的电迁移的问题。

16. 发明授权

US08030691B2 Semiconductor device and manufacturing method therefor 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US08030691B2
公开(公告)日：2011-10-04
申请号：US12045304
申请日：2008-03-10
申请人： Hisao Kawasaki
发明人： Hisao Kawasaki
IPC分类号： H01L29/80 , H01L31/112 , H01L21/338
CPC分类号： H01L27/0605 , H01L21/8252 , H01L27/0629 , H01L28/60
摘要： An MMIC 100 is a semiconductor device which includes an FET formed on a GaAs substrate 10 and an MIM capacitor having a dielectric layer 20b arranged between a lower electrode 18b and an upper electrode 22b. A method for manufacturing the MMIC 100 is provided, in which a source electrode 16a and a drain electrode 16b of the FET are formed and then a gate electrode 18a of the FET and a lower electrode 18b of the MIM capacitor are formed simultaneously by the lift-off method.
摘要翻译： MMIC 100是包括形成在GaAs衬底10上的FET和具有布置在下电极18b和上电极22b之间的电介质层20b的MIM电容器的半导体器件。提供了制造MMIC100的方法，其中形成FET的源电极16a和漏电极16b，然后由电梯同时形成FET的栅电极18a和MIM电容器的下电极18b -off方法。

17. 发明申请

US20100314769A1 FOR REDUCING ELECTROMIGRATION EFFECT IN AN INTEGRATED CIRCUIT 有权
标题翻译：用于减少集成电路中的电气效应
公开(公告)号：US20100314769A1
公开(公告)日：2010-12-16
申请号：US12675242
申请日：2007-09-20
申请人： Greg Braeckelmann , Hisao Kawasaki , Marius Orlowski , Emmanuel Petitprez
发明人： Greg Braeckelmann , Hisao Kawasaki , Marius Orlowski , Emmanuel Petitprez
IPC分类号： H01L23/48 , H01L21/768
CPC分类号： H01L21/76838 , H01L21/7682 , H01L21/76831 , H01L23/53223 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit comprising one or more dielectric layers the or each dielectric layer being provided with one or more interconnects wherein the interconnect comprises metallic atoms moving from a first region of the interconnect to a second region of the interconnect when a current flows, characterised in that the interconnect comprises a donor zone in the first region of the interconnect for providing metallic atoms in order to compensate for movement of atoms from the first region and a receptor zone at the second region of the interconnect for receiving metallic atoms in order to compensate for movement of atoms to the second region.
摘要翻译：一种包括一个或多个电介质层的集成电路，其中或每个电介质层设置有一个或多个互连，其中互连包括当电流流动时从互连的第一区域移动到互连的第二区域的金属原子，其特征在于互连件包括在互连的第一区域中的供体区域，用于提供金属原子，以便补偿来自第一区域的原子的移动以及用于接收金属原子的互连的第二区域处的受体区域，以便补偿运动的原子到第二个区域。

18. 发明授权

US06218733B1 Semiconductor device having a titanium-aluminum compound 失效
标题翻译：具有钛 - 铝化合物的半导体器件
公开(公告)号：US06218733B1
公开(公告)日：2001-04-17
申请号：US08254854
申请日：1994-06-06
申请人： Robert W. Fiordalice , Stanley M. Filipiak , Johnson Olufemi Olowolafe , Hisao Kawasaki
发明人： Robert W. Fiordalice , Stanley M. Filipiak , Johnson Olufemi Olowolafe , Hisao Kawasaki
IPC分类号： H01L2348
CPC分类号： H01L21/76852 , H01L21/32051 , H01L21/321 , H01L21/76843 , H01L21/76846 , H01L21/76867 , H01L21/76886 , H01L23/53223 , H01L2924/0002 , Y10S257/915 , H01L2924/00
摘要： The present invention includes a process for forming an intermetallic layer and a device formed by the process. The process includes a reaction step where a metal-containing layer reacts with a metal-containing gas, wherein the metals of the layer and gas are different. In one embodiment of the present invention, titanium aluminide may be formed on the sides of an interconnect. The process may be performed in a variety of equipment, such as a furnace, a rapid thermal processor, a plasma etcher, and a sputter deposition machine. The reaction to form the intermetallic layer is typically performed while the substrate is at a temperature no more than 700 degrees Celsius.
摘要翻译：本发明包括形成金属间化合物的方法和通过该方法形成的装置。该方法包括其中含金属层与含金属气体反应的反应步骤，其中该层和气体的金属是不同的。在本发明的一个实施方案中，可以在互连的侧面上形成铝化铝。该方法可以在各种设备中进行，例如炉，快速热处理器，等离子体蚀刻器和溅射沉积机。形成金属间化合物的反应通常在基板处于不超过700摄氏度的温度下进行。

19. 发明授权

US5317185A Semiconductor device having structures to reduce stress notching effects in conductive lines and method for making the same 失效
标题翻译：具有降低导电线中的应力开槽效应的结构的半导体装置及其制造方法
公开(公告)号：US5317185A
公开(公告)日：1994-05-31
申请号：US836169
申请日：1992-02-18
申请人： Mark G. Fernandes , Hisao Kawasaki
发明人： Mark G. Fernandes , Hisao Kawasaki
IPC分类号： H01L23/528 , H01L21/88
CPC分类号： H01L23/5283 , H01L2924/0002
摘要： A semiconductor device has structures to reduced stress notching effects in conductive lines. In one form, the semiconductor device includes a semiconductor die which has a plurality of active conductive lines thereon. The plurality of conductive lines collectively has a first and a second outside edge. In close proximity to each of the first and the second outside edges is a stress reducing line. Each of the stress reducing lines is a non-active structure (in other words does not transmit signals) and functions to reduce stress concentrations on the plurality of active conductive lines which are imposed by overlying insulating and passivation layers. As a result of weakened stress concentrations, the amount of stress notching in the active conductive lines is reduced.
摘要翻译：半导体器件具有降低导电线中的应力开槽效应的结构。在一种形式中，半导体器件包括其上具有多条有源导线的半导体管芯。多个导电线共同具有第一和第二外边缘。紧邻第一和第二外边缘中的每一个是应力减小线。每个应力减小线是非有源结构（换句话说，不传输信号），并且用于减少由覆盖绝缘层和钝化层施加的多个有源导线上的应力集中。作为应力集中的弱化的结果，活性导电线中的应力开槽量减少。

20. 发明授权

US08735943B2 Semiconductor device with recess having inclined sidewall and method for manufacturing the same 有权
标题翻译：具有倾斜侧壁的凹槽的半导体器件及其制造方法
公开(公告)号：US08735943B2
公开(公告)日：2014-05-27
申请号：US13600155
申请日：2012-08-30
申请人： Ryota Senda , Hisao Kawasaki
发明人： Ryota Senda , Hisao Kawasaki
IPC分类号： H01L29/66
CPC分类号： H01L29/42316 , H01L29/20 , H01L29/7787
摘要： A semiconductor device includes a semiconductor layer, an insulating film, a gate electrode, a drain electrode, and a source electrode. The semiconductor layer includes an active layer and is formed on a semi-insulating semiconductor substrate, and a tapered recess area having an inclined sidewall is formed on a surface of the semiconductor layer. The insulating film is formed on the semiconductor layer and has a through hole for exposing the recess area. The through hole has a tapered sidewall which is inclined at an angle smaller than the sidewall of the recess area. The gate electrode is formed so as to fill the recess area and the through hole. The drain electrode and the source electrode are formed at positions on opposite sides of the recess area on the semiconductor layer.
摘要翻译：半导体器件包括半导体层，绝缘膜，栅电极，漏电极和源电极。半导体层包括有源层，形成在半绝缘性半导体基板上，在半导体层的表面上形成具有倾斜侧壁的锥形凹部。绝缘膜形成在半导体层上，并且具有用于使凹部露出的通孔。通孔具有锥形侧壁，该锥形侧壁以比凹部区域的侧壁小的角度倾斜。栅电极形成为填充凹部区域和通孔。漏电极和源电极形成在半导体层上的凹部区域的相对侧的位置。

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