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11. 发明授权

US08634658B2 Apparatus, method, and program for processing image 有权
标题翻译：用于处理图像的装置，方法和程序
公开(公告)号：US08634658B2
公开(公告)日：2014-01-21
申请号：US12829870
申请日：2010-07-02
申请人： Naoyuki Onoe , Junichi Yamashita , Daisuke Mochizuki , Naoki Kobayashi , Akihiko Kaino
发明人： Naoyuki Onoe , Junichi Yamashita , Daisuke Mochizuki , Naoki Kobayashi , Akihiko Kaino
IPC分类号： G06K9/64
CPC分类号： G06K9/00268 , G06K9/00308 , G06T11/00 , G06T11/60
摘要： An image processing apparatus includes a face detector for detecting a face region from an image including a face of a user, a part detector for detecting a positional layout of a part of the face included in the face region detected by the face detector, a determiner for determining an attribute of the face on the basis of the positional layout of the part detected by the part detector and calculating a score indicating attribute determination results, a model selector for selecting, on the basis of the score calculated by the determiner, a model that is to be displayed in place of the face of the user in the image, and an image generator for generating an image of a face of the model selected by the model selector and synthesizing the image of the face of the model with the face of the user within the face region.
摘要翻译：一种图像处理装置包括：面部检测器，用于从包括用户面部的图像中检测面部区域;检测器，用于检测由面部检测器检测到的面部区域中包括的面部的一部分的位置布局;确定器用于基于由部件检测器检测到的部分的位置布局来确定面部的属性，并计算指示属性确定结果的分数;模型选择器，用于基于由确定器计算的分数来选择模型代替图像中的用户的脸部进行显示的图像生成器，以及用于生成由模型选择器选择的模型的脸部的图像的图像生成器，并且将模型的脸部的图像与脸部脸部区域内的用户。

12. 发明授权

US08605500B2 Multilevel nonvolatile semiconductor memory system 有权
标题翻译：多级非易失性半导体存储器系统
公开(公告)号：US08605500B2
公开(公告)日：2013-12-10
申请号：US13050431
申请日：2011-03-17
申请人： Naoki Kobayashi , Mitsuaki Honma , Noboru Shibata
发明人： Naoki Kobayashi , Mitsuaki Honma , Noboru Shibata
IPC分类号： G11C11/34
CPC分类号： G11C11/5628
摘要： According to one embodiment, a system includes a memory, a controller which controls an operation of the memory in a data program, and data bus which connects the memory to the controller. The memory comprises a memory cell array with memory cells which have a bit assignment to 2x (x is an integer number of 3 or more) threshold distributions, each memory cell storing x bits, and a control circuit which controls the data program of x bits to the memory cells. The controller comprises a first step generating y bit (y is an integer number and y
摘要翻译：根据一个实施例，系统包括存储器，控制数据程序中的存储器的操作的控制器以及将存储器连接到控制器的数据总线。存储器包括具有存储器单元的存储器单元阵列，其具有位分配为2x（x为3或更多的整数）阈值分布，每个存储单元存储x位，以及控制电路，其控制x位数据程序到记忆体细胞。控制器包括基于x位产生y位（y为整数和y

13. 发明申请

US20130068515A1 INTERCONNECT BOARD AND ELECTRONIC APPARATUS 有权
标题翻译：互连板和电子设备
公开(公告)号：US20130068515A1
公开(公告)日：2013-03-21
申请号：US13701010
申请日：2011-06-02
申请人： Hiroshi Toyao , Manabu Kusumoto , Naoki Kobayashi , Noriaki Ando
发明人： Hiroshi Toyao , Manabu Kusumoto , Naoki Kobayashi , Noriaki Ando
IPC分类号： H05K1/18 , H05K1/11
CPC分类号： H05K1/0236 , H05K1/0224
摘要： An electronic apparatus (100) has an electronic device (151), a power supply plane (121) and a power supply plane (122) disposed with a gap (123) therebetween, a connection member (152) that electrically connects the power supply plane (122) and the electronic device (151), a ground plane (141) facing the power supply plane (121) or the power supply plane (122), a connection member (153) that electrically connects the ground plane (141) and the electronic device (151), a plurality of conductor elements (131) that is repeatedly arrayed, and open stubs (111) formed at a location overlapping the gap (123) included in an area surrounded by the conductor elements (131). In addition, at least some of the open stubs (111) face the power supply plane (122) which is not in contact with the open stubs (111).
摘要翻译：一种电子设备（100），具有电子设备（151），电源平面（121）和设置在其间的间隙（123）的电源平面（122），连接构件（152）将电源平面（122）和电子设备（151），面对电源平面（121）或电源平面（122）的接地平面（141），将接地平面（141）电连接的连接构件电子设备（151），重复排列的多个导体元件（131）和形成在与由导体元件（131）包围的区域中的间隙（123）重叠的位置处的开口短截线（111）。此外，至少一些开放桩（111）面向不与开放桩（111）接触的供电平面（122）。

14. 发明申请

US20130045644A1 CRIMPING TERMINAL, AND CRIMPING STRUCTURE OF CRIMPING TERMINAL AGAINST ELECTRIC WIRE 有权
标题翻译：撞击终端和打击电线的电击结构
公开(公告)号：US20130045644A1
公开(公告)日：2013-02-21
申请号：US13583242
申请日：2011-03-23
申请人： Hiroshi Aoki , Osamu Oshita , Naoki Kobayashi
发明人： Hiroshi Aoki , Osamu Oshita , Naoki Kobayashi
IPC分类号： H01R4/10
CPC分类号： H01R4/183
摘要： The upper surface panel 15 and the lower surface 14 of the electric wire connection portion of the crimping terminal 10 are formed in such a cross-sectional shape that when placed and joined together an internal space is formed therein to house the end portion of an electric wire W and also such that when the interior is compressed and sealed by receiving crimping force from an vertical direction the end portion of the electrical connection is crimped thereby. Further, an electric wire insertion aperture 17 is provided in the junction 16 between the lower surface panel 14 and the upper surface panel 15 to allow the end portion of the electric wire W to be inserted therebetween.
摘要翻译：压接端子10的电线连接部分的上表面板15和下表面14形成为横截面形状，当放置并连接在一起时，形成内部空间以容纳电气端部并且还使得当通过从垂直方向接收压接力来压缩和密封内部时，电连接的端部被压接。此外，在下表面板14和上表面板15之间的接合部16中设置有电线插入孔17，以允许电线W的端部插入其间。

15. 发明申请

US20130037316A1 STRUCTURE AND CIRCUIT BOARD 有权
标题翻译：结构与电路板
公开(公告)号：US20130037316A1
公开(公告)日：2013-02-14
申请号：US13583277
申请日：2011-02-18
申请人： Hiroshi Toyao , Naoki Kobayashi , Noriaki Ando
发明人： Hiroshi Toyao , Naoki Kobayashi , Noriaki Ando
IPC分类号： H05K1/11
CPC分类号： H05K1/0236 , H01P3/00 , H05K1/0298
摘要： A structure (10) includes a conductor (151), conductors (111, 131) that are located on the same side with respect to the conductor (151), that are opposed to at least a part of the conductor (151), and that overlap each other when seen in a plan view, a connection member (101) that penetrates the conductors (111, 131, 151), that is connected to the conductor (151), and that is insulated from the conductors (111, 131), openings (112, 132) that are formed in the conductors (111, 131), respectively, and which the connection member (101) passes through, and conductor elements (121, 141) that are formed to be opposed to the openings (112, 132), that are connected to the connection member (101) passing through the openings (112, 132), and that are larger than the openings (112, 132). The number of layers in which the conductor elements (121, 141) are located is two or more and less than or equal to the number of layers in which the conductors (111, 131) are located.
摘要翻译：结构（10）包括导体（151），相对于导体（151）位于同一侧的与导体（151）的至少一部分相对的导体（111,131），以及在平面图中看到彼此重叠的连接构件（101），其连接到与导体（151）连接并且与导体（111,131）绝缘的导体（111,131,151）），分别形成在导体（111,131）中并且连接构件（101）通过的开口（112,132）以及形成为与开口相对的导体元件（121,141）（112,132），其连接到穿过所述开口（112,132）的所述连接构件（101），并且大于所述开口（112,132）。导体元件（121,141）所在的层数为两个以上且小于等于导体（111,131）所在的层数。

16. 发明授权

US08357068B2 Automatic transmission 有权
标题翻译：自动变速器
公开(公告)号：US08357068B2
公开(公告)日：2013-01-22
申请号：US12731892
申请日：2010-03-25
申请人： Kazuaki Aota , Yukiyoshi Inuta , Akihiro Yamamoto , Naoki Kobayashi , Takayuki Okuda , Peter Tenberge , Joerg Mueller , Rico Resch
发明人： Kazuaki Aota , Yukiyoshi Inuta , Akihiro Yamamoto , Naoki Kobayashi , Takayuki Okuda , Peter Tenberge , Joerg Mueller , Rico Resch
IPC分类号： F16H3/62
CPC分类号： F16H3/66 , F16H2200/006 , F16H2200/0065 , F16H2200/0086 , F16H2200/201 , F16H2200/2048
摘要： An automatic transmission includes first to third single-pinion planetary gearsets. The second ring gear and third sun gear are coupled to the first carrier and first ring gear respectively to constitute first and second rotor units. Input and output shafts are coupled to the second sun gear and third ring gear respectively. A first clutch selectively holds the first sun gear to the third carrier. A first brake selectively holds the first sun gear stationary. A second clutch selectively holds the second sun gear to the third carrier. A third clutch selectively holds the second carrier to the second rotor unit. A fourth clutch selectively holds the second carrier to the third carrier. A second brake selectively holds the first rotor unit stationary. At least eight gear ratios and one reverse gear ratio are obtained by simultaneous application of three of the clutches and brakes.
摘要翻译：自动变速器包括第一至第三单小齿轮行星齿轮组。第二齿圈和第三太阳齿轮分别联接到第一行星架和第一齿圈，以构成第一和第二转子单元。输入和输出轴分别联接到第二太阳齿轮和第三齿圈。第一离合器选择性地将第一太阳轮保持在第三行星架上。第一制动器选择性地保持第一太阳齿轮静止。第二离合器选择性地将第二太阳轮保持在第三行星架上。第三离合器选择性地将第二载体保持在第二转子单元上。第四离合器选择性地将第二载体保持在第三载体上。第二制动器选择性地保持第一转子单元静止。通过同时施加三个离合器和制动器来获得至少八个齿轮比和一个倒档齿轮比。

17. 发明申请

US20120329318A1 CONNECTION STRUCTURE OF TERMINAL TO ELECTRIC WIRE 有权
标题翻译：端子到电线的连接结构
公开(公告)号：US20120329318A1
公开(公告)日：2012-12-27
申请号：US13583143
申请日：2011-03-23
申请人： Hiroshi Aoki , Naoki Kobayashi
发明人： Hiroshi Aoki , Naoki Kobayashi
IPC分类号： H01R13/52
CPC分类号： H01R4/02 , H01R4/023 , H01R4/029 , H01R4/723 , H01R12/57 , H01R43/0207
摘要： In a connection structure of a terminal (10), a distal end of the electric wire (W) is inserted into the electric wire connection part (12) of the terminal (10) and a conductor (Wa) and a portion of an insulating sheath (Wb) of the electric wire (W) are placed on an upper surface of the base plate parts (21, 23) and the conductor (Wa) is bonded to the base plate parts (21, 23) by welding in that state, a portion of at least the conductor (Wa) of the distal end of the electric wire (W) inserted into the electric wire connection part (12) is covered with a metallic cover member (30) and the conductor (Wa) is bonded to the base plate parts (21, 23) together with the cover member (30) by welding.
摘要翻译：在端子（10）的连接结构中，电线（W）的前端插入端子（10）的电线连接部（12）中，导体（Wa）和绝缘体电线（W）的护套（Wb）被放置在基板部件（21,23）的上表面上，并且在该状态下通过焊接将导体（Wa）接合到基板部件（21,23）至少插入电线连接部分（12）中的电线（W）的远端的导体（Wa）的一部分被金属盖构件（30）覆盖，导体（Wa）被接合通过焊接与盖构件（30）一起连接到基板部件（21,23）。

18. 发明申请

US20120319908A1 ELECTRONIC APPARATUS 审中-公开
标题翻译：电子设备
公开(公告)号：US20120319908A1
公开(公告)日：2012-12-20
申请号：US13576532
申请日：2011-02-18
申请人： Goichi Tsutsumi , Naoki Kobayashi , Noriaki Ando , Hiroshi Toyao , Masaharu Imazato
发明人： Goichi Tsutsumi , Naoki Kobayashi , Noriaki Ando , Hiroshi Toyao , Masaharu Imazato
IPC分类号： H01Q1/24
CPC分类号： H05K1/0236 , H01Q1/243 , H01Q1/52 , H01Q15/008 , H05K1/0221 , H05K1/024 , H05K1/028 , H05K1/147
摘要： An electronic apparatus is provided which includes a first housing that is provided with a first electronic component (11), a second housing that is provided with a second electronic component (21), an antenna which is provided at an end portion of the first housing, and a connection body (40) which passes through the end portion of the first housing and connects the first electronic component (11) and the second electronic component (21) to each other, wherein the connection body (40) has an electric conductor layer, a dielectric layer, and a first conductor having a repeated structure at least in some areas. According to the electronic apparatus, a disadvantage can be suppressed in which in a case where a flexible substrate is disposed in the vicinity of the antenna, antenna characteristics deteriorate due to the flexible substrate.
摘要翻译：提供一种电子设备，其包括设置有第一电子部件（11）的第一壳体和设置有第二电子部件（21）的第二壳体，设置在第一壳体的端部的天线以及连接体（40），其穿过第一壳体的端部并将第一电子部件（11）和第二电子部件（21）彼此连接，其中，连接体（40）具有导电体至少在一些区域中具有重复结构的第一导体。根据电子设备，可以抑制在柔性基板设置在天线附近的情况下的天线特性由于柔性基板而劣化的缺点。

19. 发明授权

US08271925B2 Printed board design system and method including decoupling capacitor arrangement examination unit 有权
标题翻译：印刷电路板设计系统及方法，包括去耦电容布置检查单元
公开(公告)号：US08271925B2
公开(公告)日：2012-09-18
申请号：US12628350
申请日：2009-12-01
申请人： Naoki Kobayashi
发明人： Naoki Kobayashi
IPC分类号： G06F17/50
CPC分类号： H05K3/0005 , G06F17/5077 , H05K1/0231 , H05K2201/093 , H05K2201/09309 , H05K2201/10689
摘要： A decoupling capacitor pin position information obtain unit calculates based on board design data of a printed board, position information indicating positions of decoupling capacitors on the printed board. A power supply plane position/shape information obtain unit calculates based on the board design data, position/shape information indicating a position and shape of a power supply plane of the printed board. A restriction condition input unit collects restriction conditions from an input device. A decoupling capacitor examination unit judges based on the position information, the position/shape information and the restriction conditions, whether or not arrangement of the decoupling capacitors is adequate. Therefore, a designer, while designing arrangement/wiring of the printed board, can check in real time whether or not the arrangement of the decoupling capacitors is adequate, and thus can design at higher speed a printed board in which arrangement of decoupling capacitors is adequate.
摘要翻译：去耦电容针脚位置信息获取单元根据印刷电路板的板设计数据计算位置信息，指示印刷电路板上去耦电容器的位置。供电平面位置/形状信息获取单元基于板设计数据，指示印刷板的电源平面的位置和形状的位置/形状信息来计算。限制条件输入单元从输入装置收集限制条件。去耦电容器检查单元基于位置信息，位置/形状信息和限制条件判断去耦电容器的布置是否足够。因此，设计人员在设计印刷电路板的布置/接线时，可以实时检查去耦电容器的布置是否足够，从而可以更高速度设计去耦电容器布置足够的印刷电路板。

20. 发明授权

US08073058B2 Memory device and device and method for detecting motion vector 失效
标题翻译：用于检测运动矢量的记忆装置及装置及方法
公开(公告)号：US08073058B2
公开(公告)日：2011-12-06
申请号：US12559212
申请日：2009-09-14
申请人： Tetsujiro Kondo , Wataru Niitsuma , Naoki Kobayashi
发明人： Tetsujiro Kondo , Wataru Niitsuma , Naoki Kobayashi
IPC分类号： H04N7/12 , G06K9/36
CPC分类号： H04N5/145 , G06T7/231 , G06T2200/28 , G06T2207/10016 , G11C7/1006 , G11C11/565 , H04N19/43 , H04N19/436 , H04N19/51 , H04N19/61
摘要： This invention relates to a memory device and the like that are preferably applied to a case where motion vector is detected using a block matching. Pixel data of a first frame (a reference frame) is stored in a unit A of memory cell array portion 20a in straight binary format. Pixel data of a second frame (a search frame) is stored in a unit B of memory cell array portion 20b in two's complement format. The units A and B have a plurality of memory cells, respectively. Word lines WL related to the pixel data of the first and second frames are simultaneously activated so that charges accumulated in capacitors of each of the memory cells can be combined along one bit line BL. A/D converter 53 outputs a digital signal (absolute difference value) having a value that corresponds to a total amount of charges. When reading the pixel data, a subtraction and a conversion into the absolute difference value are simultaneously performed.
摘要翻译：本发明涉及优选地应用于使用块匹配检测运动矢量的情况的存储器件等。第一帧（参考帧）的像素数据以直二进制格式存储在存储单元阵列部分20a的单元A中。第二帧（搜索帧）的像素数据以二进制格式存储在存储单元阵列部分20b的单元B中。单元A和B分别具有多个存储单元。与第一和第二帧的像素数据相关的字线WL被同时激活，使得可以沿着一个位线BL组合每个存储单元的电容器中积累的电荷。 A / D转换器53输出具有与总电荷量对应的值的数字信号（绝对差值）。当读取像素数据时，同时执行减法和转换成绝对差值。

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