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11. 发明申请

US20120289653A1 ALUMINA PARTICLE COMPOSITE, METHOD OF MANUFACTURING THE ALUMINA PARTICLE COMPOSITE, RESIN COMPOSITION AND METHOD OF MANUFACTURING THE RESIN COMPOSITION 失效
标题翻译：氧化铝颗粒复合材料，制造氧化铝颗粒复合材料的方法，树脂组合物和制备树脂组合物的方法
公开(公告)号：US20120289653A1
公开(公告)日：2012-11-15
申请号：US13469302
申请日：2012-05-11
申请人： Takashi Oda , Yasuaki Kai , Tomohiro Itou , Takashi Seino , Hironobu Muramatsu
发明人： Takashi Oda , Yasuaki Kai , Tomohiro Itou , Takashi Seino , Hironobu Muramatsu
IPC分类号： C08K3/22 , C08L33/12 , C08L69/00
CPC分类号： C01F7/02 , B82Y30/00 , C01F7/021 , C01P2004/04 , C01P2004/10 , C01P2004/54 , C01P2004/62 , C01P2004/64 , C01P2006/22 , C08K9/04 , C09C1/407
摘要： An alumina particle composite (1) includes an alumina particle (2) and an organic acid (3) chemically bonded to a surface of the alumina particle (2). Further, the alumina particle (2) has a short axis length of 1 to 10 nm, a long axis length of 20 to 400 nm, and an aspect ratio of 5 to 80, and is represented by Formula I, Al2O3.nH2O Formula I where n is 0 or more.
摘要翻译：氧化铝颗粒复合材料（1）包括氧化铝颗粒（2）和与氧化铝颗粒（2）的表面化学键合的有机酸（3）。此外，氧化铝颗粒（2）的短轴长度为1〜10nm，长轴长度为20〜400nm，纵横比为5〜80，由式I表示，Al 2 O 3·nH 2 O式I 其中n为0以上。

12. 发明授权

US08247890B2 Wiring circuit structure and manufacturing method for semiconductor device using the structure 有权
标题翻译：使用该结构的半导体器件的接线电路结构和制造方法
公开(公告)号：US08247890B2
公开(公告)日：2012-08-21
申请号：US12952404
申请日：2010-11-23
申请人： Takashi Oda , Shigenori Morita
发明人： Takashi Oda , Shigenori Morita
IPC分类号： H01L23/495
CPC分类号： H01L24/81 , H01L21/6835 , H01L23/49816 , H01L23/49827 , H01L23/49838 , H01L24/13 , H01L24/16 , H01L2221/68345 , H01L2224/10165 , H01L2224/1134 , H01L2224/13099 , H01L2224/13144 , H01L2224/16227 , H01L2224/29015 , H01L2224/73103 , H01L2224/73203 , H01L2224/81001 , H01L2224/81136 , H01L2224/8114 , H01L2224/81193 , H01L2224/81801 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01022 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/01044 , H01L2924/01045 , H01L2924/01047 , H01L2924/01049 , H01L2924/0105 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/12044 , H01L2924/1461 , H01L2924/15788 , H01L2924/00012 , H01L2924/00 , H01L2924/00014
摘要： A conductor layer 2 is formed as a circuit pattern on a base insulating layer 1, a terminal 3 is formed thereon, and a supporting column 4 is formed in the vicinity of the terminal on the upper face of the base insulating layer 1. Here, supposing the protrusion height B of the bump from the element to be connected is B, the height of the supporting column is H, the height of the terminal is h, and the layer thickness of the terminal is t, as measured from the upper face of the base insulating layer as the reference surface, the height H of the supporting column is determined to satisfy B
摘要翻译：在基底绝缘层1上形成导体层2作为电路图案，在其上形成端子3，并且在基底绝缘层1的上表面上的端子附近形成支撑柱4.这里，假设凸起的突出高度B与要连接的元件的B高度一致，支柱的高度为H，端子的高度为h，端子的层厚为t，从上表面作为基准面的基底绝缘层的高度H被确定为满足B

13. 发明申请

US20120205820A1 ENCAPSULATING RESIN SHEET AND SEMICONDUCTOR DEVICE USING THE SAME, AND MANUFACTURING METHOD FOR THE SEMICONDUCTOR DEVICE 审中-公开
标题翻译：使用其的封装树脂片和半导体器件以及半导体器件的制造方法
公开(公告)号：US20120205820A1
公开(公告)日：2012-08-16
申请号：US13364592
申请日：2012-02-02
申请人： Takashi Oda , Kosuke Morita , Hiroyuki Senzai
发明人： Takashi Oda , Kosuke Morita , Hiroyuki Senzai
IPC分类号： H01L23/522 , B32B7/02 , B32B27/38 , H01L21/56
CPC分类号： H01L21/563 , H01L23/293 , H01L23/295 , H01L2224/29082 , H01L2224/73104 , H01L2224/83191 , Y10T428/24942 , Y10T428/2495
摘要： Provided are an encapsulating resin sheet having improved a connection reliability by improving a connection failure, and by suppressing intrusion of an inorganic filler between terminals of the semiconductor element and the interconnection circuit substrate, a semiconductor device using the same, and a fabricating method for the semiconductor device. The encapsulating resin sheet is an epoxy resin composition sheet having a two-layer structure of an inorganic filler containing layer and an inorganic filler non-containing layer, in which a melt viscosity of the inorganic filler containing layer is 1.0×102 to 2.0×104 Pa·s, a melt viscosity of the inorganic filler non-containing layer is 1.0×103 to 2.0×105 Pa·s, a viscosity difference between both layers is 1.5×104 Pa·s or more; and a thickness of the inorganic filler non-containing layer is ⅓ to ⅘ of a height of the connecting electrode portion formed in the semiconductor element.
摘要翻译：提供一种封装树脂片，其通过改善连接故障而提高连接可靠性，并且通过抑制半导体元件和互连电路基板的端子之间的无机填料的侵入，使用该封装树脂片的半导体器件及其制造方法半导体器件。封装树脂片是具有无机填料含有层和无机填料不含层的两层结构的无机填料含有层的熔融粘度为1.0×10 2〜2.0×10 4的环氧树脂组合物片 Pa·s时，无机填料无含水层的熔融粘度为1.0×10 3〜2.0×10 5 Pa·s，两层之间的粘度差为1.5×10 4 Pa·s以上; 无机填料不含有层的厚度为半导体元件中形成的连接电极部的高度的1/3〜。。

14. 再颁专利

USRE43468E1 Alumina particles of high aspect ratio, alumina particle manufacturing method, resin composition, and resin composition manufacturing method 失效
标题翻译：高纵横比的氧化铝颗粒，氧化铝颗粒的制造方法，树脂组合物和树脂组合物制造方法
公开(公告)号：USRE43468E1
公开(公告)日：2012-06-12
申请号：US12621060
申请日：2009-11-18
申请人： Takashi Oda , Yasuaki Kai , Tomohiro Ito
发明人： Takashi Oda , Yasuaki Kai , Tomohiro Ito
IPC分类号： B32B5/16 , C04B14/30
CPC分类号： C01F7/02 , B82Y30/00 , C01F7/34 , C01F7/448 , C01P2004/04 , C01P2004/13 , C01P2004/54 , Y10T428/257 , Y10T428/2982
摘要： An alumina particle (1) of the present invention has an alumina body with a short axis length (b) of 1 to 10 nm, a long axis length (a) of 20 to 400 nm and an aspect ratio (a/b) of 5 to 80. The alumina body is expressed by a Formula I, and n is not less than 0. Al2O3.nH2O Formula I
摘要翻译：本发明的氧化铝颗粒（1）具有短轴长（b）为1〜10nm，长轴长（a）为20〜400nm，纵横比（a / b）为氧化铝体由式I表示，n不小于0.Al 2 O 3·nH 2 O式I

15. 发明授权

US08130486B2 Electronic component and method of manufacturing the same 失效
标题翻译：电子部件及其制造方法
公开(公告)号：US08130486B2
公开(公告)日：2012-03-06
申请号：US12498572
申请日：2009-07-07
申请人： Kazuya Kawahara , Yuuki Murata , Takashi Oda
发明人： Kazuya Kawahara , Yuuki Murata , Takashi Oda
IPC分类号： H01G4/32 , H01G9/04 , H01G9/10
CPC分类号： H01G9/151 , H01G9/012 , H01G9/10 , Y10T29/417 , Y10T29/435
摘要： An electronic component includes a functional element, first and second collectors joined to the functional element, and an outer package integrally covering the functional element and the first and second collectors. The functional element has first and second end surfaces having circular shapes and a side surface having a cylindrical shape extending along a center axis. The element includes first and second electrode foils rolled about the center axis and exposed from the first and second surfaces, respectively. The outer package has first and second surfaces parallel to the first and second end surfaces of the functional element, and has first to fourth corners as seen from a direction of the center axis. The first corner is adjacent to the second corner. The first and second terminals are arranged at the first and second corners of the outer package, respectively. This electronic component can have a small size and a small height while reducing its equivalent series resistance.
摘要翻译：电子部件包括功能元件，连接到功能元件的第一和第二收集器，以及整体地覆盖功能元件和第一和第二收集器的外部封装。功能元件具有圆形形状的第一和第二端面以及具有沿着中心轴延伸的圆柱形状的侧表面。元件包括围绕中心轴线卷绕并从第一表面和第二表面暴露的第一和第二电极箔。外包装具有平行于功能元件的第一和第二端面的第一表面和第二表面，并且从中心轴线的方向看，具有第一至第四角。第一个角落与第二个角相邻。第一和第二端子分别布置在外包装的第一和第二拐角处。该电子部件可以具有小尺寸和小的高度，同时降低其等效的串联电阻。

16. 发明授权

US08124457B2 Manufacturing method of transferring a wiring circuit layer on a metal support substrate to a semiconductor element 有权
标题翻译：将金属支撑基板上的布线电路层转印到半导体元件上的制造方法
公开(公告)号：US08124457B2
公开(公告)日：2012-02-28
申请号：US12634350
申请日：2009-12-09
申请人： Takashi Oda , Shigenori Morita , Naoko Yoshida
发明人： Takashi Oda , Shigenori Morita , Naoko Yoshida
IPC分类号： H01L21/00
CPC分类号： H01L24/03 , H01L21/6835 , H01L2221/68372 , H01L2224/02319 , H01L2224/04042 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01019 , H01L2924/01022 , H01L2924/01024 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01044 , H01L2924/01045 , H01L2924/01047 , H01L2924/01049 , H01L2924/0105 , H01L2924/01057 , H01L2924/01068 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/12044 , H01L2924/1461 , H01L2924/15788 , H01L2924/00
摘要： A wiring circuit layer 2 having a connecting conductor part 21 that can be connected to an electrode 31 of a semiconductor element 3 is formed on a metal support substrate 1 in a way such that the wiring circuit layer can be separated from the substrate 1, and that the connecting conductor part 21 is exposed on the upper face of the wiring circuit layer. The wiring circuit layer 2 is laminated on the element 3 while in a wafer state, and the connecting conductor part 21 and the electrode 31 are connected. Subsequently, the support substrate 1 is peeled from the wiring circuit layer 2, and the wafer is diced, whereby individual semiconductor devices are obtained.
摘要翻译：在金属支撑基板1上形成具有能够与半导体元件3的电极31连接的连接导体部21的布线电路层2，使得布线电路层能够与基板1分离，并且连接导体部21露出在布线电路层的上表面。布线电路层2在晶片状态下层叠在元件3上，连接导体部21和电极31连接。随后，将支撑基板1从布线电路层2剥离，并对晶片进行切割，从而获得各个半导体器件。

17. 发明申请

US20090106975A1 Roughened Printed Circuit Board And Manufacturing Method Thereof 失效
标题翻译：粗化印刷电路板及其制造方法
公开(公告)号：US20090106975A1
公开(公告)日：2009-04-30
申请号：US12345134
申请日：2008-12-29
申请人： Tadao Ookawa , Mitsuru Honjo , Takashi Oda
发明人： Tadao Ookawa , Mitsuru Honjo , Takashi Oda
IPC分类号： H05K3/10
CPC分类号： H05K3/22 , H05K1/0393 , H05K3/002 , H05K3/0041 , H05K3/108 , H05K3/281 , H05K3/381 , H05K3/386 , H05K3/388 , H05K2203/025 , H05K2203/095 , Y10T29/49117 , Y10T29/49128 , Y10T29/49155 , Y10T29/49165 , Y10T29/53504
摘要： A multi-layer structure including a base insulating layer and a thin metal film layer (seed layer) is prepared. A plating resist layer is formed to have a prescribed pattern on the upper surface of the thin metal film layer. A metal plating layer is formed on the thin metal film layer exposed by electroplating. Then, the plating resist layer is removed, and the thin metal film layer in the region having the plating resist layer is removed. In this way, a conductive pattern including the thin metal film layer and the metal plating layer is formed. The upper surface of the base insulating layer in the region without the conductive pattern is subjected to roughening treatment. A cover insulating layer is formed on the upper surfaces of the base insulating layer and the conductive pattern. In this way, a printed circuit board is completed.
摘要翻译：制备包括基底绝缘层和薄金属膜层（籽晶层）的多层结构。在金属薄膜层的上表面上形成具有规定图案的电镀抗蚀剂层。在通过电镀暴露的薄金属膜层上形成金属镀层。然后，除去电镀抗蚀剂层，去除具有电镀抗蚀剂层的区域中的金属薄膜层。以这种方式形成包括金属薄膜层和金属镀层的导电图案。在没有导电图案的区域中的基底绝缘层的上表面进行粗糙化处理。覆盖绝缘层形成在基底绝缘层和导电图案的上表面上。这样，印刷电路板就完成了。

18. 发明申请

US20080135280A1 Wired circuit board 有权
公开(公告)号：US20080135280A1
公开(公告)日：2008-06-12
申请号：US12068259
申请日：2008-02-05
申请人： Takashi Oda , Yasufumi Miyake , Tadao Ohkawa
发明人： Takashi Oda , Yasufumi Miyake , Tadao Ohkawa
IPC分类号： H05K3/10 , H05K1/03
CPC分类号： H05K3/107 , H05K1/117 , H05K3/22 , H05K3/244 , H05K2201/0769 , H05K2203/0278 , Y10T29/49126 , Y10T29/4913 , Y10T29/49153 , Y10T29/49155 , Y10T29/49156 , Y10T29/49165
摘要： A wired circuit board having improved adhesion between the conductive pattern and an insulating layer to prevent a plating solution from remaining between a metal plating layer and the insulating layer. The invention prevents ionic impurities in the plating solution from remaining as residual or ionic contamination, thereby preventing a short circuit from developing when electric current flows through the circuit under a high temperature and high humidity environment. Lower end portions of the terminal portions that are formed on an insulating base layer and lower end portions of side surfaces and metal plating layers that cover the terminal portions are embedded in the insulating base layer in a flexible wired circuit board.

19. 发明授权

US07154045B2 Wired circuit board 失效
标题翻译：有线电路板
公开(公告)号：US07154045B2
公开(公告)日：2006-12-26
申请号：US10289178
申请日：2002-11-07
申请人： Yasunari Ooyabu , Takashi Oda , Shinichi Oda
发明人： Yasunari Ooyabu , Takashi Oda , Shinichi Oda
IPC分类号： H01R12/04 , H05K1/11
CPC分类号： H05K1/0259 , H05K3/28 , H05K2201/0317 , H05K2201/0326
摘要： A wired circuit board having a semi-conducting layer which has excellent chemical resistance, such as acid resistance and alkali resistance, provides no possibility of minute particles being mixed into parts mounted on the wired circuit board; and yet has excellent surface resistivity against electrostatic damage. In the wired circuit board having a conductive layer formed on one side of a base insulating layer in the form of a predetermined wired circuit pattern and a cover insulating layer formed on the conductive layer, a base-side semi-conducting layer and a cover-side semi-conducting layer, which include metal oxide, metal nitride or metal carbide, are formed on the other side of the base insulating layer and the cover insulating layer, respectively, by physical vapor deposition (PVD) or preferably by sputtering.
摘要翻译：具有耐酸性和耐碱性优异的耐化学性的半导体层的布线电路板不会将微小颗粒混入安装在布线电路板上的部件中; 并且具有优异的抗静电损伤的表面电阻率。在具有形成在预定布线电路图案形式的基底绝缘层的一侧上的导电层和形成在导电层上的覆盖绝缘层的布线电路板中，基底侧半导电层和覆盖层通过物理气相沉积（PVD）或优选通过溅射分别在基底绝缘层和覆盖绝缘层的另一侧上形成包括金属氧化物，金属氮化物或金属碳化物的侧面半导电层。

20. 发明申请

US20060042823A1 Wired circuit board 有权
标题翻译：有线电路板
公开(公告)号：US20060042823A1
公开(公告)日：2006-03-02
申请号：US11213901
申请日：2005-08-30
申请人： Takashi Oda , Yasufumi Miyake , Tadao Ohkawa
发明人： Takashi Oda , Yasufumi Miyake , Tadao Ohkawa
IPC分类号： H05K1/00
CPC分类号： H05K3/107 , H05K1/117 , H05K3/22 , H05K3/244 , H05K2201/0769 , H05K2203/0278 , Y10T29/49126 , Y10T29/4913 , Y10T29/49153 , Y10T29/49155 , Y10T29/49156 , Y10T29/49165
摘要： A wired circuit board which even when a conductive pattern is formed in the form of fine pitch can provide improved adhesion between the conductive pattern and an insulating layer to prevent a plating solution from remaining between a metal plating layer and the insulating layer, so as to prevent ionic impurities in the plating solution from remaining as residual or ionic contamination, whereby even when electric current flows through the circuit under a high temperature and high humidity environment over a long term, a short circuit from ionic migration can be prevented to suppress insulating failure. Lower end portions of terminal portions 5 formed on an insulating base layer 2 and lower end portions of side surfaces and metal plating layers 6 covering over the terminal portions 5 are embedded in the insulating base layer 2 in a flexible wired circuit board 1 at one longitudinal end portion thereof exposed from an insulating cover layer 4. This can provide the result of preventing infiltration of the plating solution in between the metal plating layers 6 and the insulating base layer 2 when the metal plating layer 6 is formed.
摘要翻译：即使导电图形以细间距的形式形成的布线电路板也能够提高导电图案与绝缘层之间的粘附性，防止电镀液残留在金属镀层与绝缘层之间，防止电镀溶液中的离子杂质残留或残留或离子污染，由此即使长期在高温高湿环境下电流流过电路，也可以防止离子迁移的短路，从而抑制绝缘破坏。形成在绝缘基底层2上的端子部分5的下端部分和覆盖在端子部分5上的侧面的下端部分和金属电镀层6的下端部分在柔性布线电路板1的一个纵向上嵌入绝缘基底层2中其端部从绝缘覆盖层4露出。这可以提供当形成金属镀层6时防止电镀液浸入金属镀层6和绝缘基层2之间的结果。

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