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11. 发明授权

US06441759B1 Multi-bit &Dgr;&Sgr; modulator having linear output 有权
标题翻译：具有线性输出的多位DELTASIGMA调制器
公开(公告)号：US06441759B1
公开(公告)日：2002-08-27
申请号：US09651744
申请日：2000-08-30
申请人： Gopal Raghavan , Henrik T. Jensen
发明人： Gopal Raghavan , Henrik T. Jensen
IPC分类号： H03M300
CPC分类号： H03M3/428 , H03M3/436
摘要： An apparatus and method of improving linearity of a multi bit &Dgr;&Sgr; modulator in which the output of a multi-bit quantizer of a &Dgr;&Sgr; modulator is connected in a feedback loop to a converter where output is a higher frequency single bit data stream which is supplied to a 1-bit digital to analog converter whose output is fed back to the quantizer to provide linearity of the output of the &Dgr;&Sgr; modulator.
摘要翻译：一种提高多位DELTASIGMA调制器的线性度的装置和方法，其中DELTASIGMA调制器的多位量化器的输出在反馈环路中连接到转换器，其中输出是较高频率的单位数据流，其被提供给 1位数模转换器，其输出反馈给量化器，以提供DELTASIGMA调制器输出的线性。

12. 发明授权

US08301097B2 Method and system for low noise amplifier (LNA) gain adjustment through narrowband received signal strength indicator (NRSSI) 有权
标题翻译：通过窄带接收信号强度指示器（NRSSI）对低噪声放大器（LNA）增益调整的方法和系统
公开(公告)号：US08301097B2
公开(公告)日：2012-10-30
申请号：US12115263
申请日：2008-05-05
申请人： Hooman Darabi , Henrik T. Jensen , Brima Ibrahim
发明人： Hooman Darabi , Henrik T. Jensen , Brima Ibrahim
IPC分类号： H04B1/06 , H04B7/00
CPC分类号： H03G1/007 , H03G3/3063 , H03G2201/103 , H03G2201/202 , H03G2201/307
摘要： A method for processing a plurality of signals may include amplifying an input signal and generating a wideband signal from the amplified input signal. The method may further include bandpass filtering the generated wideband signal to generate a narrowband signal, and adjusting amplification of the input signal based on a narrowband received signal strength indication of the generated narrowband signal, and/or a wideband received signal strength indication of the generated wideband signal. The amplified input signal may be downconverted to generate the wideband signal. The amplified input signal may be downconverted to an intermediate frequency (IF) and/or to a baseband signal to generate the wideband signal. At least one blocker signal may be bandpass filtered from the amplified input signal.
摘要翻译：用于处理多个信号的方法可以包括放大输入信号并从放大的输入信号产生宽带信号。该方法还可以包括对生成的宽带信号进行带通滤波以产生窄带信号，以及基于所生成的窄带信号的窄带接收信号强度指示和/或所生成的宽带信号强度指示来调整输入信号的放大宽带信号。放大的输入信号可以被下变频以产生宽带信号。放大的输入信号可以下变频到中频（IF）和/或基带信号以产生宽带信号。至少一个阻塞信号可以从放大的输入信号进行带通滤波。

13. 发明授权

US08112045B2 Translational loop transmitter architecture employing channel power ratio measurements for modulation accuracy calibration 有权
标题翻译：平移环路发射机架构采用信道功率比测量进行调制精度校准
公开(公告)号：US08112045B2
公开(公告)日：2012-02-07
申请号：US12336830
申请日：2008-12-17
申请人： Hong Shi , Henrik T. Jensen
发明人： Hong Shi , Henrik T. Jensen
IPC分类号： G06F15/16
CPC分类号： H04B1/0475
摘要： A Radio Frequency RF transmitter includes a translational loop architecture that supports non-constant envelope modulation types and includes by adjusting the envelope of the translational loop at the translational loop output. The RF transmitter includes an Intermediate Frequency (IF) modulator, a translational loop, an envelope time delay adjust block, an envelope adjust block, and a time delay calibration block. The IF modulator receives a modulated baseband signal and produces a modulated IF signal having a non-constant envelope. The translational loop receives the modulated IF signal and produces a modulated RF signal having a constant envelope. The envelope time delay adjust block receives an envelope signal corresponding to the original modulated signal and produces a time delayed envelope signal based upon a time delay control signal. The envelope adjust block adjusts the modulated RF signal based upon the time delayed envelope signal to produce an envelope adjusted modulated RF signal. Finally, the time delay calibration block receives the envelope adjusted modulated RF signal and produces the time delay control signal.
摘要翻译：射频RF发射机包括支持非恒定包络调制类型的平移环路架构，并且包括通过调整平移环路输出端的平移环路的包络。 RF发射机包括中频（IF）调制器，平移回路，包络时间延迟调整块，包络调整块和时间延迟校准块。 IF调制器接收调制的基带信号并产生具有非恒定包络的调制IF信号。平移环路接收调制的IF信号并产生具有恒定包络线的调制RF信号。包络时间延迟调整块接收对应于原始调制信号的包络信号，并且基于时间延迟控制信号产生时间延迟包络信号。信封调整块基于时间延迟的包络信号来调整调制的RF信号，以产生包络调制的调制的RF信号。最后，延时校准块接收包络调制的调制RF信号并产生延时控制信号。

14. 发明授权

US07903772B2 Digital demodulator with improved hardware and power efficiency 失效
标题翻译：数字解调器具有改进的硬件和电源效率
公开(公告)号：US07903772B2
公开(公告)日：2011-03-08
申请号：US11051580
申请日：2005-02-04
申请人： Henrik T. Jensen
发明人： Henrik T. Jensen
IPC分类号： H04B1/10
CPC分类号： H03D5/00
摘要： A demodulator for use in a receiver converts a digital baseband signal into inbound digital symbols with reduced hardware complexity and reduced power consumption. The demodulator includes a lowpass filter operably coupled to filter the digital baseband signal to produce a filtered digital baseband signal, and an equalizer operating at a first sampling rate to equalize the frequency response of the digital baseband signal such that the receiver overall in-band frequency response approximates the frequency response of a square root raised cosine filter to produce an adjusted digital baseband signal. An interpolator receives the adjusted digital baseband signal at the first sampling rate and interpolates the adjusted digital baseband signal to produce an interpolated digital baseband signal at a second sampling rate, from which the inbound digital symbols can be generated.
摘要翻译：用于接收机的解调器将数字基带信号转换为入站数字符号，降低了硬件复杂度并降低了功耗。解调器包括可操作地耦合以滤波数字基带信号以产生经滤波的数字基带信号的低通滤波器，以及以第一采样率操作的均衡器以均衡数字基带信号的频率响应，使得接收机的整体带内频率响应近似于平方根升余弦滤波器的频率响应，以产生经调整的数字基带信号。内插器以第一采样率接收经调整的数字基带信号，并且内插经调整的数字基带信号以产生内插数字符号的第二采样率的内插数字基带信号。

15. 发明授权

US07593695B2 RF transceiver incorporating dual-use PLL frequency synthesizer 有权
标题翻译： RF收发器采用双用PLL频率合成器
公开(公告)号：US07593695B2
公开(公告)日：2009-09-22
申请号：US11080207
申请日：2005-03-15
申请人： Henrik T. Jensen
发明人： Henrik T. Jensen
IPC分类号： H04B1/40
CPC分类号： H03L7/18 , H03L7/0891 , H04B1/403
摘要： A dual-use PLL frequency synthesizer for use in a transceiver is capable of operating as a local oscillation generator in a receiving mode and as a transmitter in a transmitting mode. The PLL frequency synthesizer includes a digital processor, a Digital-to-Analog Converter (DAC), a low pass filter and a phase locked loop. The digital processor generates a digital signal, in which the digital signal is a modulated digital signal in the transmitting mode, and the digital signal is a reference digital signal in the receiving mode. The DAC converts the digital signal to an analog signal, and the low pass filter filters the analog signal to produce a filtered analog signal. The phase locked loop up-converts the filtered analog signal to an RF signal. In the transmitting mode, the RF signal is a modulated RF signal, and in the receiving mode, the RF signal is a reference RF signal.
摘要翻译：用于收发器的双用PLL频率合成器能够作为接收模式中的本地振荡发生器和作为发射模式的发射机进行操作。 PLL频率合成器包括数字处理器，数模转换器（DAC），低通滤波器和锁相环。数字处理器产生数字信号，其中数字信号是发射模式下的调制数字信号，数字信号是接收模式下的参考数字信号。 DAC将数字信号转换为模拟信号，低通滤波器对模拟信号进行滤波以产生滤波后的模拟信号。锁相环将滤波后的模拟信号上变频为RF信号。在发送模式中，RF信号是经调制的RF信号，在接收模式中，RF信号是参考RF信号。

16. 发明授权

US07573948B2 Radio transmitter incorporating digital modulator and circuitry to accommodate baseband processor with analog interface 失效
标题翻译：无线发射机采用数字调制器和电路，以适应具有模拟接口的基带处理器
公开(公告)号：US07573948B2
公开(公告)日：2009-08-11
申请号：US10992570
申请日：2004-11-18
申请人： Henrik T. Jensen
发明人： Henrik T. Jensen
IPC分类号： H04L27/00
CPC分类号： H04B1/04 , H04B1/0007 , H04B2001/0491 , H04L27/34 , H04L2027/0018 , H04L2027/003 , H04L2027/0057
摘要： A radio frequency (RF) transmitter includes a digital radio processor and a baseband processor. A complex analog-to-digital converter (ADC) within the radio processor provides an analog interface to the baseband processor to receive an analog complex modulated baseband signal and convert the analog complex modulated baseband signal to a digital complex modulated baseband signal. A demodulator within the radio processor demodulates the digital complex modulated baseband signal to recreate the original transmit digital data as a demodulated digital signal. The demodulated digital signal is processed by a digital processor in the radio processor to mitigate the effects of various imperfections in the radio processor circuitry.
摘要翻译：射频（RF）发射机包括数字无线电处理器和基带处理器。无线电处理器内的复数模数转换器（ADC）为基带处理器提供模拟接口，以接收模拟复调制基带信号，并将模拟复调制基带信号转换为数字复调制基带信号。无线电处理器内的解调器解调数字复调制基带信号，以重构原始发射数字数据作为解调数字信号。解调的数字信号由无线电处理器中的数字处理器处理以减轻无线电处理器电路中各种缺陷的影响。

17. 发明授权

US07538623B2 Phase locked loop modulator calibration techniques 有权
标题翻译：锁相环调制器校准技术
公开(公告)号：US07538623B2
公开(公告)日：2009-05-26
申请号：US11281165
申请日：2005-11-16
申请人： Henrik T. Jensen , Hea Joung Kim
发明人： Henrik T. Jensen , Hea Joung Kim
IPC分类号： H03L7/08 , H03L7/099 , H04B7/00
CPC分类号： H03C3/0991 , H03L7/0898
摘要： A method for calibrating a phase locked loop begins by determining a gain offset of a voltage controlled oscillator of the phase locked loop. The processing then continues by adjusting current of a charge pump of the phase locked loop based on the gain offset.
摘要翻译：通过确定锁相环的压控振荡器的增益偏移开始校准锁相环的方法。然后通过基于增益偏移来调节锁相环的电荷泵的电流来继续处理。

18. 发明授权

US07522658B2 Design method and implementation of optimal linear IIR equalizers for RF transceivers 失效
标题翻译： RF收发器的最佳线性IIR均衡器的设计方法和实现
公开(公告)号：US07522658B2
公开(公告)日：2009-04-21
申请号：US10993294
申请日：2004-11-19
申请人： Henrik T. Jensen
发明人： Henrik T. Jensen
IPC分类号： H04B1/38
CPC分类号： H04L27/368
摘要： A digital filter with equalizers and a corresponding method for optimizing a linear equalizer of an RF transceiver determining filter characteristics of the specified analog filter, determining total signal filtering of the RF transceiver based upon a discrete time model of the specified analog filter and upon characteristics of the digital filter, determining an inverse of the determined total signal filtering; multiplying the inverse of the determined total signal filtering with the determined total signal filtering and optimally matching the desired equalizer filtering characteristic with an IIR magnitude equalizer to determine an optimal approximation of a magnitude response of the discrete time model of the specified analog filter. Thereafter, the method includes adding an inverse of the optimal approximation of the magnitude response and optimally matching the pre-distorting group delay response of the filter to obtain an optimal approximation to the pre-distorting group delay response of the filter.
摘要翻译：一种具有均衡器的数字滤波器和用于优化RF收发器的线性均衡器的相应方法，其确定指定的模拟滤波器的滤波器特性，基于指定的模拟滤波器的离散时间模型确定RF收发器的总信号滤波，数字滤波器，确定所确定的总信号滤波的逆; 将所确定的总信号滤波的逆与所确定的总信号滤波相乘，并将所需的均衡器滤波特性与IIR幅度均衡器进行最佳匹配，以确定指定模拟滤波器的离散时间模型的幅度响应的最佳近似。此后，该方法包括增加幅度响应的最佳近似的逆，并且最佳地匹配滤波器的失真前延迟响应，以获得滤波器的预失真群延迟响应的最佳近似。

19. 发明申请

US20090016466A1 Complex digital phase locked loop for use in a demodulator and method of optimal coefficient selection 有权
标题翻译：用于解调器的复数数字锁相环和最佳系数选择方法
公开(公告)号：US20090016466A1
公开(公告)日：2009-01-15
申请号：US12234343
申请日：2008-09-19
申请人： Henrik T. Jensen
发明人： Henrik T. Jensen
IPC分类号： H03D3/18
CPC分类号： H03D3/24 , H03D2200/0082
摘要： A complex digital phase locked loop for use in a digital demodulator includes a phase detector for producing a phase error indicative of a difference in phase between a complex digital input signal and a complex digital feedback signal. The phase error is input to a controller, which multiplies the phase error by a gain factor selected to stabilize and optimize the phase locked loop and produces an output signal for use in extracting a frequency deviation present in the complex digital input signal. The output signal is also input to a numerically controlled oscillator that tracks the phase of the complex digital input signal based on the output signal and produces the complex digital feedback signal.
摘要翻译：用于数字解调器的复数数字锁相环包括相位检测器，用于产生指示复数数字输入信号和复数数字反馈信号之间的相位差的相位误差。将相位误差输入到控制器，该控制器将相位误差乘以所选择的增益因子，以稳定和优化锁相环，并产生用于提取复数字输入信号中存在的频率偏差的输出信号。输出信号也输入到数控振荡器，该振荡器基于输出信号跟踪复数数字输入信号的相位，并产生复数数字反馈信号。

20. 发明授权

US07242336B1 Continuous-time delta-sigma ADC for a radio receiver employing 200 kHz IF 有权
标题翻译：采用200 kHz IF的无线电接收机的连续时间Δ-ΣADC
公开(公告)号：US07242336B1
公开(公告)日：2007-07-10
申请号：US11369045
申请日：2006-03-06
申请人： Henrik T. Jensen
发明人： Henrik T. Jensen
IPC分类号： H03M3/00
CPC分类号： H03M3/396 , H03M3/406 , H03M3/458
摘要： A Continuous-Time Delta-Sigma Analog-to-Digital Converter (CTΔΣADC) for a radio frequency (RF) receiver employing a 200 kHz IF realizes an optimal signal-to-noise ratio using a programmable resonator that is set to resonate at 200 kHz. The programmable resonator is operably coupled to receive both an analog input signal at a low IF of 200 kHz and an analog feedback signal. From the analog input signal and the analog feedback signal, the programmable resonator produces a resonate signal at the low IF, and provides the resonate signal to a quantizer. The quantizer produces a digital output having a digital value coarsely reflecting an amplitude of the analog input signal. The CTΔΣADC further includes at least one programmable digital-to-analog converter (DAC) operably coupled to receive the digital output and to convert the digital output into the analog feedback signal provided to the programmable resonator.
摘要翻译：采用200 kHz IF的射频（RF）接收机的连续时间Delta-Sigma模数转换器（CTDeltaSigmaADC）使用可设置为在200 kHz谐振的可编程谐振器实现最佳信噪比。可编程谐振器可操作地耦合以接收200kHz的低IF的模拟输入信号和模拟反馈信号。从模拟输入信号和模拟反馈信号，可编程谐振器在低IF处产生谐振信号，并将谐振信号提供给量化器。量化器产生具有粗略地反映模拟输入信号的幅度的数字值的数字输出。 CTDeltaSigmaADC还包括至少一个可编程数字 - 模拟转换器（DAC），可操作地耦合以接收数字输出并将数字输出转换为提供给可编程谐振器的模拟反馈信号。

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