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11. 发明申请

US20090166840A1 WAFER-LEVEL STACK PACKAGE 审中-公开
标题翻译： WAFER级堆叠包
公开(公告)号：US20090166840A1
公开(公告)日：2009-07-02
申请号：US12342689
申请日：2008-12-23
申请人： Sun-Won KANG , Seung-Duk Baek
发明人： Sun-Won KANG , Seung-Duk Baek
IPC分类号： H01L23/48
CPC分类号： H01L25/0657 , H01L21/76898 , H01L25/50 , H01L2224/05001 , H01L2224/05009 , H01L2224/05548 , H01L2224/16 , H01L2224/16145 , H01L2225/06513 , H01L2225/06527 , H01L2225/06541 , H01L2225/06551 , H01L2924/00014 , H01L2924/15311 , H01L2224/05599 , H01L2224/05099
摘要： A wafer-level stack package includes semiconductor chips, first connection members, a second connection member, a substrate and an external connection terminal. The semiconductor chips have a power/ground pad and a signal pad. The first connection members are electrically connected to the power/ground pad and the signal pad of each of the semiconductor chips. The second connection member is electrically connected to at least one of the power/ground pads of each of the semiconductor chips, the power/ground pads being connected to the first connection members. The substrate supports the stacked semiconductor chips, the substrate including wirings that are electrically connected to the first connection members and the second connection member. The external connection terminal is provided on a surface of the substrate opposite to a surface where the semiconductor chips are stacked, wherein the external connection terminals are electrically connected to the wirings, respectively.
摘要翻译：晶圆级堆叠封装包括半导体芯片，第一连接构件，第二连接构件，基板和外部连接端子。半导体芯片具有电源/接地焊盘和信号焊盘。第一连接构件电连接到电源/接地焊盘和每个半导体芯片的信号焊盘。第二连接构件电连接到每个半导体芯片的功率/接地焊盘中的至少一个，电源/接地焊盘连接到第一连接构件。基板支撑层叠的半导体芯片，基板包括电连接到第一连接构件和第二连接构件的布线。外部连接端子设置在与半导体芯片堆叠的表面相对的表面上，其中外部连接端子分别电连接到布线。

12. 发明申请

US20090108469A1 CHIP STACK PACKAGE 有权
标题翻译：芯片堆栈包
公开(公告)号：US20090108469A1
公开(公告)日：2009-04-30
申请号：US12171035
申请日：2008-07-10
申请人： Sun-Won KANG , Seung-Duk BAEK , Jong-Joo LEE
发明人： Sun-Won KANG , Seung-Duk BAEK , Jong-Joo LEE
IPC分类号： H01L23/538
CPC分类号： H01L25/0657 , H01L2224/05573 , H01L2224/13025 , H01L2224/16145 , H01L2225/06513 , H01L2225/06541 , H01L2924/15311
摘要： A chip stack package includes a plurality of chips that are stacked by using adhesive layers as intermediary media, and a through via electrode formed through the chips to electrically couple the chips. The through via electrode is classified as a power supply through via electrode, a ground through via electrode, or a signal transfer through via electrode. The power supply through via electrode and the ground through via electrode are formed of a first material such as copper, and the signal transfer through via electrode is formed of second material such as polycrystalline silicon doped with impurities. The signal transfer through via electrode may have a diametrically smaller cross section than that of each of the power supply through via electrode and the ground through via electrode regardless of their resistivities.
摘要翻译：芯片堆叠包括通过使用粘合剂层作为中间介质堆叠的多个芯片，以及通过芯片形成的通孔电极以电耦合芯片。通孔电极通过通孔电极，通过通孔电极的接地或通过通孔电极的信号传输分类为电源。通过通孔电极和通过通孔电极的接地的电源由诸如铜的第一材料形成，并且通过通孔电极的信号传输由掺杂杂质的多晶硅等第二材料形成。通过通孔电极的信号传输可以具有比通过通孔电极和通过通孔电极的接地的每个电源的直径更小的横截面，而不管其电阻率如何。

13. 发明申请

US20080246113A1 SEMICONDUCTOR DEVICE INCLUDING REDISTRIBUTION LINE STRUCTURE AND METHOD OF FABRICATING THE SAME 有权
标题翻译：包括重新分配线结构的半导体器件及其制造方法
公开(公告)号：US20080246113A1
公开(公告)日：2008-10-09
申请号：US12098352
申请日：2008-04-04
申请人： Seung-Duk BAEK , Sun-Won KANG , Hyun-Soo CHUNG
发明人： Seung-Duk BAEK , Sun-Won KANG , Hyun-Soo CHUNG
IPC分类号： H01L29/00
CPC分类号： H01L23/525 , H01L23/16 , H01L23/3114 , H01L23/3192 , H01L23/562 , H01L24/02 , H01L2224/02233 , H01L2924/01006 , H01L2924/01014 , H01L2924/01033 , H01L2924/01075 , H01L2924/01078 , H01L2924/014 , H01L2924/05042 , H01L2924/181 , H01L2924/00
摘要： The invention provides a semiconductor device. The semiconductor device includes a semiconductor chip having an active surface on which pads are disposed, a passivation layer pattern disposed to cover the active surface of the semiconductor chip and to expose the pads, a first insulation layer pattern disposed on the passivation layer pattern, a second insulation layer pattern disposed on only a portion of the first insulation layer pattern, and redistribution line patterns electrically connected to the pads and disposed so as to extend across the second insulation layer pattern and the first insulation layer pattern. A method of fabricating the same is also provided.
摘要翻译：本发明提供一种半导体器件。半导体器件包括具有布置有焊盘的有源表面的半导体芯片，布置成覆盖半导体芯片的有源表面并暴露焊盘的钝化层图案，设置在钝化层图案上的第一绝缘层图案，第二绝缘层图案仅设置在第一绝缘层图案的一部分上，再分布线图形电连接到焊盘并且被设置成跨越第二绝缘层图案和第一绝缘层图案延伸。还提供了一种制造该方法的方法。

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