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11. 发明授权

US09859235B2 Underbump metallization structure 有权
公开(公告)号：US09859235B2
公开(公告)日：2018-01-02
申请号：US12619503
申请日：2009-11-16
申请人： Yu-Wen Liu , Hao-Yi Tsai , Hsien-Wei Chen , Shin-Puu Jeng , Ying-Ju Chen , Shang-Yun Hou , Pei-Haw Tsao , Chen-Hua Yu
发明人： Yu-Wen Liu , Hao-Yi Tsai , Hsien-Wei Chen , Shin-Puu Jeng , Ying-Ju Chen , Shang-Yun Hou , Pei-Haw Tsao , Chen-Hua Yu
IPC分类号： H01L23/488 , H01L23/00 , H01L23/31
CPC分类号： H01L24/05 , H01L23/3157 , H01L24/03 , H01L24/11 , H01L24/13 , H01L2224/02125 , H01L2224/0215 , H01L2224/0345 , H01L2224/03462 , H01L2224/0401 , H01L2224/05018 , H01L2224/05027 , H01L2224/0508 , H01L2224/05096 , H01L2224/05147 , H01L2224/05155 , H01L2224/05166 , H01L2224/05171 , H01L2224/05541 , H01L2224/05552 , H01L2224/05553 , H01L2224/05557 , H01L2224/05558 , H01L2224/05566 , H01L2224/05569 , H01L2224/05572 , H01L2224/05573 , H01L2224/05644 , H01L2224/05647 , H01L2224/05655 , H01L2224/1132 , H01L2224/11334 , H01L2224/1145 , H01L2224/11462 , H01L2224/11849 , H01L2224/13005 , H01L2224/13007 , H01L2224/13111 , H01L2224/13139 , H01L2224/13147 , H01L2924/00013 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/01022 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/05042 , H01L2924/05442 , H01L2924/00014 , H01L2924/2064 , H01L2224/13099 , H01L2224/05099 , H01L2224/13599 , H01L2224/05599 , H01L2224/29099 , H01L2224/29599
摘要： A system and method for forming an underbump metallization (UBM) is presented. A preferred embodiment includes a raised UBM which extends through a passivation layer so as to make contact with a contact pad while retaining enough of the passivation layer between the contact pad and the UBM to adequately handle the peeling and shear stress that results from CTE mismatch and subsequent thermal processing. The UBM contact is preferably formed in either an octagonal ring shape or an array of contacts.

12. 发明授权

US09093411B2 Pad structure having contact bars extending into substrate and wafer having the pad structure 有权
标题翻译：衬垫结构，其具有延伸到衬底中的接触棒和具有衬垫结构的晶片
公开(公告)号：US09093411B2
公开(公告)日：2015-07-28
申请号：US12984669
申请日：2011-01-05
申请人： Ying-Ju Chen , Hsien-Wei Chen , Hao-Yi Tsai , Mirng-Ji Lii
发明人： Ying-Ju Chen , Hsien-Wei Chen , Hao-Yi Tsai , Mirng-Ji Lii
IPC分类号： H01L21/66 , H01L23/00
CPC分类号： H01L22/34 , H01L22/32 , H01L23/50 , H01L23/5226 , H01L23/5283 , H01L23/53209 , H01L23/53214 , H01L23/53228 , H01L23/5383 , H01L24/05 , H01L29/0649 , H01L2224/02166 , H01L2224/05093 , H01L2924/01013 , H01L2924/01029 , H01L2924/01074 , H01L2924/14 , H01L2924/00
摘要： A pad structure in a semiconductor wafer for wafer testing is described. The pad structure includes at least two metal pads connected there-between by a plurality of conductive visa in one or more insulation layers. A plurality of contact bars in contact with the bottom-most metal pad extends substantially vertically from the bottom-most metal pad into the substrate. An isolation structure substantially surrounds the plurality of contact bars to isolate the pad structure.
摘要翻译：描述用于晶片测试的半导体晶片中的焊盘结构。焊盘结构包括至少两个连接在其上的金属焊盘，其间通过一个或多个绝缘层中的多个导电签证。与最底部的金属焊盘接触的多个接触棒从最底部的金属焊盘基本垂直地延伸到衬底中。隔离结构基本上围绕多个接触杆以隔离垫结构。

13. 发明授权

US08450126B2 Semiconductor test pad structures 有权
标题翻译：半导体测试板结构
公开(公告)号：US08450126B2
公开(公告)日：2013-05-28
申请号：US13197003
申请日：2011-08-03
申请人： Hsien-Wei Chen , Ying-Ju Chen , Yu-Wen Liu , Hao-Yi Tsai , Shin-Puu Jeng
发明人： Hsien-Wei Chen , Ying-Ju Chen , Yu-Wen Liu , Hao-Yi Tsai , Shin-Puu Jeng
IPC分类号： H01L21/66 , G01R31/26
CPC分类号： H01L22/34 , H01L24/05 , H01L2924/14 , H01L2924/1461 , H01L2924/00
摘要： A semiconductor test pad interconnect structure with integrated die-separation protective barriers. The interconnect structure includes a plurality of stacked metal layers each having an electrically conductive test pad separated from other test pads by a dielectric material layer. In one embodiment, at least one metallic via bar is embedded into the interconnect structure and electrically interconnects each of the test pads in the metal layers together. The via bar extends substantially along an entire first side defined by each test pad in some embodiments. In other embodiments, a pair of opposing via bars may be provided that are arranged on opposite sides of a die singulation saw cut line defined in a scribe band on a semiconductor wafer.
摘要翻译：具有集成的模具隔离保护屏障的半导体测试焊盘互连结构。互连结构包括多个堆叠的金属层，每个层具有通过介电材料层与其它测试焊盘分离的导电测试焊盘。在一个实施例中，至少一个金属通孔条被嵌入到互连结构中，并将金属层中的每个测试焊盘电连接在一起。在一些实施例中，通孔棒基本上沿着由每个测试垫限定的整个第一侧面延伸。在其他实施例中，可以提供一对相对的通孔条，其布置在限定在半导体晶片上的划线带中的模切单切锯切线的相对侧上。

14. 发明授权

US08581423B2 Double solid metal pad with reduced area 有权
标题翻译：双面实心金属垫，面积减小
公开(公告)号：US08581423B2
公开(公告)日：2013-11-12
申请号：US12272501
申请日：2008-11-17
申请人： Hsien-Wei Chen , Yu-Wen Liu , Hao-Yi Tsai , Shin-Puu Jeng , Ying-Ju Chen
发明人： Hsien-Wei Chen , Yu-Wen Liu , Hao-Yi Tsai , Shin-Puu Jeng , Ying-Ju Chen
IPC分类号： H01L23/52 , H01L23/48 , H01L29/40
CPC分类号： H01L24/03 , H01L23/3192 , H01L23/585 , H01L24/05 , H01L24/08 , H01L24/45 , H01L24/48 , H01L24/85 , H01L2224/02126 , H01L2224/02166 , H01L2224/04042 , H01L2224/05009 , H01L2224/05093 , H01L2224/05094 , H01L2224/05095 , H01L2224/05552 , H01L2224/05553 , H01L2224/05556 , H01L2224/05624 , H01L2224/05639 , H01L2224/05644 , H01L2224/05647 , H01L2224/05655 , H01L2224/05684 , H01L2224/45015 , H01L2224/45124 , H01L2224/45144 , H01L2224/48463 , H01L2224/48624 , H01L2224/48639 , H01L2224/48644 , H01L2224/48647 , H01L2224/48655 , H01L2224/48684 , H01L2224/48724 , H01L2224/48739 , H01L2224/48747 , H01L2224/48755 , H01L2224/48784 , H01L2224/85 , H01L2224/85205 , H01L2924/00014 , H01L2924/01013 , H01L2924/01014 , H01L2924/01019 , H01L2924/01027 , H01L2924/01028 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/01047 , H01L2924/01074 , H01L2924/01079 , H01L2924/01082 , H01L2924/05042 , H01L2924/14 , H01L2924/19041 , H01L2924/19043 , H01L2924/30105 , H01L2924/351 , H01L2924/00 , H01L2224/48744
摘要： An integrated circuit structure includes a bond pad; an Mtop pad located directly underlying the bond pad; an Mtop-1 pad having at least a portion directly underlying the Mtop pad, wherein at least one of the Mtop pad and the Mtop-1 pad has a horizontal dimension smaller than a horizontal dimension of the bond pad; a plurality of vias interconnecting the Mtop pad and the Mtop-1 pad; and a bond ball on the bond pad. Each of the Mtop pad and the Mtop-1 pad has positive enclosures to the bond ball in all horizontal directions.
摘要翻译：集成电路结构包括接合焊盘; 直接位于接合垫下面的Mtop垫; Mtop-1垫具有直接位于Mtop垫下方的至少一部分，其中Mtop垫和Mtop-1垫中的至少一个具有小于接合垫的水平尺寸的水平尺寸; 将Mtop焊盘和Mtop-1焊盘互连的多个通孔; 和粘结垫上的粘结球。每个Mtop垫和Mtop-1垫在所有水平方向上都具有粘结球的正面外壳。

15. 发明申请

US20110287627A1 SEMICONDUCTOR TEST PAD STRUCTURES 有权
公开(公告)号：US20110287627A1
公开(公告)日：2011-11-24
申请号：US13197003
申请日：2011-08-03
申请人： Hsien-Wei Chen , Ying-Ju Chen , Yu-Wen Liu , Hao-Yi Tsai , Shin-Puu Jeng
发明人： Hsien-Wei Chen , Ying-Ju Chen , Yu-Wen Liu , Hao-Yi Tsai , Shin-Puu Jeng
IPC分类号： H01L21/768
CPC分类号： H01L22/34 , H01L24/05 , H01L2924/14 , H01L2924/1461 , H01L2924/00
摘要： A semiconductor test pad interconnect structure with integrated die-separation protective barriers. The interconnect structure includes a plurality of stacked metal layers each having an electrically conductive test pad separated from other test pads by a dielectric material layer. In one embodiment, at least one metallic via bar is embedded into the interconnect structure and electrically interconnects each of the test pads in the metal layers together. The via bar extends substantially along an entire first side defined by each test pad in some embodiments. In other embodiments, a pair of opposing via bars may be provided that are arranged on opposite sides of a die singulation saw cut line defined in a scribe band on a semiconductor wafer.
摘要翻译：具有集成的模具隔离保护屏障的半导体测试焊盘互连结构。互连结构包括多个堆叠的金属层，每个层具有通过介电材料层与其它测试焊盘分离的导电测试焊盘。在一个实施例中，至少一个金属通孔条被嵌入到互连结构中，并将金属层中的每个测试焊盘电连接在一起。在一些实施例中，通孔棒基本上沿着由每个测试垫限定的整个第一侧面延伸。在其它实施例中，可以提供一对相对的通孔条，其布置在限定在半导体晶片上的划线带中的模切单切锯切线的相对侧上。

16. 发明授权

US08013333B2 Semiconductor test pad structures 有权
标题翻译：半导体测试板结构
公开(公告)号：US08013333B2
公开(公告)日：2011-09-06
申请号：US12267021
申请日：2008-11-07
申请人： Hsien-Wei Chen , Ying-Ju Chen , Yu-Wen Liu , Hao-Yi Tsai , Shin-Puu Jeng
发明人： Hsien-Wei Chen , Ying-Ju Chen , Yu-Wen Liu , Hao-Yi Tsai , Shin-Puu Jeng
IPC分类号： H01L23/58
CPC分类号： H01L22/34 , H01L24/05 , H01L2924/14 , H01L2924/1461 , H01L2924/00
摘要： A semiconductor test pad interconnect structure with integrated die-separation protective barriers. The interconnect structure includes a plurality of stacked metal layers each having an electrically conductive test pad separated from other test pads by a dielectric material layer. In one embodiment, at least one metallic via bar is embedded into the interconnect structure and electrically interconnects each of the test pads in the metal layers together. The via bar extends substantially along an entire first side defined by each test pad in some embodiments. In other embodiments, a pair of opposing via bars may be provided that are arranged on opposite sides of a die singulation saw cut line defined in a scribe band on a semiconductor wafer.
摘要翻译：具有集成的模具隔离保护屏障的半导体测试焊盘互连结构。互连结构包括多个堆叠的金属层，每个层具有通过介电材料层与其它测试焊盘分离的导电测试焊盘。在一个实施例中，至少一个金属通孔条被嵌入到互连结构中，并将金属层中的每个测试焊盘电连接在一起。在一些实施例中，通孔棒基本上沿着由每个测试垫限定的整个第一侧面延伸。在其他实施例中，可以提供一对相对的通孔条，其布置在限定在半导体晶片上的划线带中的模切单切锯切线的相对侧上。

17. 发明授权

US07936067B2 Backend interconnect scheme with middle dielectric layer having improved strength 有权
标题翻译：具有中等介电层的后端互连方案具有改进的强度
公开(公告)号：US07936067B2
公开(公告)日：2011-05-03
申请号：US12121541
申请日：2008-05-15
申请人： Hao-Yi Tsai , Yu-Wen Liu , Hsien-Wei Chen , Ying-Ju Chen , Shin-Puu Jeng
发明人： Hao-Yi Tsai , Yu-Wen Liu , Hsien-Wei Chen , Ying-Ju Chen , Shin-Puu Jeng
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L21/76835 , H01L23/5222 , H01L23/5329 , H01L24/05 , H01L2224/02166 , H01L2224/05093 , H01L2224/05556 , H01L2924/14 , H01L2924/00
摘要： An integrated circuit structure includes a first, a second and a third metallization layer. The first metallization layer includes a first dielectric layer having a first k value; and first metal lines in the first dielectric layer. The second metallization layer is over the first metallization layer, and includes a second dielectric layer having a second k value greater than the first k value; and second metal lines in the second dielectric layer. The third metallization layer is over the second metallization layer, and includes a third dielectric layer having a third k value; and third metal lines in the third dielectric layer. The integrated circuit structure further includes a bottom passivation layer over the third metallization layer.
摘要翻译：集成电路结构包括第一，第二和第三金属化层。第一金属化层包括具有第一k值的第一介电层; 和第一介电层中的第一金属线。第二金属化层在第一金属化层之上，并且包括具有大于第一k值的第二k值的第二介电层; 和第二介电层中的第二金属线。第三金属化层在第二金属化层之上，并且包括具有第三k值的第三介电层; 和第三介电层中的第三金属线。集成电路结构还包括在第三金属化层上的底部钝化层。

18. 发明申请

US20100283148A1 Bump Pad Structure 有权
标题翻译：凸块结构
公开(公告)号：US20100283148A1
公开(公告)日：2010-11-11
申请号：US12726449
申请日：2010-03-18
申请人： Hao-Yi Tsai , Hsien-Wei Chen , Yu-Wen Liu , Ying-Ju Chen , Hsiu-Ping Wei
发明人： Hao-Yi Tsai , Hsien-Wei Chen , Yu-Wen Liu , Ying-Ju Chen , Hsiu-Ping Wei
IPC分类号： H01L23/485 , H01L21/60
CPC分类号： H01L24/05 , H01L21/768 , H01L21/76877 , H01L23/48 , H01L23/481 , H01L24/03 , H01L24/13 , H01L2224/0401 , H01L2224/05012 , H01L2224/0509 , H01L2224/05092 , H01L2224/05094 , H01L2224/05095 , H01L2224/05096 , H01L2224/05124 , H01L2224/05147 , H01L2224/05552 , H01L2224/05569 , H01L2224/05572 , H01L2224/05599 , H01L2224/131 , H01L2924/00013 , H01L2924/00014 , H01L2924/01002 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/01029 , H01L2924/01033 , H01L2924/01075 , H01L2924/01078 , H01L2924/014 , H01L2224/13099 , H01L2224/13599 , H01L2224/05099 , H01L2224/29099 , H01L2224/29599 , H01L2924/00012
摘要： An embodiment is a bump bond pad structure that comprises a substrate comprising a top layer, a reinforcement pad disposed on the top layer, an intermediate layer above the top layer, an intermediate connection pad disposed on the intermediate layer, an outer layer above the intermediate layer, and an under bump metal (UBM) connected to the intermediate connection pad through an opening in the outer layer. Further embodiments may comprise a via mechanically coupling the intermediate connection pad to the reinforcement pad. The via may comprise a feature selected from the group consisting of a solid via, a substantially ring-shaped via, or a five by five array of vias. Yet, a further embodiment may comprise a secondary reinforcement pad, and a second via mechanically coupling the reinforcement pad to the secondary reinforcement pad.
摘要翻译：一个实施例是一种凸块接合焊盘结构，其包括基板，该基板包括顶层，设置在顶层上的加强垫，顶层上的中间层，设置在中间层上的中间连接垫，中间层上方的外层层和通过外层中的开口连接到中间连接焊盘的凸块下金属（UBM）。另外的实施例可以包括将中间连接垫机械连接到加强垫的通孔。通孔可以包括选自由固体通孔，基本上环形的通孔或五个五孔的通孔组成的组的特征。然而，另一实施例可以包括辅助加强垫，以及将加强垫机械连接到辅助加强垫的第二通孔。

19. 发明申请

US20100187687A1 Underbump Metallization Structure 有权
标题翻译：底部金属化结构
公开(公告)号：US20100187687A1
公开(公告)日：2010-07-29
申请号：US12619503
申请日：2009-11-16
申请人： Yu-Wen Liu , Hao-Yi Tsai , Hsien-Wei Chen , Shin-Puu Jeng , Ying-Ju Chen , Shang-Yun Hou , Pei-Haw Tsao , Chen-Hua Yu
发明人： Yu-Wen Liu , Hao-Yi Tsai , Hsien-Wei Chen , Shin-Puu Jeng , Ying-Ju Chen , Shang-Yun Hou , Pei-Haw Tsao , Chen-Hua Yu
IPC分类号： H01L23/488 , H01L21/60
CPC分类号： H01L24/05 , H01L23/3157 , H01L24/03 , H01L24/11 , H01L24/13 , H01L2224/02125 , H01L2224/0215 , H01L2224/0345 , H01L2224/03462 , H01L2224/0401 , H01L2224/05018 , H01L2224/05027 , H01L2224/0508 , H01L2224/05096 , H01L2224/05147 , H01L2224/05155 , H01L2224/05166 , H01L2224/05171 , H01L2224/05541 , H01L2224/05552 , H01L2224/05553 , H01L2224/05557 , H01L2224/05558 , H01L2224/05566 , H01L2224/05569 , H01L2224/05572 , H01L2224/05573 , H01L2224/05644 , H01L2224/05647 , H01L2224/05655 , H01L2224/1132 , H01L2224/11334 , H01L2224/1145 , H01L2224/11462 , H01L2224/11849 , H01L2224/13005 , H01L2224/13007 , H01L2224/13111 , H01L2224/13139 , H01L2224/13147 , H01L2924/00013 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/01022 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/05042 , H01L2924/05442 , H01L2924/00014 , H01L2924/2064 , H01L2224/13099 , H01L2224/05099 , H01L2224/13599 , H01L2224/05599 , H01L2224/29099 , H01L2224/29599
摘要： A system and method for forming an underbump metallization (UBM) is presented. A preferred embodiment includes a raised UBM which extends through a passivation layer so as to make contact with a contact pad while retaining enough of the passivation layer between the contact pad and the UBM to adequately handle the peeling and shear stress that results from CTE mismatch and subsequent thermal processing. The UBM contact is preferably formed in either an octagonal ring shape or an array of contacts.
摘要翻译：提出了一种用于形成底部金属化（UBM）的系统和方法。优选实施例包括凸起的UBM，其延伸穿过钝化层以便与接触焊盘接触，同时在接触焊盘和UBM之间保留足够的钝化层以充分地处理由CTE失配引起的剥离和剪切应力，后续热处理。 UBM触点优选地形成为八边形环形或触点阵列。

20. 发明授权

US08227916B2 Package structure and method for reducing dielectric layer delamination 有权
标题翻译：用于减少介电层分层的封装结构和方法
公开(公告)号：US08227916B2
公开(公告)日：2012-07-24
申请号：US12757440
申请日：2010-04-09
申请人： Hsiu-Ping Wei , Shin-Puu Jeng , Hao-Yi Tsai , Hsien-Wei Chen , Yu-Wen Liu , Ying-Ju Chen , Tzuan-Horng Liu
发明人： Hsiu-Ping Wei , Shin-Puu Jeng , Hao-Yi Tsai , Hsien-Wei Chen , Yu-Wen Liu , Ying-Ju Chen , Tzuan-Horng Liu
IPC分类号： H01L23/498 , H01L21/3205
CPC分类号： H01L21/76801 , H01L23/3192 , H01L23/522 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/13 , H01L2224/02166 , H01L2224/0345 , H01L2224/03452 , H01L2224/03462 , H01L2224/03464 , H01L2224/0401 , H01L2224/04042 , H01L2224/05008 , H01L2224/05022 , H01L2224/05096 , H01L2224/05124 , H01L2224/05147 , H01L2224/05572 , H01L2224/05624 , H01L2224/05647 , H01L2224/05655 , H01L2224/05666 , H01L2224/05671 , H01L2224/1145 , H01L2224/11452 , H01L2224/11462 , H01L2224/11464 , H01L2224/13116 , H01L2224/13147 , H01L2224/16 , H01L2924/0002 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/01024 , H01L2924/01029 , H01L2924/0105 , H01L2924/01074 , H01L2924/01078 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H01L2924/00014 , H01L2224/05552 , H01L2924/00
摘要： A semiconductor package structure is provided. The structure includes a semiconductor chip having a plurality of interconnect layers formed thereover. A first passivation layer is formed over the plurality of interconnect layers. A stress buffer layer is formed over the first passivation layer. A bonding pad is formed over the stress buffer layer. A second passivation layer is formed over a portion of the bonding pad, the second passivation having at least one opening therein exposing a portion of the bonding pad.
摘要翻译：提供半导体封装结构。该结构包括其上形成有多个互连层的半导体芯片。在多个互连层上形成第一钝化层。在第一钝化层上形成应力缓冲层。在应力缓冲层上形成接合焊盘。在接合焊盘的一部分上形成第二钝化层，第二钝化层具有至少一个开口，露出焊接区的一部分。

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