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11. 发明专利

DE3103143A1 未知
公开(公告)号：DE3103143A1
公开(公告)日：1981-12-03
申请号：DE3103143
申请日：1981-01-30
申请人： HITACHI LTD
发明人： SUGIURA JUNE , KOSA YASUNOBU , KOMORI KAZUHIRO , UCHIDA KEN , SHIMIZU SHINJI
IPC分类号： H01L27/112 , G11C5/02 , G11C16/04 , G11C17/00 , H01L21/8246 , H01L21/8247 , H01L23/522 , H01L27/115 , H01L29/788 , H01L29/792 , G11C11/40 , G11C17/06 , H01L21/72 , H05K7/06
摘要： A semiconductor memory device includes a number of conductive layers for bit and selection lines alternately juxtaposed on the surface of a semiconductor substrate beneath a field insulating layer, with a number of MOS type memory cells arranged between the conductive layers for the bit and selection lines.

12. 发明专利

JPH01184956A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPH01184956A
公开(公告)日：1989-07-24
申请号：JP831888
申请日：1988-01-20
申请人： HITACHI LTD
发明人： TAKEDA TOSHIFUMI , MEGURO SATOSHI , UCHIDA KEN
IPC分类号： H01L21/336 , H01L29/78
摘要： PURPOSE:To contrive the improvement of an integration density in a peripheral circuit by a method wherein, after the gate electrode of a MISFET is formed, an impurity is ion-implanted at a high energy transmitting the gate electrode to control the threshold voltage of this MISFET. CONSTITUTION:A photoresist 10 of a prescribed form is formed and thereafter, boron, for example, is ion implanted on the conditions of 180keV and a dose of 8.0-10 /cm using this photoresist 10 as a a mask. The boron ion-implanted at a high energy in such a way is transmitted a gate electrode 5 and is distributed widely in the depth direction in a p-type well 2. By the ion-implantation of this boron, the threshold voltage of an n-channel MOSFET Q1 is set at the final target value. Moreover, the impurity concentration at a part, in which this boron is ion-implanted, in the well 2 is augmented. As a result, a spreading of depletion layers to the side of a source region 8 in the p-n junction between a drain region 9 at the time of application of a voltage to a drain of the MOSFET Q1 and the well 2 can be inhibited.

13. 发明专利

JPS6325966A MANUFACTURE OF SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPS6325966A
公开(公告)日：1988-02-03
申请号：JP16793186
申请日：1986-07-18
申请人： HITACHI LTD
发明人： UCHIDA KEN , MEGURO SATOSHI , HIROBE YOSHIMICHI , NOJIRI KAZUO
IPC分类号： H01L21/8246 , H01L27/112
摘要： PURPOSE:To shorten a turnaround time, to prevent decrease in withstanding voltage at the junction in an MISFET and to make it possible to decrease leakage current from the junction, by performing channel doping for writing information in a memory cell after the formation of an interlayer insulating film and before or after the formation of interconnections, and performing annealing with microwave irradiation. CONSTITUTION:Channel doping for writing information in a memory cell comprising a MISFET is performed after the formation of an interlayer insulating film and before or after the formation of interconnections SL and DL. Then, annealing with microwave irradiation is performed. For example, on a semiconductor substrate 1, a field insulating film 2, a gate insulating film 3, word lines WL1 and WL2, n type semiconductor regions 4 and 5, an interlayer insulating film 6, contact holes 6a-6c, source lines SL1 and SL2 and a data line DL are formed. Only the interlayer insulating film 6 at the upper part of the channel part of MISFET Q1, in which information '0' is to be written, is exposed. The other part of the surface is covered with a photoresist film 7, and channel doping is performed. The thereshold voltage value of the MISFET Q1 is set at a high value. Then annealing with microwave irradiation is performed.

14. 发明专利

JPS61241966A SEMICONDUCTOR DEVICE AND MANUFACTURE THEREOF 失效
公开(公告)号：JPS61241966A
公开(公告)日：1986-10-28
申请号：JP8246385
申请日：1985-04-19
申请人： HITACHI LTD
发明人： UCHIDA KEN
IPC分类号： H01L27/092 , H01L21/8238 , H01L21/8246 , H01L21/8247 , H01L27/08 , H01L27/10 , H01L27/112 , H01L29/78 , H01L29/788 , H01L29/792
摘要： PURPOSE:To prevent intrusion of water or contaminants into the vicinity of a gate electrode, by constituting the side wall of a MOS transistor by a nitride film or an oxynitride film, which is a constituent minute material of the gate electrode of an MNOS type transistor. CONSTITUTION:On the surface of an N-type silicon single crystal semiconductor substrate 1, a P-type well 2, a field oxide film 3, a gate oxide film 4 and a polycrystalline silicon film 5 are formed. Phosphorus is introduced, and a gate electrode 7 is formed in an active region 6. Then, phosphorus ions are implanted in a part of the active region 6 through an oxide film 8, and a low- concentration-ion implanted layer 9 is formed. After the oxide film 8 is etched, an SiO2 film 10 is formed. A silicon nitride film 11, a polycrystalline silicon film 12 and a photoresist pattern 13 are formed. With these as masks, the polycrystalline silicon film 12 is etched. After a side wall 16 is formed, arsenic ions are implanted through the SiO2 film 10, and a high-concentration-ion implanted layer is formed. Thus, intrusion of water and contaminants into the vicinity of the gate electrode of the MOS transistor is prevented, and the operation of the MOS transistor is stabilized.

15. 发明专利

JPS6177197A Semiconductor integrated circuit 失效
标题翻译：半导体集成电路
公开(公告)号：JPS6177197A
公开(公告)日：1986-04-19
申请号：JP19662784
申请日：1984-09-21
申请人： Hitachi Ltd
发明人： TANIDA YUJI , HAGIWARA TAKAAKI , MINAMI SHINICHI , NABEYA SHINJI , UCHIDA KEN , FURUNO TAKESHI
IPC分类号： G11C17/18 , G11C16/02 , G11C16/04 , G11C17/00 , H01L27/10
摘要： PURPOSE: To obtain a memory cell requiring no enhancement type reading transistor by applying the gate bias of an MIS type transistor belonging to a non-selection word line in a direction in which the transistor is not conductive.
CONSTITUTION: Gates of memory elements M11, M12, M21, M22 are connected through word lines W1, W2 to a switch 10 and an X decoder 12. Sources of the respective memory elements are connected through bit lines B1, B2 to a switch 14, a drain is connected through a switch 11 controlled by a Y decoder 16 to an input and output circuit 18 during reading, and a well is connected through an S1 to a switch 20. In case of reading the memory elements M11, M12, a word line W1 is set at 3V, a word line W2 at -0V, B1, B2 at 3V, and S1 at -0V. In this manner, without receiving the influence of the memory elements belonging to the non-selecting word lines, the information of the memory element constituted with one element/bit can be read.
COPYRIGHT: (C)1986,JPO&Japio
摘要翻译：目的：通过在晶体管不导电的方向上施加属于非选择字线的MIS型晶体管的栅极偏置来获得不需要增强型读取晶体管的存储单元。构成：存储元件M11，M12，M21，M22的栅极通过字线W1，W2连接到开关10和X解码器12.各存储元件的源通过位线B1，B2连接到开关14，在读取期间，通过由Y解码器16控制的开关11将漏极连接到输入和输出电路18，并且通过S1将开关连接到开关20.在读取存储元件M11，M12的情况下，线W1设定为3V，字线W2为-0V，B1，B2为3V，S1为-0V。以这种方式，在不接收属于非选择字线的存储元件的影响的情况下，可以读取由一个元件/位构成的存储元件的信息。

16. 发明专利

JPS6146058A Semiconductor device and reading method thereof 失效
标题翻译：半导体器件及其读取方法
公开(公告)号：JPS6146058A
公开(公告)日：1986-03-06
申请号：JP16636984
申请日：1984-08-10
申请人： Hitachi Ltd
发明人： UCHIDA KEN , MEGURO SATOSHI , TANIMURA NOBURO , YASUI NORIMASA
IPC分类号： G11C17/00 , G11C16/04 , H01L21/8246 , H01L21/8247 , H01L27/10 , H01L27/112 , H01L29/788 , H01L29/792
CPC分类号： H01L29/792
摘要： PURPOSE:To improve the degree of integration by forming structure in which memory cells in each line arranged along a word line are isolated severally by wells or wells surrounded by insulators at every line. CONSTITUTION:A P type well 21 is shaped onto an insulator 20 while being surrounded by a thick SiO2 film 22. A source and a drain in a MNOST are each formed on both sides of the P well 21 while being brought into contact with the SiO2 film 22, and the source 23 and the drain 24 are shaped by diffusing an N impurity. An extremely thin SiO2 film 25, an Si3N4 film 26 and a gate electrode 27 are formed onto a channel between the source 23 and the drain 24 in order from a lower section. In a memory cell having such constitution, selectivity among word lines can be ensured by back-biassing the well, thus improving the degree of integration as one element/cell.
摘要翻译：目的：通过形成结构来提高积分度，其中沿着字线布置的每行中的存储器单元由在每一行的绝缘体围绕的阱或阱分别隔离。构成：AP型阱21成形为绝缘体20，同时被厚的SiO 2膜22包围。MNOST中的源极和漏极分别形成在P阱21的两侧，同时与SiO 2膜接触 22，源23和漏极24通过扩散N +杂质而成形。从源极23和漏极24之间的沟道上形成极薄的SiO 2膜25，Si 3 N 4膜26和栅电极27。在具有这种结构的存储单元中，可以通过对阱进行反向偏移来确保字线之间的选择性，从而提高作为一个元件/单元的集成度。

17. 发明专利

JPS60152057A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS60152057A
公开(公告)日：1985-08-10
申请号：JP721584
申请日：1984-01-20
申请人： HITACHI MICROCUMPUTER ENG , HITACHI LTD
发明人： SATOU NOBUYUKI , TERASAWA MASAAKI , UCHIDA KEN , NABEYA SHINJI , HAGIWARA TAKAAKI , TANIDA YUUJI
IPC分类号： H01L27/10 , H01L21/8247 , H01L27/06 , H01L29/788 , H01L29/792 , H01L29/866
摘要： PURPOSE:To obtain different reference voltage easily by constituting a semiconductor device as constant-voltage diodes having each different withstanding voltage by utilizing the different junction withstanding voltage of two kinds of diodes having junctions of different shapes manufactured through the same process. CONSTITUTION:With a diode D1, a junction between high concentration (N type and P type) regions can be formed to a beltlike section along a P type region 11 to a plane shape parallel with the surface of a substrate 1 while a junction between the high concentration (N type) region and a low concentration (P type) region can be formed to a section shallower than the junction between the high concentration regions to a plane shape parallel with the surface of the substrate 1. With a diode D2, a junction between high concentration (N type and P type) regions can be shaped to the section surrounding the side surface of a P region 12 while a junction between the high concentration (N type) region and a low concentration (P type) region can be formed on a plane parallel with the surface of the substrate 1 in a section deeper than the junction between high concentration. Breakdown voltage at a time when P-N junctions are reverse-biassed differs in the diodes D1 and D2.

18. 发明专利

JPS57128977A SEMICONDUCTOR MEMORY STORAGE 失效
公开(公告)号：JPS57128977A
公开(公告)日：1982-08-10
申请号：JP1431081
申请日：1981-02-04
申请人： HITACHI LTD
发明人： UCHIDA KEN
IPC分类号： H01L21/8247 , H01L29/788 , H01L29/792
摘要： PURPOSE:To form the memory without forming a source, and to integrate the storage to a high degree by continueing a semiconductor region for writing only at the one side of a gate section and reading informations by the difference of electrostatic capacity at the time of writing and erasing. CONSTITUTION:The EPROM on a P type Si substrate 1 consists of a memory section 4 composed of the gate section 2 and an N type region 3 corresponding to a drain diffused and shaped to the substrate only at the one side of the gate section. A FET6 of the N type region 3 and a poly Si gate 5 is formed adjacently to the memory section 4, and used for reading writing informations. An N type region 7 is shaped as a data line while being opposed to the N type region 3. When writing, a channel under the gate section 2 is at off, and the FET is at on. When reading, all are at on, and the capacity of the memory section changes. Accordingly, the informations can be written and read in excellent reliability without the source section, and a memory cell can be fined.

19. 发明专利

JPS57128976A SEMICONDUCTOR MEMORY STORAGE 失效
公开(公告)号：JPS57128976A
公开(公告)日：1982-08-10
申请号：JP1430881
申请日：1981-02-04
申请人： HITACHI LTD
发明人： UCHIDA KEN , KOMORI KAZUHIRO , SUGIURA JIYUN
IPC分类号： H01L27/112 , H01L21/3205 , H01L21/76 , H01L21/8246 , H01L21/8247 , H01L23/52 , H01L29/788 , H01L29/792
摘要： PURPOSE:To prevent the generation of parasitic channels among a memory section and other regions, and to contract size by forming the same conduction type high-concentration region under wiring to which high voltage is applied according to the same process as high concentration for promoting the writing of the memory section. CONSTITUTION:The memory section 2 on a P type Si substrate 1 consists of N type source and drain diffusion regions 5, 6, a floating gate 10 and a control gate 11 on a thin oxide film 9 between the regions and a P type high- concentration region 8 under a thick oxide film. The control gate 10 extends to the circumferential side on an oxide film 8 of a field section as a word wire of the memory, and is connected to Al wiring 12 to which high voltage for writing is applied. The memory storage functions as a channel stopper a great deal because a high-concentration P type region 21 is shaped under the Al wiring, and electrical conduction between the memory section 2 and surrounding sections 3, 4 is inhibited while the size of a chip can be contracted.

20. 发明专利

JPS53144274A SEMICONDUCTOR DEVICE AND ITS MANUFACTURE 失效
公开(公告)号：JPS53144274A
公开(公告)日：1978-12-15
申请号：JP5868877
申请日：1977-05-23
申请人： HITACHI LTD
发明人： UCHIDA KEN
IPC分类号： H01L29/78 , H01L21/205 , H01L21/8234 , H01L21/86 , H01L27/06 , H01L27/12 , H01L29/417
摘要： PURPOSE:To simplify the circuit constitution by forming MOSFET containing independent V-groove onto the sapphire substrate which is to be an isolation and then drawing out the independent source electrodes from the side surface of MOSFET.

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