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    • 11. 发明专利
    • SEMICONDUCTOR DEVICE
    • JPH04353697A
    • 1992-12-08
    • JP12719791
    • 1991-05-30
    • HITACHI LTD
    • UDAGAWA SATORUYAMAGUCHI YASUNORIKUMADA ATSUSHI
    • G11C11/413G11C11/401
    • PURPOSE:To stabilize operation of a memory board mounting memory integrated circuits and enhance reliability thereof by suppressing power source noise induced on a power source voltage feeding line and balancing amount of superposed noise. CONSTITUTION:A power source voltage feeding terminal VCC for feeding a power source voltage to memory integrated circuits RAM11 to RAM48 and a power source voltage feeding terminal VCCB for feeding a power source voltage to a data output buffer are provided separately and a feeding line SVCA1 or SVCB1 for feeding a power source voltage to the terminal VCC and a feeding line SVCA2 or SVCB2 for feeding a power source voltage to the terminal VCCB are also provided separately. Moreover, the memory integrated circuits are divided into groups of a first and a second integrated circuit groups and connection between the power source voltage feeding lines SVCA1 and SVCA2 and the feeding lines SVCB1 and SVCB2 is crossed between these integrated circuit groups. Moreover, data output buffer is formed as a open drain type and an output terminal thereof is coupled with power source voltage for termination of the memory board MB1.
    • 13. 发明专利
    • SEMICONDUCTOR MEMORY DEVICE
    • JPH01166398A
    • 1989-06-30
    • JP32390887
    • 1987-12-23
    • HITACHI LTD
    • KUMADA ATSUSHIKAJITANI KAZUHIKO
    • G11C29/00G11C11/34G11C11/401G11C11/413G11C29/42
    • PURPOSE:To contrive a high speed memory access by disposing address decoders for selective driving of word line in each memory mat and arranging them uniformly to either address input buffer or a data input/output circuit side. CONSTITUTION:Address decoders 21-24 for forming a word line selecting driving signal to select a memory cell, which is included in memory mats 11-14, are arranged in each memory mat 11-14 uniformly to either an address input buffer 16 side or a data input and output circuit 15 side. Accordingly, the selecting driving direction of the memory cell by the address decoders 21-24 is caused to be constant regardless of the position of the memory cell, and the increase and decrease of a load, with which the address decoders 21-24 and the data input/output circuit 15 are respectively driven, is canceled. Then, even when the position of the memory cell to be an access subject is changed, the fluctuation of the total load, with which the both circuits 16 and 15 are driven, is suppressed. Thus, the high speed memory access can be attained.