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11. 发明专利

DE3821636A1 未知
公开(公告)号：DE3821636A1
公开(公告)日：1989-01-05
申请号：DE3821636
申请日：1988-06-27
申请人： HITACHI LTD
发明人： BEKKI YOSHINORI , WADA HIROYUKI , HIRAI MASATO
IPC分类号： H04L12/437 , H04B3/00 , H04L25/02
摘要： In a ring network system including two transmission lines transmitting a signal in directions opposite to each other, and a plurality of line concentrators connected in the form of a loop by the two transmission lines and each accommodating a plurality of terminal stations connected to one of the two transmission lines, a signal detecting unit and a terminating circuit are disposed in each of the line concentrators on the signal output side of each of the transmission lines so as to be connectable to and disconnectable from the transmission lines, so that, when the signal detecting unit in one of the line concentrators is connected to the associated transmission line, the transmission line is disconnected in the line concentrator, and the terminating circuit is connected to the downstream segment of the disconnected transmission line.

12. 发明专利

JP2000101571A SYNCHRONIZATION CONTROL METHOD FOR TERMINAL ADAPTER 失效
公开(公告)号：JP2000101571A
公开(公告)日：2000-04-07
申请号：JP26595798
申请日：1998-09-21
申请人： HITACHI LTD
发明人： SASAHARA KOJI , HIRAI MASATO
IPC分类号： H04L7/00 , H04L12/02 , H04M11/00
摘要： PROBLEM TO BE SOLVED: To normally perform communication in interconnection of terminal adapters between different makes by providing a buffer in the terminal adapter and adjusting a timing between control signals and data signals sent out to an ISDN line and received from the ISDN line matching the opposing terminal adapter. SOLUTION: At the time of transmitting and receiving the control signals and data signals of an ITU-T recommendation V.24 standard, synchronization between the control signals and the data signals is varied. A transmission data buffer 8 and a control signal buffer 11 respectively delay transmission data and the control signals from a V.24 DTE interface 7 corresponding to a delay from a control part 15 and then, send them out to an ISDN frame generation part 9. A reception data buffer 12 and the control signal buffer 14 respectively delay the transmission data and the control signals delivered from an ISDN frame development part 13 corresponding to the delay value from the control part 15 and then, send them out to the V.24 DTE interface 7.

13. 发明专利

JPS63190225A LOAD DRIVING CIRCUIT 失效
公开(公告)号：JPS63190225A
公开(公告)日：1988-08-05
申请号：JP1837787
申请日：1987-01-30
申请人： HITACHI LTD
发明人： HIRAI MASATO , YOSHINO RYOZO
IPC分类号： H01H47/00 , H04L12/42

14. 发明专利

JPH0997232A SIGNAL TRANSMITTING METHOD AND EXECUTING DEVICE FOR THE SAME 失效
公开(公告)号：JPH0997232A
公开(公告)日：1997-04-08
申请号：JP25222795
申请日：1995-09-29
申请人： HITACHI LTD
发明人： TAMURA YASUAKI , SUZUKI YASUSHI , HIRAI MASATO
IPC分类号： G06F13/40 , H04B15/00
摘要： PROBLEM TO BE SOLVED: To suppress electromagnetic radiation noise and electromagnetic induction noise and simultaneously to transmit much more signals without changing the number of signal transmission lines. SOLUTION: A high frequency signal outputted from a high frequency signal output device 110 is transmitted to a high frequency signal input device 210 by a first signal transmission line 311, the return current of the high frequency signal from the high frequency signal input device 210 is transmitted through an input side capacitor C21 connected to the high frequency signal input device 210 and an output side capacitor C11 connected to the high frequency signal output device 110, to the high frequency signal output device 110 by a second signal transmission line 312, and a DC signal or a low frequency signal outputted by the signal output device 110 is transmitted to the signal input device 210 by the second signal transmission line 312 without interposing the output side capacitor C11 and the input side capacitor C21.

15. 发明专利

JPH07303115A CHANGEOVER SYSTEM FOR TRANSMISSION LINE 失效
公开(公告)号：JPH07303115A
公开(公告)日：1995-11-14
申请号：JP9504294
申请日：1994-05-09
申请人： HITACHI LTD , HITACHI COMPUTER ELECTRONIC
发明人： NAKAUCHI TOSHIHIKO , HIRAI MASATO , SHIGUMA TAKASHI , KAMIYA AKIRA
IPC分类号： H04L12/437
摘要： PURPOSE:To provide an inexpensive transmission line changeover system of a constitution capable of using a connector not having an external power terminal exclusive for a switch circuit. CONSTITUTION:A power application/non-application state in a connector 12 is discriminated via control terminals 124, 125 of the connector 12 and when power of the connector 12 is applied normally, switches 1-4 are controlled to be closed, and a single ring LAN including a transmission line changeover device 11 is built up. When the power is not applied to the connector 12, the switches 1, 4 and 2, 3 are controlled to be closed with each other, then the connector 12 is disconnected from the ring type LAN and the transmission line changeover device 11 connects the connectors 13, 14.

16. 发明专利

JPS6236412B2 失效
公开(公告)号：JPS6236412B2
公开(公告)日：1987-08-06
申请号：JP13971481
申请日：1981-09-07
申请人： HITACHI LTD
发明人： FURUKAWA HIROSHI , KUSAMA TAKEO , HIRAI MASATO , AKYAMA FUMIO
IPC分类号： H04B3/46 , H04L1/14 , H04L1/24 , H04L29/14

17. 发明专利

JPS61216524A PHASE LOCK DETECTING CIRCUIT 失效
公开(公告)号：JPS61216524A
公开(公告)日：1986-09-26
申请号：JP5584185
申请日：1985-03-22
申请人： HITACHI LTD
发明人： HIRAI MASATO , YOSHINO RYOZO
IPC分类号： H03L7/113 , H03L7/089 , H03L7/095
摘要： PURPOSE:To set a phase lock detection range and also to set an adaptive frequency range without any adjustment only by varying the setting of a delay time by solving problems of a conventional analog system by employing a digital system. CONSTITUTION:A frequency phase comparator 1 outputs signals D and U according to the phase relation between an input signal and the output of a VCO. Those outputs D and U are ORed and a signal 10 which is delayed by a time (t) is sampled by flip-flops 7 and 8 with the leading edge of the VCO output. When the phase difference between the input signal and VCO output is smaller than the delay time (t), the signal 10 is '0' at a sampling point of time, so signals 11 and 12 are both '0' and the output of an AND circuit 9 is '1', so that is detected as a phase lock state. When the phase difference is larger than the delay time (t), the input signal is sampled to obtain '0', but the output side of the VCO is sampled to detect '1' as the signal 10, which is not detected as the phase lock state. Namely, the range wherein the phase lock state is detected is determined only by the delay time (t).

18. 发明专利

JPS6091748A DIGITAL SIGNAL DEMODULATING SYSTEM 失效
公开(公告)号：JPS6091748A
公开(公告)日：1985-05-23
申请号：JP20016983
申请日：1983-10-26
申请人： HITACHI LTD
发明人： OOE TAKAO , MIYAJIMA SEITAROU , KUSAMA TAKEO , HIRAI MASATO
IPC分类号： H04L27/156 , H04L27/14
摘要： PURPOSE:To realize demodulating operation by a digital circuit by allowing an up-down counter to be counted in high-order or low-order direction with a pulse signal whose duty ratio is varied in response to a frequency of a frequency modulation signal. CONSTITUTION:An input signal 101 is inputted to an exclusive OR circuit 302, where the signal is exclusively ORed with an output of a phase comparator circuit 301 and the result is converted into a signal 317 having a duty ratio depending on the ratio of the upper limit frequency f5 to the lower limit frequency f6 of the frequency band possible for demodulation. A counter control circuit A303 outputs a clock signal as a signal 318 or 319 by using the signal 317 to increment the up-dwon counter A304 by the signal 318 and decrement it by the signal 319. When the counter A304 reaches a maximum value, a detection circuit 307 detects 1s of the demodulated data and when the A304 reaches a minimum value, the circuit 307 detects Os, and its state is held in a flip-flop 309.

19. 发明专利

JPH1165943A DATA TRANSFER DEVICE 失效
公开(公告)号：JPH1165943A
公开(公告)日：1999-03-09
申请号：JP22460797
申请日：1997-08-21
申请人： HITACHI LTD
发明人： ADACHI SHUICHI , HIRAI MASATO
IPC分类号： G06F12/16 , G06F11/10
摘要： PROBLEM TO BE SOLVED: To enable the detection of errors even at the time of write, to detect whether an error check sequence is coincident with that of writing time or not to detect the error even at the time of read, to reduce the load of an application software when there are many data to be written in a memory, and to shorten processing time. SOLUTION: At the time of data write to a memory 9, transmission data are formatted into frame and by having the error check sequence, the error is detected at the time of write. At the time of read, the error is detected as well corresponding to whether the error check sequence is coincident with that of writing time or not. Then, the result is reported. Besides, the result of the error check performed by a read part is reported by the frame so that the burden of the application software can be reduced when there are many data to be written in the memory 9.

20. 发明专利

JPH06102964A INFORMATION PROCESSING SYSTEM 失效
公开(公告)号：JPH06102964A
公开(公告)日：1994-04-15
申请号：JP25017392
申请日：1992-09-18
申请人： HITACHI LTD
发明人： NAKAUCHI TOSHIHIKO , HIRAI MASATO
IPC分类号： G06F1/12 , G06F1/04 , G06F1/10 , H03K5/1252 , H03K5/19 , H03L7/08 , H03L7/14 , H04L7/00
摘要： PURPOSE:To prevent a fault in LAN and to shorten system response time at regular time by phase-compensating a digital network clock and a system clock synchronizing whole nodes in LAN when the phase of the digital network clock fluctuates. CONSTITUTION:A system where a phase locked loop (PLL) 31 is synchronized with an external clock 26 and it is set to be a system clock source is provided with a phase compensation circuit 40 compensating the phase of a clock 44 inputted to the phase locked loop 31 when the phase of the external clock 26 fluctuates. Since the fault caused by the frequency fluctuation of PLL can be avoided without using an elastic buffer, data delay which occurs by the passage of data through the elastic buffer is improved, and system response time in LAN can be shortened.

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