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    • 11. 发明授权
    • Methods and systems for on-the-fly chip verification
    • 用于实时芯片验证的方法和系统
    • US07996801B2
    • 2011-08-09
    • US12188749
    • 2008-08-08
    • Kelvin Wong
    • Kelvin Wong
    • G06F17/50
    • G06F17/5022
    • Methods and systems for on-the-fly chip verification method for tracking non-contiguous events. A method includes comparing a first search marker associated with a first check vector to a search key associated with an output vector of a design under test (DUT). The method also includes performing either: verifying a validity of the output vector when the first search marker equals the search key, or comparing a second search marker associated with a second check vector to the search key when the first search marker does not equal the search key.
    • 用于跟踪非连续事件的用于实时芯片验证方法的方法和系统。 一种方法包括将与第一校验向量相关联的第一搜索标记与与待测设计(DUT)的输出向量相关联的搜索关键字进行比较。 该方法还包括执行以下操作之一:当第一搜索标记等于搜索关键字时验证输出向量的有效性,或者当第一搜索标记不等于搜索时,将与第二检查向量相关联的第二搜索标记与搜索关键字进行比较 键。
    • 16. 发明申请
    • DEVICE AND METHOD FOR DETECTION AND PROCESSING OF STALLED DATA REQUEST
    • 用于检测和处理数据请求的设备和方法
    • US20080114909A1
    • 2008-05-15
    • US11869303
    • 2007-10-09
    • Kelvin Wong
    • Kelvin Wong
    • G06F13/14
    • G06F13/423
    • A device comprises a communication module connected to an external data link The communication module is arranged to receive a plurality of read and write requests from the data link, and a logic module connected to the communication module. The communication module is arranged to transmit at least some of the plurality of read and write requests to the logic module, the logic module being arranged to process the read and write requests in turn, to detect when the processing of a request is stalled, to execute a decision logic in response to the detection of a stalled request, and to process either the same request or a different request according to the output of the decision logic.
    • 一种设备包括连接到外部数据链路的通信模块。通信模块被布置为从数据链路接收多个读取和写入请求,以及连接到通信模块的逻辑模块。 通信模块被布置为将多个读取和写入请求中的至少一些传送到逻辑模块,逻辑模块被布置成依次处理读取和写入请求,以检测何时处理请求被停止,到 响应于停止的请求的检测执行决策逻辑,并根据决策逻辑的输出处理相同的请求或不同的请求。
    • 17. 发明申请
    • Method, Apparatus and Software for Managing Processing For a Plurality of Processors
    • 用于管理多个处理器的处理的方法,设备和软件
    • US20080052714A1
    • 2008-02-28
    • US11776011
    • 2007-07-11
    • Kelvin Wong
    • Kelvin Wong
    • G06F9/46
    • G06F9/5027G06F9/5038G06F2209/5013
    • A method, apparatus or software for managing processing for a plurality of processors in a multi processor device is disclosed in which a plurality of jobs are assigned as pending jobs for processing by the processors. Each pending job and its associated task are identified. Processing is initiated by one or more of the processors of a respective pending job. In response to one of the processors completing the processing of a respective pending job, a further one of the pending jobs is selected for processing. The selection of a further pending job occurs if no other job currently being processed by any of the processors is associated with the same task as the further pending job.
    • 公开了一种用于管理多处理器设备中的多个处理器的处理的方法,装置或软件,其中将多个作业分配为待处理作业以供处理器处理。 识别每个挂起的作业及其相关任务。 处理由相应未决作业的一个或多个处理器发起。 响应于一个处理器完成相应待处理作业的处理,另外一个待处理作业被选择用于处理。 如果任何处理器当前正在处理的任何其他作业与与另外待处理的作业相同的任务相关联,则进行另一待处理作业的选择。
    • 18. 发明授权
    • On-chip diagnostic system, integrated circuit and method
    • 片上诊断系统,集成电路及方法
    • US06662347B2
    • 2003-12-09
    • US10160300
    • 2002-05-30
    • Kelvin Wong
    • Kelvin Wong
    • G06F1750
    • G01R31/31724G01R31/31722G01R31/31723
    • An on-chip diagnostic system is used with an internal bus (10) of an integrated circuit. The bus has a number of byte-wide data lanes. A register (20) of the system is arranged to store a byte pattern. A series of comparators (30) receive byte signals from each of the byte lanes of the internal bus (10) and compare these with the byte pattern from the register (20). Outputs from the comparators are provided to a decoder (40) which provides, in the case of one of the byte lanes containing the same byte as the data pattern, an output signal (50) identifying that data lane, to a diagnostic port of the integrated circuit. In this way more information may be provided at the diagnostic port at any one time. An entire internal bus may be monitored in a single test run whilst at the same time making more of the diagnostic port available for tracing control signals, thus reducing the amount of time required to determine the cause of chip design problems.
    • 片上诊断系统与集成电路的内部总线(10)一起使用。 总线有一些字节宽的数据通道。 系统的寄存器(20)被设置为存储字节模式。 一系列比较器(30)从内部总线(10)的每个字节通道接收字节信号,并将其与来自寄存器(20)的字节模式进行比较。 来自比较器的输出被提供给解码器(40),其在包含与数据模式相同的字节的字节通道中的一个的情况下,将识别该数据通道的输出信号(50)提供给 集成电路。 这样就可以在诊断端口上随时提供更多的信息。 可以在单个测试运行中监视整个内部总线,同时使更多的诊断端口可用于跟踪控制信号,从而减少确定芯片设计问题原因所需的时间。
    • 19. 发明授权
    • Integrated circuit and method of testing the integrity of electrical connection of the circuit to external equipment
    • 集成电路和测试电路与外部设备电气连接完整性的方法
    • US08330484B2
    • 2012-12-11
    • US12688463
    • 2010-01-15
    • Kelvin Wong
    • Kelvin Wong
    • G01R31/26G01R31/3187
    • G01R31/31905G01R31/31704G01R35/005
    • An integrated circuit and method of testing the integrity of the electrical connection of the integrated circuit to external equipment are provided. The integrated circuit comprises an output port including output contacts for coupling the integrated circuit to external equipment, via external connectors. The output port receives internal operational signals and routes the operational signals to the output contacts for connection of the operational signals to external equipment. A connection test signal store is dynamically loadable with test signals. Signals sent to the output port can be switched between the test signals and operational signals. External equipment monitors the integrity of an electrical connection between the output contacts and the external connectors by detecting expected transitions in the test signals.
    • 提供了一种集成电路和测试集成电路与外部设备的电连接完整性的方法。 集成电路包括输出端口,其包括用于经由外部连接器将集成电路耦合到外部设备的输出触点。 输出端口接收内部操作信号,并将操作信号路由到输出触点,以将操作信号连接到外部设备。 连接测试信号存储器可通过测试信号进行动态加载。 发送到输出端口的信号可以在测试信号和操作信号之间切换。 外部设备通过检测测试信号中的预期转换来监视输出触点和外部连接器之间的电气连接的完整性。