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    • 12. 发明申请
    • Garbage collection barrier with direct user mode traps
    • 垃圾收集障碍与直接用户模式陷阱
    • US20100180090A1
    • 2010-07-15
    • US12592579
    • 2009-11-25
    • Cliff N. Click, JR.Gil TeneMichael A. Wolf
    • Cliff N. Click, JR.Gil TeneMichael A. Wolf
    • G06F12/00
    • G06F12/0269
    • A computer system includes a processor; and a memory coupled to the processor, configured to provide the processor with a plurality of instructions including a set of garbage collection instructions configured to perform one or more garbage collection barrier operations and a subsequent instruction that immediately follows the garbage collection instruction; wherein the processor is configured to execute the set of garbage collection instructions, including by: evaluating a memory reference to determine a condition associated with the set of garbage collection instructions; and in the event that the condition is met, while maintaining the same privilege level, saving information that is based at least in part on the current value of a program counter, and setting the program counter to correspond to a target location that is other than the location of the subsequent instruction.
    • 计算机系统包括处理器; 以及耦合到所述处理器的存储器,被配置为向所述处理器提供多个指令,所述指令包括被配置为执行一个或多个垃圾收集屏障操作的一组垃圾收集指令以及紧随所述垃圾收集指令的后续指令; 其中所述处理器被配置为执行所述一组垃圾收集指令,包括:评估存储器引用以确定与所述一组垃圾收集指令相关联的条件; 并且在条件满足的情况下,在保持相同特权级别的情况下,至少部分地基于程序计数器的当前值保存信息,并且将程序计数器设置为对应于除 后续指令的位置。
    • 13. 发明授权
    • Processor instruction used to perform a matrix test to generate a memory-related trap
    • 处理器指令用于执行矩阵测试以生成与存储器相关的陷阱
    • US08108628B2
    • 2012-01-31
    • US12658669
    • 2010-02-12
    • Jack H. ChoquetteGil TeneMichael A. Wolf
    • Jack H. ChoquetteGil TeneMichael A. Wolf
    • G06F13/00
    • G06F12/0253G06F9/3004G06F9/3861G06F11/2236
    • Instruction execution includes fetching an instruction that comprises a first set of one or more bits identifying the instruction, and a second set of one or more bits associated with a first address value. It further includes executing the instruction to determine whether to perform a trap, wherein executing the instruction includes selecting from a plurality of tests at least one test for determining whether to perform a trap and carrying out the at least one test. The second set of one or more bits is used in the determination of whether to perform the trap; and the plurality of tests includes a matrix test that determines whether a data value being stored as pointed to by the first address value is escaping from one of a plurality of managed memory types to another one of the plurality of managed memory types and generates a trap in the event that the data value is determined to be escaping from one of the plurality of managed memory types to another one of the plurality of managed memory types, wherein the matrix test is based on a matrix associated with garbage collection and a matrix entry located using at least some of the first set of one or more bits and at least some of the second set of one or more bits.
    • 指令执行包括获取包括识别指令的一个或多个比特的第一组的指令,以及与第一地址值相关联的一个或多个比特的第二组。 它还包括执行指令以确定是否执行陷阱,其中执行指令包括从多个测试中选择至少一个用于确定是否执行陷阱并进行至少一个测试的测试。 在确定是否执行陷阱时使用第二组一个或多个比特; 并且所述多个测试包括矩阵测试,所述矩阵测试确定由所述第一地址值指示的存储的数据值是否从多个管理存储器类型中的一个转移到所述多个管理存储器类型中的另一个,并产生陷阱 在数据值被确定为从多个托管存储器类型之一转移到多个托管存储器类型中的另一个的情况下,其中矩阵测试基于与垃圾收集相关联的矩阵和位于 使用一个或多个比特的第一组中的至少一些以及一个或多个比特的第二组中的至少一些。
    • 15. 发明申请
    • Processor instruction used to determine whether to perform a memory-related trap
    • 处理器指令用于确定是否执行内存相关的陷阱
    • US20100153689A1
    • 2010-06-17
    • US12658669
    • 2010-02-12
    • Jack ChoquetteGil TeneMichael A. Wolf
    • Jack ChoquetteGil TeneMichael A. Wolf
    • G06F9/38G06F12/10
    • G06F12/0253G06F9/3004G06F9/3861G06F11/2236
    • Instruction execution includes fetching an instruction that comprises a first set of one or more bits identifying the instruction, and a second set of one or more bits associated with a first address value. It further includes executing the instruction to determine whether to perform a trap, wherein executing the instruction includes selecting from a plurality of tests at least one test for determining whether to perform a trap and carrying out the at least one test. The second set of one or more bits is used in the determination of whether to perform the trap; and the plurality of tests includes a matrix test that determines whether a data value being stored as pointed to by the first address value is escaping from one of a plurality of managed memory types to another one of the plurality of managed memory types and generates a trap in the event that the data value is determined to be escaping from one of the plurality of managed memory types to another one of the plurality of managed memory types, wherein the matrix test is based on a matrix associated with garbage collection and a matrix entry located using at least some of the first set of one or more bits and at least some of the second set of one or more bits.
    • 指令执行包括获取包括识别指令的一个或多个比特的第一组的指令,以及与第一地址值相关联的一个或多个比特的第二组。 它还包括执行指令以确定是否执行陷阱,其中执行指令包括从多个测试中选择至少一个用于确定是否执行陷阱并进行至少一个测试的测试。 在确定是否执行陷阱时使用第二组一个或多个比特; 并且所述多个测试包括矩阵测试,所述矩阵测试确定由所述第一地址值指示的存储的数据值是否从多个管理存储器类型中的一个转移到所述多个管理存储器类型中的另一个,并产生陷阱 在数据值被确定为从多个托管存储器类型之一转移到多个托管存储器类型中的另一个的情况下,其中矩阵测试基于与垃圾收集相关联的矩阵和位于 使用一个或多个比特的第一组中的至少一些以及一个或多个比特的第二组中的至少一些。