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11. 发明授权

US4533876A Differential operational amplifier with common mode feedback 失效
标题翻译：具有共模反馈的差分运算放大器
公开(公告)号：US4533876A
公开(公告)日：1985-08-06
申请号：US543194
申请日：1983-10-18
申请人： Yusuf Haque , Erwin Ofner
发明人： Yusuf Haque , Erwin Ofner
IPC分类号： H03F3/345 , H03F1/08 , H03F3/34 , H03F3/45 , H03F3/16
CPC分类号： H03F3/45654 , H03F1/086 , H03F3/45192 , H03F3/45659 , H03F2200/153 , H03F2203/45424 , H03F2203/45651
摘要： A differential operational amplifier is provided with a feedback loop which continuously adjusts the common mode voltage level of the amplifier so that it lies in the center of the dynamic range of the amplifier. The feedback loop measures the instantaneous common mode voltage level and compares it with a reference voltage which is set to reflect the desired common mode voltage. An error signal is generated and fed back into the amplifier to adjust the instantaneous common mode voltage level towards the reference level. Frequency compensation is also provided to overcome the phase shift introduced by the use of RC networks.
摘要翻译：差分运算放大器设置有反馈回路，其连续地调节放大器的共模电压电平，使其位于放大器的动态范围的中心。反馈回路测量瞬时共模电压电平，并将其与设置为反映所需共模电压的参考电压进行比较。产生误差信号并反馈到放大器，以将瞬时共模电压电平调整到参考电平。还提供频率补偿以克服使用RC网络引入的相移。

12. 发明授权

US08525556B2 Time-interleaved sample-and-hold 失效
标题翻译：时间交错采样和保持
公开(公告)号：US08525556B2
公开(公告)日：2013-09-03
申请号：US13015981
申请日：2011-01-28
申请人： Ramesh Kumar Singh , Yusuf Haque , Donald E. Lewis
发明人： Ramesh Kumar Singh , Yusuf Haque , Donald E. Lewis
IPC分类号： G11C27/02
CPC分类号： G11C27/02 , G11C7/1042 , G11C27/024
摘要： A time-interleaved sample-and-hold system includes a first sample-and-hold circuit and a second sample-and-hold circuit. The first sample-and-hold circuit and the second sample-and-hold circuit share a common sampling switch. A method of remediating a timing offset between a first sample-and-hold circuit and a second sample-and-hold circuit in a time-interleaved sample-and-hold system includes switching at least one shunt capacitor disposed between two logic gates in a timing circuit to adjust a delay between a timing signal for a common sampling switch electrically coupled to the first and second sample-and-hold circuits and a timing signal for at least one of the sample-and-hold circuits.
摘要翻译：时间交替采样和保持系统包括第一采样保持电路和第二采样保持电路。第一采样保持电路和第二采样保持电路共用一个公共采样开关。在时间交织的采样和保持系统中修复第一采样保持电路和第二采样保持电路之间的定时偏移的方法包括：切换至少一个分流电容器，该并联电容器设置在两个逻辑门之间定时电路，用于调整电耦合到第一和第二采样保持电路的公共采样开关的定时信号与至少一个采样和保持电路的定时信号之间的延迟。

13. 发明申请

US20130141261A1 TIME-INTERLEAVED ANALOG-TO-DIGITAL CONVERTER BANDWIDTH MATCHING 失效
标题翻译：时间间隔模数转换器带宽匹配
公开(公告)号：US20130141261A1
公开(公告)日：2013-06-06
申请号：US13309194
申请日：2011-12-01
申请人： Tracy Johancsik , Ryan James Kier , Yusuf Haque
发明人： Tracy Johancsik , Ryan James Kier , Yusuf Haque
IPC分类号： H03M1/06 , H03M1/10 , H03M1/12
CPC分类号： H03M1/54 , H03M1/1061 , H03M1/1215 , H03M1/1245
摘要： A time-interleaved Analog-to-Digital Converter (ADC) includes a set of sub-ADC circuits. Each sub-ADC circuit comprises a sample-and-hold circuit. Each sample-and-hold circuit includes a bootstrap circuit for maintaining a constant voltage level between an input terminal of a switch and a gate terminal of the switch, the switch for switching between a sample mode and a hold mode. Each sample and hold circuit also includes a capacitor bank associated with the bootstrap circuit such that a setting of the capacitor bank affects an ON state intrinsic resistance of the switch by affecting the voltage level.
摘要翻译：时间交织的模数转换器（ADC）包括一组子ADC电路。每个子ADC电路包括采样和保持电路。每个采样和保持电路包括一个自举电路，用于在开关的输入端和开关的栅极端之间保持恒定的电压电平，用于在采样模式和保持模式之间切换的开关。每个采样和保持电路还包括与自举电路相关联的电容器组，使得电容器组的设置通过影响电压电平来影响开关的导通状态固有电阻。

14. 发明申请

US20120194223A1 TIME-INTERLEAVED SAMPLE-AND-HOLD 失效
标题翻译：时间间隔采样和保持
公开(公告)号：US20120194223A1
公开(公告)日：2012-08-02
申请号：US13015981
申请日：2011-01-28
申请人： Ramesh Kumar Singh , Yusuf Haque , Donald E. Lewis
发明人： Ramesh Kumar Singh , Yusuf Haque , Donald E. Lewis
IPC分类号： G11C27/02
CPC分类号： G11C27/02 , G11C7/1042 , G11C27/024
摘要： A time-interleaved sample-and-hold system includes a first sample-and-hold circuit and a second sample-and-hold circuit. The first sample-and-hold circuit and the second sample-and-hold circuit share a common sampling switch. A method of remediating a timing offset between a first sample-and-hold circuit and a second sample-and-hold circuit in a time-interleaved sample-and-hold system includes switching at least one shunt capacitor disposed between two logic gates in a timing circuit to adjust a delay between a timing signal for a common sampling switch electrically coupled to the first and second sample-and-hold circuits and a timing signal for at least one of the sample-and-hold circuits.
摘要翻译：时间交替采样和保持系统包括第一采样保持电路和第二采样保持电路。第一采样保持电路和第二采样保持电路共用一个公共采样开关。在时间交织的采样和保持系统中修复第一采样保持电路和第二采样保持电路之间的定时偏移的方法包括：切换至少一个分流电容器，该并联电容器设置在两个逻辑门之间定时电路，用于调整电耦合到第一和第二采样保持电路的公共采样开关的定时信号与至少一个采样和保持电路的定时信号之间的延迟。

15. 发明申请

US20100321227A1 Current Mode Analog-to-Digital Converter 有权
标题翻译：电流模式模数转换器
公开(公告)号：US20100321227A1
公开(公告)日：2010-12-23
申请号：US12870146
申请日：2010-08-27
申请人： Rex K. Hales , Marcellus C. Harper , Tracy Johancsik , Yusuf Haque
发明人： Rex K. Hales , Marcellus C. Harper , Tracy Johancsik , Yusuf Haque
IPC分类号： H03M1/34
CPC分类号： G01R19/257 , H03M1/0607 , H03M1/0682 , H03M1/146 , H03M1/366
摘要： A current-mode analog-to-digital converter includes: a current input node; a current-mode sample and hold circuit configured to output a steady source of electrical current having an analog value proportional to a sampled analog value of an electrical current at the current input node; and at least one current comparator that compares the electrical current output by the current-mode sample and hold circuit to at least one reference current to produce a digital representation of the sampled analog value of the electrical current at the current input node.
摘要翻译：电流模式模数转换器包括：电流输入节点; 电流模式采样和保持电路，被配置为输出具有与当前输入节点处的电流的采样模拟值成比例的模拟值的稳定电流源; 以及至少一个电流比较器，其将由电流模式采样和保持电路输出的电流与至少一个参考电流进行比较，以产生在当前输入节点处的电流的采样模拟值的数字表示。

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