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11. 发明授权

US06259309B1 Method and apparatus for the replacement of non-operational metal lines in DRAMS 失效
标题翻译：用于替代DRAMS中的非操作金属线的方法和装置
公开(公告)号：US06259309B1
公开(公告)日：2001-07-10
申请号：US09305434
申请日：1999-05-05
申请人： Gerhard Mueller , Toshiaki Kirihata
发明人： Gerhard Mueller , Toshiaki Kirihata
IPC分类号： G05F1116
CPC分类号： G11C29/80 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor integrated circuit device including a redundant metal line for replacing a non-operational metal line for connecting to a circuit block. The invention further includes a method for decoupling a defective or otherwise non-operational conductive data line from a circuit block to which it is connected, and replacing the defective conductive data line with a redundant line by coupling it to the same circuit block. A spare conductive block is not needed. The redundant metal lines may be used in multiple levels of hierarchy within an integrated circuit device.
摘要翻译：一种半导体集成电路器件，包括用于替换用于连接到电路块的非操作金属线的冗余金属线。本发明还包括一种用于将有缺陷或其它不可操作的导电数据线与其所连接的电路块分离的方法，以及通过将其连接到相同的电路块来用冗余线代替有缺陷的导电数据线。不需要备用导电块。冗余金属线可以在集成电路器件内的多个层级中使用。

12. 发明授权

US5917744A Semiconductor memory having hierarchical bit line architecture with interleaved master bitlines 失效
标题翻译：半导体存储器具有分层位线架构和交错主位线
公开(公告)号：US5917744A
公开(公告)日：1999-06-29
申请号：US993537
申请日：1997-12-18
申请人： Toshiaki Kirihata , Gerhard Mueller
发明人： Toshiaki Kirihata , Gerhard Mueller
IPC分类号： G11C11/401 , G11C7/18 , G11C11/4097 , H01L21/8242 , H01L27/108 , G11C5/06
CPC分类号： G11C11/4097 , G11C7/18
摘要： Disclosed is a semiconductor memory employing a hierarchical bitline architecture which allows for a widened master bitline pitch as well as low bitline capacitance. In an exemplary embodiment, the memory (30) includes a plurality of memory cells (MC) arranged in rows and columns for storing data. Each column has at least one sense amplifier (SA.sub.i), at least one pair of master bitlines (MBL.sub.i, MBL.sub.i ) operatively coupled to the sense amplifier, and at least two pairs of local bitlines (LBL.sub.1i, LBL.sub.1i , LBL.sub.2i, LBL.sub.2i ), coupled to memory cells and selectively coupled to the sense amplifier. At least one of the local bitline pairs is selectively coupled to the sense amplifier via the master bitline pair. Each master bitline pair has a length shorter than a column length, and the master bitlines are arranged in an interleaved configuration. The pitch of at least a portion of at least some of the master bitlines is greater than the local bitline pitch. The master bitlines may be arranged in either folded or open configurations. The master bitline pitch may be about twice the local bitline pitch.
摘要翻译：公开了采用分级位线架构的半导体存储器，其允许加宽的主位线间距以及低位线电容。在示例性实施例中，存储器（30）包括以行和列排列以存储数据的多个存储单元（MC）。每列具有至少一个读出放大器（SAi），可操作地耦合到读出放大器的至少一对主位线（MBLi，+ E，ovs MBLi + EE）和至少两对本地位线（LBL1i，+ E ，ovs LBL1i + EE，LBL2i，+ E，ovs LBL2i + EE），耦合到存储器单元并选择性地耦合到读出放大器。本地位线对中的至少一个经由主位线对选择性地耦合到读出放大器。每个主位线对具有比列长度短的长度，并且主位线被布置成交错配置。至少一些主位线的至少一部分的间距大于局部位线间距。主位线可以以折叠或开放的配置布置。主位线间距可以是本地位线间距的两倍。

13. 发明申请

US20050144373A1 System and method for variable array architecture for memories 有权
标题翻译：用于存储器的可变阵列架构的系统和方法
公开(公告)号：US20050144373A1
公开(公告)日：2005-06-30
申请号：US10748333
申请日：2003-12-31
申请人： Toshiaki Kirihata , Gerhard Mueller , Wing Luk
发明人： Toshiaki Kirihata , Gerhard Mueller , Wing Luk
IPC分类号： G06F12/00 , G06F13/16
CPC分类号： G06F13/1694 , Y02D10/14
摘要： A memory system that employs simultaneous activation of at least two dissimilar memory arrays, during a data manipulation, such as read or write operations is disclosed. An exemplary embodiment includes a memory system containing a plurality of arrays, each in communication with a common controller, wherein the arrays are activated by different supply voltage (Vdd). When a processor sends a command to retrieve or write data to the memory system, two or more arrays are addressed to supply the required data. By proper partitioning of the data between dissimilar arrays, the efficiency of data reading is improved.
摘要翻译：公开了一种在诸如读取或写入操作的数据操作期间同时激活至少两个不同的存储器阵列的存储器系统。示例性实施例包括包含多个阵列的存储器系统，每个阵列与公共控制器通信，其中阵列由不同的电源电压（Vdd）激活。当处理器发送命令以检索或写入数据到存储器系统时，寻址两个或更多个阵列以提供所需的数据。通过在不同阵列之间适当分割数据，数据读取的效率得到提高。

14. 发明授权

US06799290B1 Data path calibration and testing mode using a data bus for semiconductor memories 失效
标题翻译：使用半导体存储器的数据总线的数据路径校准和测试模式
公开(公告)号：US06799290B1
公开(公告)日：2004-09-28
申请号：US09512756
申请日：2000-02-25
申请人： Toshiaki Kirihata , Gerhard Mueller , David Russell Hanson
发明人： Toshiaki Kirihata , Gerhard Mueller , David Russell Hanson
IPC分类号： G11C2900
CPC分类号： G11C29/02
摘要： A method for testing a data path for a semiconductor memory device, in accordance with the present invention, includes providing a semiconductor memory device including a plurality of stages in a data path, and transferring data into the data path. Components are disabled to isolate at least one stage of the plurality of stages such that data written to or read from the at least one stage is available at an output. The data at the output is preferably compared to expected data. Alternately, system level calibration between devices may be performed to ensure proper communication between devices without destroying data in a memory array and making a dynamic data skew calibration possibly while running an application.
摘要翻译：根据本发明的用于测试半导体存储器件的数据路径的方法包括提供包括数据路径中的多个级并将数据传送到数据路径的半导体存储器件。组件被禁用以隔离多个级中的至少一个级，使得写入或从至少一个级读取的数据在输出端可用。优选地将输出端的数据与预期数据进行比较。或者，可以执行设备之间的系统级校准，以确保设备之间的正确通信，而不会破坏存储器阵列中的数据并且在运行应用时可能进行动态数据偏移校准。

15. 发明授权

US06680857B2 Unit-architecture with implemented limited bank-column-select repairability 有权
标题翻译：单元架构采用有限的库列选择可修复性
公开(公告)号：US06680857B2
公开(公告)日：2004-01-20
申请号：US09964208
申请日：2001-09-26
申请人： Gerhard Mueller , Toshiaki Kirihata
发明人： Gerhard Mueller , Toshiaki Kirihata
IPC分类号： H01L27020
CPC分类号： G11C29/70
摘要： Multiple conductive paths are provided in a circuit portion between a circuit element and a logic block, enabling repairing of defects in the conductive line coupling the circuit element and logic blocks without the use of fusing.
摘要翻译：在电路元件和逻辑块之间的电路部分提供多个导电路径，能够修复在不使用熔断的情况下连接电路元件和逻辑块的导线中的缺陷。

16. 发明授权

US06522171B2 Method of reducing sub-threshold leakage in circuits during standby mode 有权
公开(公告)号：US06522171B2
公开(公告)日：2003-02-18
申请号：US09759011
申请日：2001-01-11
申请人： David R. Hanson , Toshiaki Kirihata , Gerhard Mueller
发明人： David R. Hanson , Toshiaki Kirihata , Gerhard Mueller
IPC分类号： H03K19096
CPC分类号： H03K19/0016 , H03K19/0963
摘要： A dynamic logic circuit having reduced sub-threshold leakage current during standby mode comprises a connection to at least one upper power rail, a connection to a lower power rail, a precharge node, and an output node adapted to be charged to the potential of the upper power rail after a precharge signal is received at the precharge node. A latch on the output node is provided to maintain the potential at the output node, along with at least one input node for receiving at least one evaluation signal to maintain the potential at the output node to the voltage of the upper power rail or reduce the potential at the output node to the potential of the lower power rail. A device is coupled to the output node to set the output node to a potential which minimizes the sub-threshold leakage upon receipt of a standby signal to maintain the potential at the output node at the potential of the upper power rail or at the potential of the lower power rail.

17. 发明授权

US06683486B2 Low voltage shifter with latching function 失效
标题翻译：具有锁定功能的低电压转换器
公开(公告)号：US06683486B2
公开(公告)日：2004-01-27
申请号：US10114221
申请日：2002-04-02
申请人： David Hanson , Gerhard Mueller , Toshiaki Kirihata
发明人： David Hanson , Gerhard Mueller , Toshiaki Kirihata
IPC分类号： H03L500
CPC分类号： H03K3/356147 , H03K3/012
摘要： A low voltage level shifter circuit with an embedded latch, implemented on a signal line having thereon low voltage signals. There is included a low voltage level shifter circuit configured to receive a low voltage input signal from a first portion of the signal line and output a higher voltage output signal on a second portion of the signal line. A latching circuit is also included, and is configured to latch the low voltage input signal from the first portion of the signal line.
摘要翻译：具有嵌入式锁存器的低电压电平移位器电路，其在具有低电压信号的信号线上实现。包括低电压电平移位器电路，其配置为从信号线的第一部分接收低电压输入信号，并在信号线的第二部分上输出更高电压的输出信号。还包括锁存电路，并且被配置为锁存来自信号线的第一部分的低电压输入信号。

18. 发明授权

US06370055B1 Semiconductor memory having asymmetric column addressing and twisted read write drive (RWD) line architecture 失效
标题翻译：具有非对称列寻址和双绞读写驱动（RWD）线架构的半导体存储器
公开(公告)号：US06370055B1
公开(公告)日：2002-04-09
申请号：US09795761
申请日：2001-02-28
申请人： David Hanson , Gerhard Mueller , Toshiaki Kirihata
发明人： David Hanson , Gerhard Mueller , Toshiaki Kirihata
IPC分类号： G11C506
CPC分类号： G11C5/063
摘要： There is provided a semiconductor memory having a plurality of memory units. The memory includes a plurality of read write drive (RWD) lines horizontally and/or vertically twisted such that the RWD lines are shared between the plurality of memory units. A plurality of columns is included in each of the plurality of memory units. Each of the plurality of columns is adapted to access the plurality of RWD lines through asymmetrical addressing.
摘要翻译：提供了具有多个存储单元的半导体存储器。存储器包括水平和/或垂直扭转的多个读写驱动（RWD）线，使得RWD线在多个存储器单元之间共享。在多个存储单元的每一个中包括多个列。多个列中的每一个适于通过非对称寻址来访问多个RWD线。

19. 发明授权

US06240043B1 SDRAM with a maskable input 有权
标题翻译： SDRAM具有可屏蔽输入
公开(公告)号：US06240043B1
公开(公告)日：2001-05-29
申请号：US09456588
申请日：1999-12-08
申请人： David R. Hanson , Toshiaki Kirihata , Gerhard Mueller
发明人： David R. Hanson , Toshiaki Kirihata , Gerhard Mueller
IPC分类号： G11C800
CPC分类号： G11C7/1006 , G11C7/1021
摘要： A random access memory (RAM) included in an integrated circuit and particularly a synchronous dynamic RAM (SDRAM) having a maskable data input. The SDRAM includes an xy data input register receiving a burst x bits long and y bits wide corresponding to the number of data lines (DQs). An xy mask register receives a corresponding mask bit for each received data bit, each mask bit indicating whether the corresponding data bit is stored in the SDRAM array. An enable buffer receives data outputs from the xy data input register and passes the individual data outputs to the array depending on corresponding mask states stored in the xy mask register. The mask register is preferably set to a masked state. Un masking occurs when an enable signal is asserted on a bit by bit basis. This allows the remaining bits within the burst length to be in a masked state when a write burst interrupt command is asserted. During an input prefetch, an interrupt may occur causing any received portion of the burst or prefetch to be stored in the array without disturbing memory locations corresponding to the balance or remaining bits of the prefetch.
摘要翻译：包括在集成电路中的随机存取存储器（RAM），特别是具有可屏蔽数据输入的同步动态RAM（SDRAM）。 SDRAM包括一个xy数据输入寄存器，它接收与数据线（DQ）数量相对应的突发x位长和y位宽。 xy屏蔽寄存器接收每个接收数据位的相应掩码位，每个掩码位指示对应的数据位是否存储在SDRAM阵列中。使能缓冲器从xy数据输入寄存器接收数据输出，并根据存储在xy掩码寄存器中的相应屏蔽状态将各个数据输出传递给阵列。掩模寄存器优选设置为掩蔽状态。当使能信号被逐位置信时，会发生解掩码。当允许写突发中断命令被断言时，允许脉冲串长度内的其余位处于屏蔽状态。在输入预取期间，可能会发生中断，导致突发或预取的任何接收的部分被存储在阵列中，而不会干扰对应于预取的余额或剩余比特的存储器位置。

20. 发明授权

US6140855A Dynamic-latch-receiver with self-reset pointer 失效
标题翻译：具有自复位指针的动态锁存器
公开(公告)号：US6140855A
公开(公告)日：2000-10-31
申请号：US281461
申请日：1999-03-30
申请人： Toshiaki Kirihata , Gerhard Mueller , David R. Hanson
发明人： Toshiaki Kirihata , Gerhard Mueller , David R. Hanson
IPC分类号： H03K19/0175 , G06F13/28 , G11C7/10 , G11C11/407 , H04L25/02 , H04L25/03 , H03K3/356
CPC分类号： G11C7/1087 , G11C7/1078
摘要： A dynamic latch receiver device comprises a sequence of data latch devices arranged in parallel for enabling sequential latching of data signals communicated serially on a single data line. The device includes a first pointer signal generator for generating a sequence of one or more first pointer signals, each generated first pointer signal of a sequence corresponding to a specific latch device and overlapping in time with a prior generated first pointer signal of the sequence; and, a pulse converter device associated with a latch device for receiving a corresponding first pointer signal and generating a respective second pointer signal for input to a respective latch device, each second pointer signal generated in a non-overlapping sequence for triggering a respective latching of each data signal in synchronism with serially communicated data signals.
摘要翻译：动态锁存接收器装置包括并行排列的一系列数据锁存装置，用于使能顺序锁存在单个数据线上串行通信的数据信号。该装置包括用于产生一个或多个第一指针信号的序列的第一指针信号发生器，每个产生与特定锁存装置相对应的序列的第一指针信号，并且与该序列的先前生成的第一指针信号在时间上重叠; 以及与锁存装置相关联的脉冲转换器装置，用于接收对应的第一指针信号并产生相应的第二指针信号以输入到相应的锁存装置，每个第二指针信号以不重叠的顺序产生，用于触发相应的锁存每个数据信号与串行数据信号同步。

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