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11. 发明申请

US20100191894A1 Digital Data Architecture Employing Redundant Links in a Daisy Chain of Component Modules 有权
标题翻译：数字数据架构在组件模块的菊花链中使用冗余链路
公开(公告)号：US20100191894A1
公开(公告)日：2010-07-29
申请号：US12361666
申请日：2009-01-29
申请人： Gerald Keith Bartley , Darryl John Becker , John Michael Borkenhagen , Philip Raymond Germann , William Paul Hovis , Mark Owen Maxson
发明人： Gerald Keith Bartley , Darryl John Becker , John Michael Borkenhagen , Philip Raymond Germann , William Paul Hovis , Mark Owen Maxson
IPC分类号： G06F12/06
CPC分类号： G06F11/201 , G06F13/1684 , G11C5/06
摘要： A communications architecture utilizes modules arranged in a daisy-chain, each module supporting multiple input and output ports. Point-to-point links are arranged so that a first output link of each of multiple modules connects to the next module in the chain, and a second output link connects to a module after it, and inputs arranged similarly, so that any single module can be by-passed in the event of malfunction. Multiple chains may be cross-linked and/or serviced by hubs or chains of hubs. Preferably, the redundant links are used in a non-degraded operating mode to provide higher bandwidth and/or reduced latency of communication. The exemplary embodiment is a memory subsystem in which the modules are buffered memory chips.
摘要翻译：通信架构使用以菊花链布置的模块，每个模块支持多个输入和输出端口。点对点链路被布置成使得多个模块中的每一个的第一输出链路连接到链中的下一个模块，并且第二输出链路在其之后连接到模块，并且类似地布置输入，使得任何单个模块发生故障时可以旁路。多个链路可以由集线器或集线器的链路交联和/或服务。优选地，冗余链路以非降级操作模式使用，以提供更高的带宽和/或降低的通信延迟。示例性实施例是其中模块是缓冲存储器芯片的存储器子系统。

12. 发明授权

US08108647B2 Digital data architecture employing redundant links in a daisy chain of component modules 有权
标题翻译：在组件模块的菊花链中采用冗余链路的数字数据架构
公开(公告)号：US08108647B2
公开(公告)日：2012-01-31
申请号：US12361666
申请日：2009-01-29
申请人： Gerald Keith Bartley , Darryl John Becker , John Michael Borkenhagen , Philip Raymond Germann , William Paul Hovis , Mark Owen Maxson
发明人： Gerald Keith Bartley , Darryl John Becker , John Michael Borkenhagen , Philip Raymond Germann , William Paul Hovis , Mark Owen Maxson
IPC分类号： G06F12/16 , G06F11/00
CPC分类号： G06F11/201 , G06F13/1684 , G11C5/06
摘要： A communications architecture utilizes modules arranged in a daisy-chain, each module supporting multiple input and output ports. Point-to-point links are arranged so that a first output link of each of multiple modules connects to the next module in the chain, and a second output link connects to a module after it, and inputs arranged similarly, so that any single module can be by-passed in the event of malfunction. Multiple chains may be cross-linked and/or serviced by hubs or chains of hubs. Preferably, the redundant links are used in a non-degraded operating mode to provide higher bandwidth and/or reduced latency of communication. The exemplary embodiment is a memory subsystem in which the modules are buffered memory chips.
摘要翻译：通信架构使用以菊花链布置的模块，每个模块支持多个输入和输出端口。点对点链路被布置成使得多个模块中的每一个的第一输出链路连接到链中的下一个模块，并且第二输出链路在其之后连接到模块，并且类似地布置输入，使得任何单个模块发生故障时可以旁路。多个链路可以由集线器或集线器的链路交联和/或服务。优选地，冗余链路以非降级操作模式使用，以提供更高的带宽和/或降低的通信延迟。示例性实施例是其中模块是缓冲存储器芯片的存储器子系统。

13. 发明申请

US20080307253A1 Method and Apparatus for Implementing Redundant Memory Access Using Multiple Controllers on the Same Bank of Memory 有权
标题翻译：用于在同一存储器上使用多个控制器实现冗余存储器访问的方法和装置
公开(公告)号：US20080307253A1
公开(公告)日：2008-12-11
申请号：US11872191
申请日：2007-10-15
申请人： Gerald Keith Bartley , Darryl John Becker , John Michael Borkenhagen , Paul Eric Dahlen , Philip Raymond Germann , William Paul Hovis
发明人： Gerald Keith Bartley , Darryl John Becker , John Michael Borkenhagen , Paul Eric Dahlen , Philip Raymond Germann , William Paul Hovis
IPC分类号： G06F11/16
CPC分类号： G06F11/2017 , G06F2201/85 , G11C29/70
摘要： A method and apparatus implement redundant memory access using multiple controllers on the same bank of memory, and a design structure on which the subject circuit resides is provided. A first memory controller uses the memory as its primary address space, for storage and fetches. A second redundant controller is also connected to the same memory. System control logic is used to notify the redundant controller of the need to take over the memory interface. The redundant controller initializes if required and takes control of the memory. The memory only needs to be initialized if the system has to be brought down and restarted in the redundant mode. This invention allows the system to continue to stay up and continue running during a memory controller or link failure.
摘要翻译：一种方法和装置利用在同一组存储器上的多个控制器实现冗余存储器访问，并且提供了一个主题电路驻留的设计结构。第一个存储器控制器使用存储器作为其主地址空间，用于存储和提取。第二个冗余控制器也连接到同一个存储器。系统控制逻辑用于通知冗余控制器需要接管存储器接口。如果需要，冗余控制器将初始化并控制存储器。如果系统必须在冗余模式下被关闭并重新启动，才需要初始化内存。本发明允许系统在存储器控制器或链路故障期间继续保持并继续运行。

14. 发明申请

US20080307252A1 Method and Apparatus for Implementing Redundant Memory Access Using Multiple Controllers on the Same Bank of Memory 有权
标题翻译：用于在同一存储器上使用多个控制器实现冗余存储器访问的方法和装置
公开(公告)号：US20080307252A1
公开(公告)日：2008-12-11
申请号：US11758732
申请日：2007-06-06
申请人： Gerald Keith Bartley , Darryl John Becker , John Michael Borkenhagen , Paul Eric Dahlen , Philip Raymond Germann , William Paul Hovis
发明人： Gerald Keith Bartley , Darryl John Becker , John Michael Borkenhagen , Paul Eric Dahlen , Philip Raymond Germann , William Paul Hovis
IPC分类号： G06F12/16 , G06F11/00
CPC分类号： G06F11/2017
摘要： A method and apparatus implement redundant memory access using multiple controllers on the same bank of memory. A first memory controller uses the memory as its primary address space, for storage and fetches. A second redundant controller is also connected to the same memory. System control logic is used to notify the redundant controller of the need to take over the memory interface. The redundant controller initializes if required and takes control of the memory. The memory only needs to be initialized if the system has to be brought down and restarted in the redundant mode. This invention allows the system to continue to stay up and continue running during a memory controller or link failure.
摘要翻译：一种方法和装置利用在同一组存储器上的多个控制器实现冗余存储器访问。第一个存储器控制器使用存储器作为其主地址空间，用于存储和提取。第二个冗余控制器也连接到同一个存储器。系统控制逻辑用于通知冗余控制器需要接管存储器接口。如果需要，冗余控制器将初始化并控制存储器。如果系统必须在冗余模式下被关闭并重新启动，才需要初始化内存。本发明允许系统在存储器控制器或链路故障期间继续保持并继续运行。

15. 发明授权

US07882479B2 Method and apparatus for implementing redundant memory access using multiple controllers on the same bank of memory 有权
标题翻译：用于在同一存储器组上使用多个控制器实现冗余存储器访问的方法和装置
公开(公告)号：US07882479B2
公开(公告)日：2011-02-01
申请号：US11872191
申请日：2007-10-15
申请人： Gerald Keith Bartley , Darryl John Becker , John Michael Borkenhagen , Paul Eric Dahlen , Philip Raymond Germann , William Paul Hovis
发明人： Gerald Keith Bartley , Darryl John Becker , John Michael Borkenhagen , Paul Eric Dahlen , Philip Raymond Germann , William Paul Hovis
IPC分类号： G06F17/50
CPC分类号： G06F11/2017 , G06F2201/85 , G11C29/70
摘要： A method and apparatus implement redundant memory access using multiple controllers on the same bank of memory, and a design structure on which the subject circuit resides is provided. A first memory controller uses the memory as its primary address space, for storage and fetches. A second redundant controller is also connected to the same memory. System control logic is used to notify the redundant controller of the need to take over the memory interface. The redundant controller initializes if required and takes control of the memory. The memory only needs to be initialized if the system has to be brought down and restarted in the redundant mode. This invention allows the system to continue to stay up and continue running during a memory controller or link failure.
摘要翻译：一种方法和装置利用在同一组存储器上的多个控制器实现冗余存储器访问，并且提供了一个主题电路驻留的设计结构。第一个存储器控制器使用存储器作为其主地址空间，用于存储和提取。第二个冗余控制器也连接到同一个存储器。系统控制逻辑用于通知冗余控制器需要接管存储器接口。如果需要，冗余控制器将初始化并控制存储器。如果系统必须在冗余模式下被关闭并重新启动，才需要初始化内存。本发明允许系统在存储器控制器或链路故障期间继续保持并继续运行。

16. 发明授权

US07725762B2 Implementing redundant memory access using multiple controllers on the same bank of memory 有权
标题翻译：在同一内存块上使用多个控制器实现冗余内存访问
公开(公告)号：US07725762B2
公开(公告)日：2010-05-25
申请号：US11758732
申请日：2007-06-06
申请人： Gerald Keith Bartley , Darryl John Becker , John Michael Borkenhagen , Paul Eric Dahlen , Philip Raymond Germann , William Paul Hovis
发明人： Gerald Keith Bartley , Darryl John Becker , John Michael Borkenhagen , Paul Eric Dahlen , Philip Raymond Germann , William Paul Hovis
IPC分类号： G06F11/00
CPC分类号： G06F11/2017
摘要： A method and apparatus implement redundant memory access using multiple controllers on the same bank of memory. A first memory controller uses the memory as its primary address space, for storage and fetches. A second redundant controller is also connected to the same memory. System control logic is used to notify the redundant controller of the need to take over the memory interface. The redundant controller initializes if required and takes control of the memory. The memory only needs to be initialized if the system has to be brought down and restarted in the redundant mode. This invention allows the system to continue to stay up and continue running during a memory controller or link failure.
摘要翻译：一种方法和装置利用在同一组存储器上的多个控制器实现冗余存储器访问。第一个存储器控制器使用存储器作为其主地址空间，用于存储和提取。第二个冗余控制器也连接到同一个存储器。系统控制逻辑用于通知冗余控制器需要接管存储器接口。如果需要，冗余控制器将初始化并控制存储器。如果系统必须在冗余模式下被关闭并重新启动，才需要初始化内存。本发明允许系统在存储器控制器或链路故障期间继续保持并继续运行。

17. 发明授权

US07921264B2 Dual-mode memory chip for high capacity memory subsystem 有权
标题翻译：用于高容量存储器子系统的双模存储芯片
公开(公告)号：US07921264B2
公开(公告)日：2011-04-05
申请号：US11769011
申请日：2007-06-27
申请人： Gerald Keith Bartley , John Michael Borkenhagen , Philip Raymond Germann
发明人： Gerald Keith Bartley , John Michael Borkenhagen , Philip Raymond Germann
IPC分类号： G06F12/00
CPC分类号： G06F13/1684 , G06F12/0607 , G06F13/1694 , Y02D10/13 , Y02D10/14
摘要： A dual-mode memory chip supports a first operation mode in which received data access commands contain chip select data to identify the chip addressed by the command, and control logic in the memory chip determines whether the command is addressed to the chip, and a second operation mode in which the received data access command addresses a set of multiple chips. Preferably, the first mode supports a daisy-chained configuration of memory chips. Preferably the second mode supports a hierarchical interleaved memory subsystem, in which each addressable set of chips is configured as a tree, command and write data being propagated down the tree, the number of chips increasing at each succeeding level of the tree.
摘要翻译：双模存储器芯片支持第一操作模式，其中接收的数据访问命令包含芯片选择数据以识别由命令寻址的芯片，并且存储器芯片中的控制逻辑确定命令是否寻址到芯片，第二操作模式操作模式，其中所接收的数据访问命令寻址一组多个芯片。优选地，第一模式支持存储芯片的菊花链配置。优选地，第二模式支持分层交错存储器子系统，其中每个可寻址的芯片集合被配置为树，命令和写入数据在树下传播，在树的每个后续级别增加的码片数量。

18. 发明授权

US07809913B2 Memory chip for high capacity memory subsystem supporting multiple speed bus 有权
标题翻译：支持多速总线的高容量内存子系统的内存芯片
公开(公告)号：US07809913B2
公开(公告)日：2010-10-05
申请号：US11769006
申请日：2007-06-27
申请人： Gerald Keith Bartley , John Michael Borkenhagen , Philip Raymond Germann
发明人： Gerald Keith Bartley , John Michael Borkenhagen , Philip Raymond Germann
IPC分类号： G06F13/18
CPC分类号： G06F13/4243
摘要： A memory module contains an interface for receiving memory access commands from an external source, in which a first portion of the interface receives memory access data at a first bus frequency and a second portion of the interface receives memory access data at a second different bus frequency. Preferably, the memory module contains a second interface for re-transmitting memory access data, also operating at dual frequency. The memory module is preferably used in a high-capacity memory subsystem organized in a tree configuration in which data accesses are interleaved. Preferably, the memory module has multiple-mode operation, one of which supports dual-speed buses for receiving and re-transmitting different parts of data access commands, and another of which supports conventional daisy-chaining.
摘要翻译：存储器模块包含用于从外部源接收存储器访问命令的接口，其中接口的第一部分以第一总线频率接收存储器访问数据，并且接口的第二部分以第二不同总线频率接收存储器访问数据。优选地，存储器模块包含第二接口，用于重新传输也以双频操作的存储器访问数据。存储器模块优选地用于以树形结构组织的高容量存储器子系统，其中数据访问是交错的。优选地，存储器模块具有多模式操作，其中之一支持用于接收和重新传送数据访问命令的不同部分的双速总线，另一个支持常规的菊花链。

19. 发明授权

US07921271B2 Hub for supporting high capacity memory subsystem 有权
标题翻译：用于支持高容量内存子系统的集线器
公开(公告)号：US07921271B2
公开(公告)日：2011-04-05
申请号：US11769019
申请日：2007-06-27
申请人： Gerald Keith Bartley , John Michael Borkenhagen , Philip Raymond Germann
发明人： Gerald Keith Bartley , John Michael Borkenhagen , Philip Raymond Germann
IPC分类号： G06F13/18
CPC分类号： G06F13/4243
摘要： A high-capacity memory subsystem architecture utilizes multiple memory modules arranged in one or more clusters, each attached to a respective hub which in turn is attached to a memory controller. Within a cluster, data is interleaved so that each data access command accesses all modules of the cluster. The hub communicates with the memory modules at a lower bus frequency, but the distributing of data among multiple modules enables the cluster to maintain the composite data rate of the memory-controller-to-hub bus. Preferably, the memory system employs buffered memory chips having dual-mode operation, one of which supports a cluster configuration in which data is interleaved and the communications buses operate at reduced bus width and/or reduced bus frequency to match the level of interleaving.
摘要翻译：高容量存储器子系统架构利用布置在一个或多个簇中的多个存储器模块，每个存储器模块连接到相应的集线器，该集线器又连接到存储器控制器。在集群内，数据被交织，以便每个数据访问命令访问集群的所有模块。集线器以较低的总线频率与存储器模块通信，但是在多个模块之间分配数据使集群能够保持存储器 - 控制器到集线器总线的复合数据速率。优选地，存储器系统采用具有双模操作的缓冲存储器芯片，其中之一支持数据被交错的集群配置，并且通信总线以减小的总线宽度和/或减少的总线频率进行操作以匹配交织级别。

20. 发明授权

US07822936B2 Memory chip for high capacity memory subsystem supporting replication of command data 有权
标题翻译：支持高容量内存子系统的内存芯片支持复制命令数据
公开(公告)号：US07822936B2
公开(公告)日：2010-10-26
申请号：US11769001
申请日：2007-06-27
申请人： Gerald Keith Bartley , John Michael Borkenhagen , Philip Raymond Germann
发明人： Gerald Keith Bartley , John Michael Borkenhagen , Philip Raymond Germann
IPC分类号： G06F13/10
CPC分类号： G06F13/1684 , G06F12/084 , Y02D10/13 , Y02D10/14
摘要： A memory module contains a first interface for receiving data access commands and a second interface for re-transmitting data access commands to other memory modules, the second interface propagating multiple copies of received data access commands to multiple other memory modules. The memory module is preferably used in a high-capacity memory subsystem organized in a tree configuration in which data accesses are interleaved. Preferably, the memory module has multiple-mode operation, one of which supports multiple replication of commands and another of which supports conventional daisy-chaining.
摘要翻译：存储器模块包括用于接收数据访问命令的第一接口和用于将数据访问命令重新传送到其他存储器模块的第二接口，第二接口将接收的数据访问命令的多个副本传播到多个其他存储器模块。存储器模块优选地用于以树形结构组织的高容量存储器子系统，其中数据访问是交错的。优选地，存储器模块具有多模式操作，其中之一支持命令的多个复制，另一个支持常规的菊花链。

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