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11. 发明授权

US4723228A Memory decoding circuit 失效
标题翻译：存储器解码电路
公开(公告)号：US4723228A
公开(公告)日：1988-02-02
申请号：US528205
申请日：1983-08-31
申请人： Ashwin H. Shah , James D. Gallia , Shivaling S. Mahant-Shetti
发明人： Ashwin H. Shah , James D. Gallia , Shivaling S. Mahant-Shetti
IPC分类号： G11C11/413 , G11C7/10 , G11C8/12 , G11C11/34 , G11C11/41 , G11C11/419 , G11C8/00
CPC分类号： G11C7/10 , G11C8/12
摘要： Column decoding is performed using multiply decoded subsets of column address bits bussed across the array to multiple first stage and second stage column multiplexers. That is, for example, in an 8k by 9 memory wherein each subarray contains 16 selectable columns at each bit position, two of the address bits would be fully decoded to provide four buss lines across the chip. Each column has a primary sense amplifier, controlled by one of these four decoded lines. The outputs of each set of four primary sense amplifiers are multiplexed into a secondary sense amplifier, (preferably on a local three-scale buss) and the output of each secondary sense amplifier is selected or deselected by four buss lines which are the decoded signals corresponding to the other two address bits which select one of 16 columns. Preferably multiplexing of the output of the secondary sense amplifiers is accomplished by a three-state buffer, so that the output of these buffers can be accomplished as a wired-or function.
摘要翻译：列解码使用跨阵列总线的列地址位的多位解码子集执行到多个第一级和第二级列复用器。也就是说，例如，在8k×9存储器中，每个子阵列在每个位位置包含16个可选列，地址位中的两个将被完全解码以在芯片上提供四条总线。每列具有由这四条解码线中的一条控制的初级读出放大器。每组四个主感测放大器的输出被复用到次级读出放大器（优选地在局部三级总线上），并且每个次级读出放大器的输出由对应的解码信号的四条母线选择或取消选择到另外两个选择16列之一的地址位。优选地，二次感测放大器的输出的多路复用由三态缓冲器实现，使得这些缓冲器的输出可以被实现为有线或功能。

12. 发明授权

US06954231B2 CMOS sensor camera with on-chip image compression 有权
标题翻译： CMOS传感器相机具有片上图像压缩功能
公开(公告)号：US06954231B2
公开(公告)日：2005-10-11
申请号：US10022995
申请日：2001-12-17
申请人： Shivaling S. Mahant-Shetti
发明人： Shivaling S. Mahant-Shetti
IPC分类号： H04N5/374 , H04N5/378 , H04N3/14
CPC分类号： H04N5/374
摘要： A digital camera (10) that has an array (11) of CMOS sensor elements (11a). The array (11) is read in a manner that performs spatial-to-frequency transforms for image compression on the analog output signals of the sensor elements. More specifically, wordlines (12) and bitlines (13) are pulsewidth modulated so that the coincidence of their “on” times corresponds to a desired coefficient of the basis function of the transform (FIGS. 3 and 4). Additional comparator circuitry (15), quantizers (16), and encoding circuitry (19) can be part of the same integrated circuit as the array (11).
摘要翻译：一种数字照相机（10），其具有CMOS传感器元件（11a）的阵列（11）。以对传感器元件的模拟输出信号进行图像压缩的空间 - 频率变换的方式来读取阵列（11）。更具体地，字线（12）和位线（13）被脉冲宽度调制，使得它们的“接通”时间的一致对应于变换的基函数的期望系数（图3和图4）。附加比较器电路（15），量化器（16）和编码电路（19）可以是与阵列（11）相同的集成电路的一部分。

13. 发明授权

US5939740A Gate array base cell 失效
标题翻译：门阵列基体单元
公开(公告)号：US5939740A
公开(公告)日：1999-08-17
申请号：US679521
申请日：1996-07-12
申请人： Mashashi Hashimoto , Shivaling S. Mahant-Shetti
发明人： Mashashi Hashimoto , Shivaling S. Mahant-Shetti
IPC分类号： H01L21/82 , H01L21/8234 , H01L21/8238 , H01L27/088 , H01L27/118 , H01L27/02
CPC分类号： H01L27/11807 , H01L21/8238
摘要： A gate array base cell which can easily be configured as high conductivity transistor device or a low conductivity transistor device comprises a moat region of first conductivity type, typically heavily doped n-type silicon or heavily doped p-type silicon, for example. A channel region of a different conductivity type separates the moat region into at least three portions. An insulating layer, such as silicon dioxide, for example, and a gate are formed above the channel region. The gate may be formed of polysilicon, for example. Modifications, variations, circuit configurations and an illustrative fabrication method are also disclosed.
摘要翻译：可以容易地配置为高导电性晶体管器件或低导电性晶体管器件的栅阵列基电池包括例如通常为重掺杂n型硅或重掺杂p型硅的第一导电类型的护环区域。不同导电类型的沟道区域将护城河区域分成至少三个部分。在通道区域上形成例如二氧化硅等绝缘层和栅极。例如，栅极可以由多晶硅形成。还公开了修改，变型，电路配置和说明性制造方法。

14. 发明授权

US5652441A Gate array base cell with novel gate structure 失效
标题翻译：具有新颖栅极结构的栅极阵列基体
公开(公告)号：US5652441A
公开(公告)日：1997-07-29
申请号：US328998
申请日：1994-10-25
申请人： Mashashi Hashimoto , Shivaling S. Mahant-Shetti
发明人： Mashashi Hashimoto , Shivaling S. Mahant-Shetti
IPC分类号： H01L21/82 , H01L21/8238 , H01L27/092 , H01L27/118 , H01L27/10 , H01L27/11
CPC分类号： H01L27/11807 , Y10S257/903
摘要： A semiconductor 110 device includes an array of like base cells wherein each base cell includes at least one source 132 and at least one drain 130 region formed in a semiconductor substrate. At least one gate 126 is formed over and insulated from a channel region 118 which separates the source 132 and drain 130 regions. An insulating layer 190 overlies the structure. A plurality of contacts are formed in the insulating layer in a plurality of substantially parallel; evenly spaced grid lines G1-G5. In addition, at least one additional contact 150 formed between two adjacent ones G2 and G3 of the substantially parallel grid lines is formed. A plurality of interconnect lines 142 and 144 are formed over the insulating layer such that each contact is connected to at least one of the interconnect lines. Modifications, variations, circuit configurations and an illustrative fabrication method are also disclosed.
摘要翻译：半导体110器件包括类似的基本单元的阵列，其中每个基极单元包括形成在半导体衬底中的至少一个源极132和至少一个漏极130区域。至少一个栅极126形成在分离源极132和漏极130区域的沟道区域118的上方并与其绝缘。绝缘层190覆盖在结构上。绝缘层中形成多个大致平行的多个触头; 均匀间隔格栅G1-G5。此外，形成在基本上平行的栅格线的两个相邻的G2和G3之间形成的至少一个附加触点150。多个互连线142和144形成在绝缘层上，使得每个触点连接到互连线中的至少一个。还公开了修改，变型，电路配置和说明性制造方法。

15. 发明授权

US5563430A Gate array base cell 失效
公开(公告)号：US5563430A
公开(公告)日：1996-10-08
申请号：US475118
申请日：1995-06-07
申请人： Masashi Hashimoto , Shivaling S. Mahant-Shetti
发明人： Masashi Hashimoto , Shivaling S. Mahant-Shetti
IPC分类号： H01L21/82 , H01L21/8234 , H01L21/8238 , H01L27/088 , H01L27/118 , H01L27/02
CPC分类号： H01L27/11807 , H01L21/8238
摘要： A gate array base cell which can easily be configured as high conductivity transistor device or a low conductivity transistor device comprises a moat region of first conductivity type, typically heavily doped n-type silicon or heavily doped p-type silicon, for example. A channel region of a different conductivity type separates the moat region into at least three portions. An insulating layer, such as silicon dioxide, for example, and a gate are formed above the channel region. The gate may be formed of polysilicon, for example. Modifications, variations, circuit configurations and an illustrative fabrication method are also disclosed.

16. 发明授权

US5391943A Gate array cell with predefined connection patterns 失效
标题翻译：门阵列单元格具有预定义的连接模式
公开(公告)号：US5391943A
公开(公告)日：1995-02-21
申请号：US178712
申请日：1994-01-10
申请人： Shivaling S. Mahant-Shetti , Robert J. Landers
发明人： Shivaling S. Mahant-Shetti , Robert J. Landers
IPC分类号： H01L21/82 , H01L27/118 , H03K19/0175 , H03K19/0948 , H03K19/173 , H03K19/21 , H03K19/017
CPC分类号： H01L27/11807 , H03K19/1735
摘要： A base cell for a CMOS gate array is provided with a plurality of N-channel transistors 10 and a plurality of P-channel transistors 12. These transistors are interconnected at the transistor level to form a partially prewired circuit. Additional N-channel (14) and P-channel (70, 72) transistors are included in the base cell at least some of which are larger in size than those in the plurality of N-channel transistors 10 or the plurality of P-channel transistors 12. These larger size transistors are used as output drivers to send the logical output signal of the cell to another cell.
摘要翻译：用于CMOS门阵列的基电池设置有多个N沟道晶体管10和多个P沟道晶体管12.这些晶体管在晶体管级互连以形成部分预接线电路。附加的N沟道（14）和P沟道（70,72）晶体管包括在基底单元中，其中至少一些的尺寸大于多个N沟道晶体管10或多个P沟道晶体管12.这些较大尺寸的晶体管用作输出驱动器以将单元的逻辑输出信号发送到另一个单元。

17. 发明授权

US5367702A System and method for approximating nonlinear functions 失效
标题翻译：用于近似非线性函数的系统和方法
公开(公告)号：US5367702A
公开(公告)日：1994-11-22
申请号：US000071
申请日：1993-01-04
申请人： Shivaling S. Mahant-Shetti , Thomas J. Aton , Jerold A. Seitchik
发明人： Shivaling S. Mahant-Shetti , Thomas J. Aton , Jerold A. Seitchik
IPC分类号： G06F17/17 , G06F7/552 , G06F15/353
CPC分类号： G06F7/552 , G06F2207/5525
摘要： A system (10) is provided for approximating a nonlinear function. The system (10) comprises first and second multiple generating circuits (12) and (14) for multiplying a first quantity and a second quantity by up to three integer powers of two. First and second function generating circuits (16) and (18) generate first and second functions of the first and the second quantities by combining the multiples generated in first and second multiple generating circuits (12) and (14). First and second approximation generating circuits (20) and (22) generate first and second approximations of the nonlinear function by shifting the output of first and second function generating circuits (16) and (18). Approximation selecting circuit (24) outputs the appropriate approximation generated in first and second approximation generating circuits (20) and (22).
摘要翻译：提供一种用于近似非线性函数的系统（10）。系统（10）包括用于将第一数量和第二数量乘以最多三个整数二的幂数的第一和第二多个产生电路（12）和（14）。第一和第二功能发生电路（16）和（18）通过组合在第一和第二多个发电电路（12）和（14）中产生的倍数来产生第一和第二量的第一和第二功能。第一和第二近似产生电路（20）和（22）通过移位第一和第二函数发生电路（16）和（18）的输出来产生非线性函数的第一和第二近似。近似选择电路（24）输出在第一和第二近似发生电路（20）和（22）中产生的适当近似。

18. 发明授权

US5345196A Method and apparatus for current and voltage control of an oscillator 失效
标题翻译：用于振荡器电流和电压控制的方法和装置
公开(公告)号：US5345196A
公开(公告)日：1994-09-06
申请号：US88993
申请日：1993-07-07
申请人： John W. Fattaruso , Shivaling S. Mahant-Shetti
发明人： John W. Fattaruso , Shivaling S. Mahant-Shetti
IPC分类号： H03K3/0231 , H03K3/354 , H03K17/041 , H03K17/687
CPC分类号： H03K3/0231 , H03K17/04106 , H03K17/687 , H03K3/354
摘要： A variable frequency oscillator (19) and method of producing an oscillating signal are provided in which a current mirror (12) receives a control current and generates a mirrored current. A capacitor (20) is coupled to the current mirror (12) and charges and discharges through the current mirror (12) based on the direction of the mirrored current. A trigger (22) is coupled to the capacitor (20) and outputs a first voltage level when the capacitor (20) charges to a first voltage threshold and outputs a second voltage level when the capacitor (20) discharges to a second voltage threshold. A switch (14) is coupled to the current mirror (12) and the trigger (22) for changing the direction of the mirrored current based on the output voltage of the trigger (22).
摘要翻译：提供了可变频率振荡器（19）和产生振荡信号的方法，其中电流镜（12）接收控制电流并产生镜像电流。电容器（20）耦合到电流镜（12），并且基于镜像电流的方向对电流镜（12）进行充电和放电。当电容器（20）充电到第一电压阈值时，触发器（22）耦合到电容器（20）并输出第一电压电平，并且当电容器（20）放电到第二电压阈值时，输出第二电压电平。开关（14）耦合到电流镜（12）和触发器（22），用于基于触发器（22）的输出电压来改变镜像电流的方向。

19. 发明授权

US5072276A Elevated CMOS 失效
标题翻译：高架CMOS
公开(公告)号：US5072276A
公开(公告)日：1991-12-10
申请号：US622254
申请日：1990-12-04
申请人： Satwinder S. Malhi , Ravishankar Sundaresan , Shivaling S. Mahant-Shetti
发明人： Satwinder S. Malhi , Ravishankar Sundaresan , Shivaling S. Mahant-Shetti
IPC分类号： H01L27/06 , H01L27/092 , H01L29/78
CPC分类号： H01L27/092 , H01L21/823885 , H01L27/0688 , H01L29/7827
摘要： A new class of CMOS integrated circuits, wherein the PMOS and NMOS devices are both configured as vertical transistors. One trench can contain a PMOS device, an NMOS device, and a gate which is coupled to control both the PMOS device and the NMOS device. Latchup problems do not arise, and n+ to p+ spacing rules are not required.
摘要翻译：一类新的CMOS集成电路，其中PMOS和NMOS器件均被配置为垂直晶体管。一个沟槽可以包含PMOS器件，NMOS器件和耦合以控制PMOS器件和NMOS器件的栅极。 Latchup问题不会出现，并且不需要n +到p +间隔规则。

20. 发明授权

US4978908A Scanning electron microscope based parametric testing method and apparatus 失效
公开(公告)号：US4978908A
公开(公告)日：1990-12-18
申请号：US327080
申请日：1989-03-22
申请人： Shivaling S. Mahant-Shetti , Thomas J. Aton , Rebeca J. Gale
发明人： Shivaling S. Mahant-Shetti , Thomas J. Aton , Rebeca J. Gale
IPC分类号： H01J37/28 , G01Q30/02 , G01R31/302 , G01R31/305 , H01L21/66
CPC分类号： G01R31/305
摘要： A scanning electron microscope (28) is connected to a test structure (48) formed on a semiconductor wafer. The test structure (48) comprises a plurality of first parallel structures (54) and a plurality of second parallel structure (56) transverse to and interlocking with the first structures (54). An island (60) is formed within a grid (58) formed by the structures (54-56) and is separated therefrom. An electron beam (38) from the scanning electron microscope (28) is aimed at the structure (48) and secondary electrons emitted therefrom are visually displayed on a monitor (44). The visual display (47) provides information on whether the island (60) is electrically separated from the mesh (58) or shorted thereto by comparing the intensity of the various islands (60).

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