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11. 发明申请

US20050101087A1 Semiconductor memory device and its production process 有权
标题翻译：半导体存储器件及其生产工艺
公开(公告)号：US20050101087A1
公开(公告)日：2005-05-12
申请号：US10727266
申请日：2003-12-04
申请人： Tetsuo Endoh , Fujio Masuoka , Takuji Tanigami , Takashi Yokoyama , Shinji Horii
发明人： Tetsuo Endoh , Fujio Masuoka , Takuji Tanigami , Takashi Yokoyama , Shinji Horii
IPC分类号： H01L21/8247 , G11C16/04 , H01L21/28 , H01L21/336 , H01L21/8246 , H01L21/84 , H01L27/02 , H01L27/115 , H01L27/12 , H01L29/06 , H01L29/788 , H01L29/792
CPC分类号： H01L27/0207 , G11C16/0483 , H01L21/28273 , H01L21/28282 , H01L21/84 , H01L27/115 , H01L27/11519 , H01L27/11553 , H01L27/11556 , H01L27/11568 , H01L27/1203 , H01L29/0692 , H01L29/66825 , H01L29/66833 , H01L29/7881 , H01L29/792 , H01L29/7926
摘要： The present invention provides a semiconductor memory device comprising: a first conductivity type semiconductor substrate; and a plurality of memory cells constituted of an island-like semiconductor layer which is formed on the semiconductor substrate, and a charge storage layer and a control gate which are formed entirely or partially around a sidewall of the island-like semiconductor layer, wherein the plurality of memory cells are disposed in series, the island-like semiconductor layer which constitutes the memory cells has cross-sectional areas varying in stages in a horizontal direction of the semiconductor substrate, and an insulating film capable of passing charges is provided at least in a part of a plane of the island-like semiconductor layer horizontal to the semiconductor substrate.
摘要翻译：本发明提供一种半导体存储器件，包括：第一导电型半导体衬底; 以及由在半导体衬底上形成的岛状半导体层和电荷存储层和控制栅极构成的多个存储单元，其形成在岛状半导体层的侧壁的整个或部分周围，其中，多个存储单元被串联设置，构成存储单元的岛状半导体层具有在半导体衬底的水平方向上分级变化的横截面区域，并且能够至少在岛状半导体层的与半导体衬底水平的平面的一部分。

12. 发明授权

US07387935B2 Memory cell unit, nonvolatile semiconductor storage device including memory cell unit, and memory cell array driving method 有权
标题翻译：存储单元单元，包括存储单元单元的非易失性半导体存储器件和存储单元阵列驱动方法
公开(公告)号：US07387935B2
公开(公告)日：2008-06-17
申请号：US10941505
申请日：2004-09-14
申请人： Fujio Masuoka , Hiroshi Sakuraba , Fumiyoshi Matsuoka , Syounosuke Ueno , Ryusuke Matsuyama , Shinji Horii , Takuji Tanigami
发明人： Fujio Masuoka , Hiroshi Sakuraba , Fumiyoshi Matsuoka , Syounosuke Ueno , Ryusuke Matsuyama , Shinji Horii , Takuji Tanigami
IPC分类号： H01L21/336 , G11C16/04
CPC分类号： H01L29/7926 , G11C16/0483 , H01L27/115 , H01L27/11556 , H01L29/7881 , H01L29/792
摘要： A memory cell unit including: a semiconductor substrate having a source diffusion layer in at least a part of a surface thereof; a column-shaped semiconductor layer provided on the semiconductor substrate, and having a drain diffusion layer provided in an uppermost portion thereof and a first low concentration impurity diffusion layer provided in an entire bottom portion thereof; a memory cell arrangement which includes a plurality of memory cells provided in a peripheral wall of the column-shaped semiconductor layer and connected in series perpendicularly to the substrate, the memory cells each having a charge storage layer and a control gate; a second impurity diffusion layer provided at a lower end of the memory cell arrangement; and a selection transistor having a gate electrode provided around the peripheral wall of the column-shaped semiconductor layer and connecting the second impurity diffusion layer and the first impurity diffusion layer; wherein the first impurity diffusion layer extends into a part of a channel region provided in the peripheral wall of the column-shaped semiconductor layer in opposed relation to the gate electrode of the selection transistor.
摘要翻译：一种存储单元，包括：在其表面的至少一部分中具有源极扩散层的半导体衬底; 设置在半导体基板上的柱状半导体层，在其最上部设置有漏极扩散层，在底部设置有第一低浓度杂质扩散层; 存储单元布置，其包括设置在所述列状半导体层的周壁中并且与所述基板垂直串联连接的多个存储单元，所述存储单元各自具有电荷存储层和控制栅极; 设置在所述存储单元布置的下端的第二杂质扩散层; 以及选择晶体管，其具有设置在所述柱状半导体层的周壁周围的栅电极，并且连接所述第二杂质扩散层和所述第一杂质扩散层; 其中所述第一杂质扩散层延伸到与所述选择晶体管的栅电极相对的所述柱状半导体层的周壁中设置的沟道区的一部分。

13. 发明申请

US20050063237A1 Memory cell unit, nonvolatile semiconductor storage device including memory cell unit, and memory cell array driving method 有权
标题翻译：存储单元单元，包括存储单元单元的非易失性半导体存储器件和存储单元阵列驱动方法
公开(公告)号：US20050063237A1
公开(公告)日：2005-03-24
申请号：US10941505
申请日：2004-09-14
申请人： Fujio Masuoka , Hiroshi Sakuraba , Fumiyoshi Matsuoka , Syounosuke Ueno , Ryusuke Matsuyama , Shinji Horii , Takuji Tanigami
发明人： Fujio Masuoka , Hiroshi Sakuraba , Fumiyoshi Matsuoka , Syounosuke Ueno , Ryusuke Matsuyama , Shinji Horii , Takuji Tanigami
IPC分类号： G11C16/02 , G11C7/00 , G11C16/04 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L29/7926 , G11C16/0483 , H01L27/115 , H01L27/11556 , H01L29/7881 , H01L29/792
摘要： A memory cell unit including: a semiconductor substrate having a source diffusion layer in at least a part of a surface thereof; a column-shaped semiconductor layer provided on the semiconductor substrate, and having a drain diffusion layer provided in an uppermost portion thereof and a first low concentration impurity diffusion layer provided in an entire bottom portion thereof; a memory cell arrangement which includes a plurality of memory cells provided in a peripheral wall of the column-shaped semiconductor layer and connected in series perpendicularly to the substrate, the memory cells each having a charge storage layer and a control gate; a second impurity diffusion layer provided at a lower end of the memory cell arrangement; and a selection transistor having a gate electrode provided around the peripheral wall of the column-shaped semiconductor layer and connecting the second impurity diffusion layer and the first impurity diffusion layer; wherein the first impurity diffusion layer extends into a part of a channel region provided in the peripheral wall of the column-shaped semiconductor layer in opposed relation to the gate electrode of the selection transistor.
摘要翻译：一种存储单元，包括：在其表面的至少一部分中具有源极扩散层的半导体衬底; 设置在半导体基板上的柱状半导体层，在其最上部设置有漏极扩散层，在底部设置有第一低浓度杂质扩散层; 存储单元布置，其包括设置在所述列状半导体层的周壁中且与所述基板垂直串联连接的多个存储单元，所述存储单元各自具有电荷存储层和控制栅极; 设置在所述存储单元布置的下端的第二杂质扩散层; 以及选择晶体管，其具有设置在所述柱状半导体层的周壁周围的栅电极，并且连接所述第二杂质扩散层和所述第一杂质扩散层; 其中所述第一杂质扩散层延伸到与所述选择晶体管的栅电极相对的所述柱状半导体层的周壁中设置的沟道区的一部分。

14. 发明申请

US20050047209A1 Nonvolatile semiconductor storage device, and liquid crystal display device including the same 有权
标题翻译：非易失性半导体存储装置以及包含该非易失性半导体存储装置的液晶显示装置
公开(公告)号：US20050047209A1
公开(公告)日：2005-03-03
申请号：US10919777
申请日：2004-08-16
申请人： Fujio Masuoka , Hiroshi Sakuraba , Fumiyoshi Matsuoka , Syounosuke Ueno , Ryusuke Matsuyama , Shinji Horii
发明人： Fujio Masuoka , Hiroshi Sakuraba , Fumiyoshi Matsuoka , Syounosuke Ueno , Ryusuke Matsuyama , Shinji Horii
IPC分类号： G02F1/133 , G09G3/20 , G09G3/36 , G11C16/02 , G11C16/04 , G11C16/06 , G11C16/08 , G11C11/34
CPC分类号： G11C16/0483
摘要： A nonvolatile semiconductor storage device including: a plurality of memory cell unit groups each comprising one or more NAND nonvolatile memory cell units each comprising at least one memory cell having a control gate, a first selection transistor having a first selection gate, and a second selection transistor having a second selection gate, the memory cell unit groups each further comprising a control gate line connected to the control gate, a first selection gate line connected to the first selection gate, and a second selection gate line connected to the second selection gate; a common control gate line connected commonly to the control gate lines of different ones of the memory cell unit groups; a first common selection gate line connected commonly to the first selection gate lines of different ones of the memory cell unit groups; and a second common selection gate line connected commonly to the second selection gate lines of different ones of the memory cell unit groups; wherein the memory cells in the respective memory cell unit groups are each uniquely selected on the basis of a combination of the common control gate line and the first and second common selection gate lines.
摘要翻译：一种非易失性半导体存储装置，包括：多个存储单元单元组，每个存储单元单元组包括一个或多个NAND非易失性存储单元单元，每个非易失性存储单元单元包括至少一个具有控制栅极的存储单元，晶体管具有第二选择栅极，所述存储单元单元组还包括连接到所述控制栅极的控制栅极线，连接到所述第一选择栅极的第一选择栅极线和连接到所述第二选择栅极的第二选择栅极线; 公共控制栅极线，共同地连接到不同的存储单元单元组的控制栅极线; 第一公共选择栅极线，共同连接到不同的存储单元单元组的第一选择栅极线; 以及第二公共选择栅极线，共同连接到不同的存储单元单元组的第二选择栅极线; 其中各个存储单元单元组中的存储单元是基于公共控制栅极线和第一和第二公共选择栅极线的组合而被唯一地选择的。

15. 发明授权

US07088617B2 Nonvolatile semiconductor storage device, and liquid crystal display device including the same 有权
标题翻译：非易失性半导体存储装置以及包含该非易失性半导体存储装置的液晶显示装置
公开(公告)号：US07088617B2
公开(公告)日：2006-08-08
申请号：US10919777
申请日：2004-08-16
申请人： Fujio Masuoka , Hiroshi Sakuraba , Fumiyoshi Matsuoka , Syounosuke Ueno , Ryusuke Matsuyama , Shinji Horii
发明人： Fujio Masuoka , Hiroshi Sakuraba , Fumiyoshi Matsuoka , Syounosuke Ueno , Ryusuke Matsuyama , Shinji Horii
IPC分类号： G11C16/04
CPC分类号： G11C16/0483
摘要： A nonvolatile semiconductor storage device including: a plurality of memory cell unit groups each comprising one or more NAND nonvolatile memory cell units each comprising at least one memory cell having a control gate, a first selection transistor having a first selection gate, and a second selection transistor having a second selection gate, the memory cell unit groups each further comprising a control gate line connected to the control gate, a first selection gate line connected to the first selection gate, and a second selection gate line connected to the second selection gate; a common control gate line connected commonly to the control gate lines of different ones of the memory cell unit groups; a first common selection gate line connected commonly to the first selection gate lines of different ones of the memory cell unit groups; and a second common selection gate line connected commonly to the second selection gate lines of different ones of the memory cell unit groups; wherein the memory cells in the respective memory cell unit groups are each uniquely selected on the basis of a combination of the common control gate line and the first and second common selection gate lines.
摘要翻译：一种非易失性半导体存储装置，包括：多个存储单元单元组，每个存储单元单元组包括一个或多个NAND非易失性存储单元单元，每个非易失性存储单元单元包括至少一个具有控制栅极的存储单元，晶体管具有第二选择栅极，所述存储单元单元组还包括连接到所述控制栅极的控制栅极线，连接到所述第一选择栅极的第一选择栅极线和连接到所述第二选择栅极的第二选择栅极线; 公共控制栅极线，共同地连接到不同的存储单元单元组的控制栅极线; 第一公共选择栅极线，共同连接到不同的存储单元单元组的第一选择栅极线; 以及第二公共选择栅极线，共同连接到不同的存储单元单元组的第二选择栅极线; 其中各个存储单元单元组中的存储单元是基于公共控制栅极线和第一和第二公共选择栅极线的组合而被唯一地选择的。

16. 发明申请

US20050012134A1 Nonvolatile memory device driving method, semiconductor storage device, and liquid crystal display device including the semiconductor storage device 有权
标题翻译：非易失性存储器件驱动方法，半导体存储器件和包括半导体存储器件的液晶显示器件
公开(公告)号：US20050012134A1
公开(公告)日：2005-01-20
申请号：US10888693
申请日：2004-07-08
申请人： Fujio Masuoka , Hiroshi Sakuraba , Fumiyoshi Matsuoka , Syounosuke Ueno , Ryusuke Matsuyama , Shinji Horii
发明人： Fujio Masuoka , Hiroshi Sakuraba , Fumiyoshi Matsuoka , Syounosuke Ueno , Ryusuke Matsuyama , Shinji Horii
IPC分类号： G02F1/1343 , G02F1/133 , G09G3/36 , G11C16/02 , G11C16/04 , G11C16/06 , G11C16/12 , G11C16/14 , G11C16/30 , H01L21/8247 , H01L27/10 , H01L27/115 , H01L29/788 , H01L29/792 , H01L21/336 , H01L27/108 , H01L29/76 , H01L29/94 , H01L31/119
CPC分类号： H01L27/11556 , G09G3/3611 , G09G2320/0285 , G11C16/0433 , G11C16/14 , H01L27/115 , H01L29/7881 , H01L29/7887
摘要： A method for driving a nonvolatile memory device including a semiconductor substrate, an island semiconductor layer on the substrate, a memory cell having a control gate and a charge storage layer surrounding a peripheral surface of the island semiconductor layer, a first selection transistor provided between the memory cell and the substrate and having a first selection gate, a source diffusion layer between the substrate and the island semiconductor layer, a drain diffusion layer provided in an opposing end of the island semiconductor layer from the source diffusion layer, and a second selection transistor provided between the memory cell and the drain diffusion layer and having a second selection gate, the method comprising the steps of: applying a negative first voltage to the drain and the first selection gate, applying a positive second voltage to the second selection gate, and applying 0V or a positive third voltage to the source; and applying a positive fourth voltage higher than the second voltage to the control gate of the memory cell for injecting electric charges into the charge storage layer.
摘要翻译：一种用于驱动包括半导体衬底，在衬底上的岛状半导体层，具有控制栅极的存储单元和围绕岛状半导体层的外围表面的电荷存储层的非易失性存储器件的方法，存储单元和基板，并且具有第一选择栅极，在基板和岛状半导体层之间的源极扩散层，设置在岛状半导体层与源极扩散层相对的端部的漏极扩散层，以及第二选择晶体管设置在所述存储单元和所述漏极扩散层之间并具有第二选择栅极，所述方法包括以下步骤：向所述漏极和所述第一选择栅极施加负的第一电压，向所述第二选择栅极施加正的第二电压，以及向源施加0V或正的第三电压; 以及将高于第二电压的正的第四电压施加到用于向电荷存储层注入电荷的存储单元的控制栅极。

17. 发明授权

US07009888B2 Low voltage, island-layer-based nonvolatile semiconductor storage device with floating biased memory cell channel 有权
标题翻译：具有浮置偏置存储单元通道的低电压，基于岛的非易失性半导体存储器件
公开(公告)号：US07009888B2
公开(公告)日：2006-03-07
申请号：US10888693
申请日：2004-07-08
申请人： Fujio Masuoka , Hiroshi Sakuraba , Fumiyoshi Matsuoka , Syounosuke Ueno , Ryusuke Matsuyama , Shinji Horii
发明人： Fujio Masuoka , Hiroshi Sakuraba , Fumiyoshi Matsuoka , Syounosuke Ueno , Ryusuke Matsuyama , Shinji Horii
IPC分类号： G11C16/12
CPC分类号： H01L27/11556 , G09G3/3611 , G09G2320/0285 , G11C16/0433 , G11C16/14 , H01L27/115 , H01L29/7881 , H01L29/7887
摘要： A method for driving a nonvolatile memory device including a semiconductor substrate, an island semiconductor layer on the substrate, a memory cell having a control gate and a charge storage layer surrounding a peripheral surface of the island semiconductor layer, a first selection transistor provided between the memory cell and the substrate and having a first selection gate, a source diffusion layer between the substrate and the island semiconductor layer, a drain diffusion layer provided in an opposing end of the island semiconductor layer from the source diffusion layer, and a second selection transistor provided between the memory cell and the drain diffusion layer and having a second selection gate, the method comprising the steps of: applying a negative first voltage to the drain and the first selection gate, applying a positive second voltage to the second selection gate, and applying 0V or a positive third voltage to the source; and applying a positive fourth voltage higher than the second voltage to the control gate of the memory cell for injecting electric charges into the charge storage layer.
摘要翻译：一种用于驱动包括半导体衬底，在衬底上的岛状半导体层，具有控制栅极的存储单元和围绕岛状半导体层的外围表面的电荷存储层的非易失性存储器件的方法，存储单元和基板，并且具有第一选择栅极，在基板和岛状半导体层之间的源极扩散层，设置在岛状半导体层与源极扩散层相对的端部的漏极扩散层，以及第二选择晶体管设置在所述存储单元和所述漏极扩散层之间并具有第二选择栅极，所述方法包括以下步骤：向所述漏极和所述第一选择栅极施加负的第一电压，向所述第二选择栅极施加正的第二电压，以及向源施加0V或正的第三电压; 以及将高于第二电压的正的第四电压施加到用于向电荷存储层注入电荷的存储单元的控制栅极。

18. 发明授权

US07602026B2 Memory cell, semiconductor memory device, and method of manufacturing the same 有权
标题翻译：存储单元，半导体存储器件及其制造方法
公开(公告)号：US07602026B2
公开(公告)日：2009-10-13
申请号：US11474414
申请日：2006-06-26
申请人： Shinji Horii , Takashi Yokoyama , Tetsuya Ohnishi
发明人： Shinji Horii , Takashi Yokoyama , Tetsuya Ohnishi
IPC分类号： H01L23/62
CPC分类号： H01L27/101 , H01L27/2445 , H01L27/2463 , H01L45/04 , H01L45/1233 , H01L45/1253 , H01L45/147 , H01L45/1675 , H01L45/1683 , H01L2924/0002 , H01L2924/00
摘要： A memory cell in a semiconductor memory device comprises a variable resistor element configured so that a variable resistor body is sandwiched between a first electrode and a second electrode, and a transistor element capable of controlling a flow of current in the variable resistor element, wherein the transistor element and the variable resistor element are placed one over the other along a direction in which the first electrode, the variable resistor body, and the second electrode of the variable resistor element are layered, and one of the first electrode and the second electrode of the variable resistor element is connected to one electrode of the transistor element.
摘要翻译：半导体存储器件中的存储单元包括可变电阻器元件，其被配置为使得可变电阻体夹在第一电极和第二电极之间，以及晶体管元件，其能够控制可变电阻器元件中的电流流动，其中，晶体管元件和可变电阻元件沿着可变电阻器元件的第一电极，可变电阻体和第二电极层叠的方向一个放置，并且第一电极和第二电极中的一个可变电阻元件连接到晶体管元件的一个电极。

19. 发明申请

US20060289942A1 Memory cell, semiconductor memory device, and method of manufacturing the same 有权
公开(公告)号：US20060289942A1
公开(公告)日：2006-12-28
申请号：US11474414
申请日：2006-06-26
申请人： Shinji Horii , Takashi Yokoyama , Tetsuya Ohnishi
发明人： Shinji Horii , Takashi Yokoyama , Tetsuya Ohnishi
IPC分类号： H01L29/76 , H01L21/8238
CPC分类号： H01L27/101 , H01L27/2445 , H01L27/2463 , H01L45/04 , H01L45/1233 , H01L45/1253 , H01L45/147 , H01L45/1675 , H01L45/1683 , H01L2924/0002 , H01L2924/00
摘要： A memory cell in a semiconductor memory device comprises a variable resistor element configured so that a variable resistor body is sandwiched between a first electrode and a second electrode, and a transistor element capable of controlling a flow of current in the variable resistor element, wherein the transistor element and the variable resistor element are placed one over the other along a direction in which the first electrode, the variable resistor body, and the second electrode of the variable resistor element are layered, and one of the first electrode and the second electrode of the variable resistor element is connected to one electrode of the transistor element.

20. 发明授权

US07619675B2 Solid-state image taking apparatus with photoelectric converting and vertical charge transferring sections and method for fabricating the same 失效
标题翻译：具有光电转换和垂直电荷转移部分的固态摄像装置及其制造方法
公开(公告)号：US07619675B2
公开(公告)日：2009-11-17
申请号：US11175042
申请日：2005-07-06
申请人： Shinji Horii
发明人： Shinji Horii
IPC分类号： H04N3/14 , H04N5/335
CPC分类号： H01L27/14687 , H01L27/14623 , H01L27/14656 , H01L27/14806 , H01L27/14812 , H04N5/335
摘要： A solid-state image pickup apparatus includes one or a plurality of photoelectric converting sections for photoelectric converting incident light into a signal charge on a semiconductor substrate, and a vertical charge-transferring section for charge-transferring the signal charge photoelectric converted at the photoelectric converting section, in which the vertical charge-transferring section is located under the photoelectric converting section on the side of the semiconductor substrate.
摘要翻译：固体摄像装置包括一个或多个光电转换部分，用于将入射光光电转换成半导体衬底上的信号电荷;以及垂直电荷转移部分，用于对在光电转换处转换的信号电荷进行电荷转移其中垂直电荷转移部分位于半导体衬底侧的光电转换部分的下方。

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