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11. 发明授权

US07873933B2 Computer program for balancing power plane pin currents in a printed wiring board 有权
标题翻译：用于平衡印刷电路板中电源平面引脚电流的计算机程序
公开(公告)号：US07873933B2
公开(公告)日：2011-01-18
申请号：US11936673
申请日：2007-11-07
申请人： Hubert Harrer , Andreas Huber , Thomas-Michael Winkel
发明人： Hubert Harrer , Andreas Huber , Thomas-Michael Winkel
IPC分类号： G06F17/50 , H03K17/693
CPC分类号： H05K1/0265 , H05K2201/093 , H05K2201/09663 , H05K2201/0969 , H05K2201/10189 , Y10T29/49156
摘要： A computer program for balancing power plane pin currents in a printed wiring board (PWB) provides for reduction in pin counts required for power plane (including ground plane) connections and/or reduction in requirements for connector current handling per pin. One or more slots is introduced in the metal layer implementing the power plane that alter the current distribution in the power plane. The per-pin current profile for connector pins connected to the power plane is equalized by tuning the length of the slot(s). The slots may be dashed or made internal to the power plane metal layer to avoid weakening the metal layer for laminated multi-layer PWBs and may be shaped around a connector end when the power plane pin allocation is not uniform at the connector ends. The resulting equalization reduces either pin count required for carrying the power plane current or reduces connector pin current requirements.
摘要翻译：用于平衡印刷电路板（PWB）中的电源平面引脚电流的计算机程序提供了降低电源平面（包括接地平面）连接所需的引脚数量和/或减少每个引脚上连接器电流处理的要求。在实现改变电力平面中的电流分布的电力平面的金属层中引入一个或多个槽。连接到电源平面的连接器引脚的每引脚电流曲线通过调整插槽的长度来均衡。槽可以在电源平面金属层的内部虚线或内部形成，以避免层压的多层PWB的金属层的削弱，并且当电源平面引脚分配在连接器端不均匀时可以围绕连接器端成形。所产生的均衡减少了承载电源平面电流所需的引脚数或减少连接器引脚电流要求。

12. 发明授权

US07481469B2 Door lock for an oven 失效
标题翻译：烤箱门锁
公开(公告)号：US07481469B2
公开(公告)日：2009-01-27
申请号：US11809576
申请日：2007-06-01
申请人： Hubert Harrer
发明人： Hubert Harrer
IPC分类号： E05C3/06
CPC分类号： F24C15/022 , H05B6/6417 , Y10S292/69 , Y10T292/0911 , Y10T292/0948 , Y10T292/1021 , Y10T292/1082
摘要： A door lock for an oven includes a lock housing, a geared motor, an actuating shaft to be driven by the geared motor, a retaining plate and a locking element formed as a lever to be operated by the actuating shaft. The lever is mounted on the retaining plate and has a lever axle for reversibly changing location relative to the lock housing. A spring exerts a force being overcome in an emergency-unlocking function permitting adjustment of the retaining plate to allow opening of the lever having been previously brought into a locking position by the actuating shaft, without further operation of the actuating shaft. The actuating shaft is adjustable along its axis by the lever having been unlocked in an emergency.
摘要翻译：用于烤箱的门锁包括锁壳，齿轮传动马达，由齿轮传动马达驱动的致动轴，保持板和形成为由致动轴操作的杆的锁定元件。杠杆安装在保持板上，并具有用于相对于锁壳体可逆地改变位置的杠杆轴。弹簧在紧急解锁功能中施加克服的力，允许调节保持板，以允许先前已经由致动轴进入锁定位置的杠杆的打开，而不需要驱动轴的进一步操作。致动轴可以通过在紧急情况下被解锁的杠杆沿其轴线调节。

13. 发明申请

US20080059919A1 COMPUTER PROGRAM FOR BALANCING POWER PLANE PIN CURRENTS IN A PRINTED WIRING BOARD 有权
标题翻译：印刷电路板平衡电源引脚电流的计算机程序
公开(公告)号：US20080059919A1
公开(公告)日：2008-03-06
申请号：US11936673
申请日：2007-11-07
申请人： Hubert Harrer , Andreas Huber , Thomas-Michael Winkel
发明人： Hubert Harrer , Andreas Huber , Thomas-Michael Winkel
IPC分类号： G06F17/50
CPC分类号： H05K1/0265 , H05K2201/093 , H05K2201/09663 , H05K2201/0969 , H05K2201/10189 , Y10T29/49156
摘要： A computer program for balancing power plane pin currents in a printed wiring board (PWB) provides for reduction in pin counts required for power plane (including ground plane) connections and/or reduction in requirements for connector current handling per pin. One or more slots is introduced in the metal layer implementing the power plane that alter the current distribution in the power plane. The per-pin current profile for connector pins connected to the power plane is equalized by tuning the length of the slot(s). The slots may be dashed or made internal to the power plane metal layer to avoid weakening the metal layer for laminated multi-layer PWBs and may be shaped around a connector end when the power plane pin allocation is not uniform at the connector ends. The resulting equalization reduces either pin count required for carrying the power plane current or reduces connector pin current requirements.
摘要翻译：用于平衡印刷电路板（PWB）中的电源平面引脚电流的计算机程序提供了降低电源平面（包括接地平面）连接所需的引脚数量和/或减少每个引脚上连接器电流处理的要求。在实现改变电力平面中的电流分布的电力平面的金属层中引入一个或多个槽。连接到电源平面的连接器引脚的每引脚电流曲线通过调整插槽的长度来均衡。槽可以在电源平面金属层的内部虚线或内部形成，以避免层压的多层PWB的金属层的削弱，并且当电源平面引脚分配在连接器端不均匀时可以围绕连接器端成形。所产生的均衡减少了承载电源平面电流所需的引脚数或减少连接器引脚电流要求。

14. 发明申请

US20070241568A1 Door lock for an oven 失效
标题翻译：烤箱门锁
公开(公告)号：US20070241568A1
公开(公告)日：2007-10-18
申请号：US11809576
申请日：2007-06-01
申请人： Hubert Harrer
发明人： Hubert Harrer
IPC分类号： E05C1/06
CPC分类号： F24C15/022 , H05B6/6417 , Y10S292/69 , Y10T292/0911 , Y10T292/0948 , Y10T292/1021 , Y10T292/1082
摘要： A door lock for an oven includes a lock housing, a geared motor, an actuating shaft to be driven by the geared motor, a retaining plate and a locking element formed as a lever to be operated by the actuating shaft. The lever is mounted on the retaining plate and has a lever axle for reversibly changing location relative to the lock housing. A spring exerts a force being overcome in an emergency-unlocking function permitting adjustment of the retaining plate to allow opening of the lever having been previously brought into a locking position by the actuating shaft, without further operation of the actuating shaft. The actuating shaft is adjustable along its axis by the lever having been unlocked in an emergency.
摘要翻译：用于烤箱的门锁包括锁壳，齿轮传动马达，由齿轮传动马达驱动的致动轴，保持板和形成为由致动轴操作的杆的锁定元件。杠杆安装在保持板上，并具有用于相对于锁壳体可逆地改变位置的杠杆轴。弹簧在紧急解锁功能中施加克服的力，允许调节保持板，以允许先前已经由致动轴进入锁定位置的杠杆的打开，而不需要驱动轴的进一步操作。致动轴可以通过在紧急情况下被解锁的杠杆沿其轴线调节。

15. 发明申请

US20070232090A1 Space transforming land grid array interposers 有权
标题翻译：空间变换土地格栅阵列插值
公开(公告)号：US20070232090A1
公开(公告)日：2007-10-04
申请号：US11395355
申请日：2006-03-31
申请人： Evan Colgan , Paul Coteus , Hubert Harrer , Gareth Hougham , John Magerlein , John Torok
发明人： Evan Colgan , Paul Coteus , Hubert Harrer , Gareth Hougham , John Magerlein , John Torok
IPC分类号： H01R12/00
CPC分类号： H05K1/141 , H01L23/13 , H01L23/49811 , H01L23/49838 , H01L2224/16225 , H01L2224/73253 , H01L2924/09701 , H01L2924/3011 , H01R12/7082 , H01R13/2414 , H05K2201/0367 , H05K2201/049 , H05K2201/10378 , H05K2201/10719
摘要： LGA (land grid array) interposers having variable pitch connectors and distribution wiring to support space transforming I/O interconnections between first level chip modules and second level packaging. Apparatus and methods for constructing high-performance electronic modules (such as processor modules for computer systems) using LGA interposers that provide space transform I/O interconnections between fine pitch I/O contacts on a chip module and coarse pitch contacts on a circuit board.
摘要翻译：具有可变节距连接器和配线的LGA（地面栅格阵列）插入器，以支持第一级芯片模块与第二级封装之间的空间转换I / O互连。使用LGA插入器构建高性能电子模块（例如计算机系统的处理器模块）的装置和方法，其提供芯片模块上的精细间距I / O触点与电路板上的粗略俯仰触点之间的空间变换I / O互连。

16. 发明申请

US20050131664A1 Characterizing input/output models 有权
标题翻译：表征输入/输出模型
公开(公告)号：US20050131664A1
公开(公告)日：2005-06-16
申请号：US10732952
申请日：2003-12-11
申请人： Zhaoqing Chen , Jan Garrett-Hoffman , Hubert Harrer , Stephen White
发明人： Zhaoqing Chen , Jan Garrett-Hoffman , Hubert Harrer , Stephen White
IPC分类号： G06F17/50
CPC分类号： G06F17/5022
摘要： A method, apparatus, system, and signal-bearing medium that in an embodiment select a simulator input fragment, characterize an I/O model using a set of simulator input fragments, create a set of behavioral models based on the characterization and compare the set of behavioral models to the I/O model. In an embodiment, the set of behavioral models is compared to the I/O model by creating simulator input decks that include net topology for the I/O model and the set of behavioral models, simulating the decks, and comparing the output from the simulating.
摘要翻译：一种方法，装置，系统和信号承载介质，其在一个实施例中选择模拟器输入片段，使用一组模拟器输入片段表征I / O模型，基于表征创建一组行为模型并比较该组的行为模型到I / O模型。在一个实施例中，将行为模型集合与I / O模型进行比较，通过创建包括I / O模型的网络拓扑和模拟甲板的行为模型集合的仿真器输入卡，并将来自模拟的。

17. 发明申请

US20050050489A1 Electronic circuit design analysis system 失效
标题翻译：电子电路设计分析系统
公开(公告)号：US20050050489A1
公开(公告)日：2005-03-03
申请号：US10651151
申请日：2003-08-28
申请人： Thaddeus Chen , Zhaoqing Chen , Hubert Harrer , Jan Hoffman , Susan Karwoski , Joonsuk Park , Stephen White , John Zack
发明人： Thaddeus Chen , Zhaoqing Chen , Hubert Harrer , Jan Hoffman , Susan Karwoski , Joonsuk Park , Stephen White , John Zack
IPC分类号： G06F17/50
CPC分类号： G06F17/5022
摘要： A method, apparatus and program product generate package files that are separately stored and selectively combined to generate a net file suited for system simulation and analysis. Selective combination of the package files using respective reference connections of each package enables focused and efficient modeling of design performance characteristics.
摘要翻译：方法，装置和程序产品生成分开存储并选择性组合的包文件，以生成适合于系统仿真和分析的网文件。使用每个包的相应参考连接选择性组合包文件可以对设计性能特征进行集中和高效的建模。

18. 发明授权

US08989532B2 Integrated circuit package connected to an optical data transmission medium using a coolant 有权
标题翻译：使用冷却剂连接到光学数据传输介质的集成电路封装
公开(公告)号：US08989532B2
公开(公告)日：2015-03-24
申请号：US13312583
申请日：2011-12-06
申请人： Harry Barowski , Thomas Brunschwiler , Roger F. Dangel , Hubert Harrer , Andreas Huber , Norbert M. Meier , Bruno Michel , Tim Niggemeier , Stephan Paredes , Jochen Supper , Jonas R. Weiss
发明人： Harry Barowski , Thomas Brunschwiler , Roger F. Dangel , Hubert Harrer , Andreas Huber , Norbert M. Meier , Bruno Michel , Tim Niggemeier , Stephan Paredes , Jochen Supper , Jonas R. Weiss
IPC分类号： G02B6/12 , G02B6/43 , G02B6/122
CPC分类号： G02B6/43 , G02B6/12002 , G02B6/122
摘要： An integrated circuit coupling device includes an integrated circuit package; and an optical data transmission medium connected to the integrated circuit package, and comprising a movable coolant, adapted to remove heat from the integrated circuit package, in operation.
摘要翻译：集成电路耦合器件包括集成电路封装; 以及连接到集成电路封装的光学数据传输介质，并且包括适于在操作中从集成电路封装件移除热量的可移动冷却剂。

19. 发明授权

US08427833B2 Thermal power plane for integrated circuits 有权
标题翻译：用于集成电路的火力发电平面
公开(公告)号：US08427833B2
公开(公告)日：2013-04-23
申请号：US12914730
申请日：2010-10-28
申请人： Harry Barowski , Thomas Brunschwiler , Hubert Harrer , Andreas Huber , Bruno Michel , Tim Niggemeier , Stephan Paredes , Jochen Supper
发明人： Harry Barowski , Thomas Brunschwiler , Hubert Harrer , Andreas Huber , Bruno Michel , Tim Niggemeier , Stephan Paredes , Jochen Supper
IPC分类号： H05K7/20 , H01L25/00
CPC分类号： H01L23/50 , H01L23/3677 , H01L23/38 , H01L23/473 , H01L23/481 , H01L23/49833 , H01L23/5286 , H01L25/18 , H01L2224/131 , H01L2224/16225 , H01L2224/16227 , H01L2225/06513 , H01L2225/06541 , H01L2225/06589 , H01L2924/09701 , Y10T29/49002 , Y10T29/49155 , H01L2924/014
摘要： A mechanism is provided for a thermal power plane that delivers power and constitutes minimal thermal resistance. The mechanism comprises a processor layer coupled, via a first set of coupling devices, to a signaling and input/output (I/O) layer and a power delivery layer coupled, via a second set of coupling devices, to the processor layer. In the mechanism, the power delivery layer is dedicated to only delivering power and does not provide data communication signals to the elements of the mechanism. In the mechanism, the power delivery layer comprises a plurality of conductors, a plurality of insulating materials, one or more ground planes, and a plurality of through laminate vias. In the mechanism, the signaling and input/output (I/O) layer is dedicated to only transmitting the data communication signals to and receiving the data communications signals from the processor layer and does not provide power to the elements of the processor layer.
摘要翻译：提供了一种用于传递功率并构成最小热阻的火力发电平面的机构。该机构包括经由第一组耦合装置耦合到经由第二组耦合装置耦合到处理器层的信令和输入/输出（I / O）层和电力输送层的处理器层。在该机构中，功率传递层专用于仅传递功率，并且不向机构的元件提供数据通信信号。在该机构中，电力输送层包括多个导体，多个绝缘材料，一个或多个接地平面以及多个通过层压体的通孔。在该机制中，信令和输入/输出（I / O）层专用于仅向数据通信信号发送数据通信信号并从处理器层接收数据通信信号，并且不向处理器层的元件供电。

20. 发明授权

US08253234B2 Optimized semiconductor packaging in a three-dimensional stack 有权
标题翻译：在三维堆叠中优化半导体封装
公开(公告)号：US08253234B2
公开(公告)日：2012-08-28
申请号：US12914644
申请日：2010-10-28
申请人： Harry Barowski , Thomas Brunschwiler , Hubert Harrer , Andreas Huber , Bruno Michel , Tim Niggemeier , Stephan Paredes , Jochen Supper
发明人： Harry Barowski , Thomas Brunschwiler , Hubert Harrer , Andreas Huber , Bruno Michel , Tim Niggemeier , Stephan Paredes , Jochen Supper
IPC分类号： H01L23/52
CPC分类号： H01L25/0657 , H01L25/105 , H01L25/16 , H01L2225/06513 , H01L2225/06589 , H01L2225/1052 , H01L2225/1088 , H01L2924/0002 , H01L2924/09701 , Y10T29/41 , H01L2924/00
摘要： A mechanism is provided for optimizing semiconductor packing in a three-dimensional (3D) very-large-scale integration (VLSI) device. The 3D VLSI device comprises a processor layer coupled, via a first set of coupling devices, to at least one signaling and input/output (I/O) layer. The 3D VLSI device further comprises a power delivery layer coupled, via a second set of coupling devices, to the processor layer. In the 3D VLSI device the power delivery layer is dedicated to only delivering power and does not provide data communication signals to the elements of the three-dimensional VLSI device, and the at least one signaling and input/output (I/O) layer is dedicated to only transmitting the data communication signals to and receiving the data communications signals from the processor layer and does not provide power to the elements of the processor layer.
摘要翻译：提供了一种用于优化三维（3D）超大规模集成（VLSI）器件中的半导体封装的机制。 3D VLSI设备包括经由第一组耦合设备耦合到至少一个信令和输入/输出（I / O）层的处理器层。 3D VLSI设备还包括经由第二组耦合设备耦合到处理器层的功率传递层。在3D VLSI设备中，功率传递层专用于仅传递功率，并且不向三维VLSI设备的元件提供数据通信信号，并且至少一个信令和输入/输出（I / O）层是专用于仅向数据通信信号发送数据通信信号并从处理器层接收数据通信信号，并且不向处理器层的元件供电。

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