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11. 发明授权

US5164340A Structure and method for contacts in CMOS devices 失效
标题翻译： CMOS器件中的接触结构和方法
公开(公告)号：US5164340A
公开(公告)日：1992-11-17
申请号：US719791
申请日：1991-06-24
申请人： Fusen Chen , Frank R. Bryant , Girish Dixit
发明人： Fusen Chen , Frank R. Bryant , Girish Dixit
IPC分类号： H01L21/28 , H01L21/3205 , H01L21/768
CPC分类号： H01L21/76802 , Y10S148/133
摘要： The method for fabrication of openings in semiconductor devices to improve metal step coverage includes forming an active region over a substrate. A metal oxide layer is then formed over the source/drain region. An insulating layer is formed over the metal oxide layer. A photoresist layer is formed over the insulating layer, and patterned to form an opening, exposing a portion of the insulating. The insulating layer is then etched to expose a portion of the metal oxide layer. The photoresist layer is removed and the insulating layer is reflowed so as to form rounded corners at the opening of the insulating layer. The exposed portion of the metal oxide layer is removed to expose a portion of the active region.

12. 发明授权

US06883894B2 Printhead with looped gate transistor structures 有权
标题翻译：带环形栅晶体管结构的打印头
公开(公告)号：US06883894B2
公开(公告)日：2005-04-26
申请号：US09813087
申请日：2001-03-19
申请人： Frank R. Bryant , Joseph M. Torgerson , Angela White Bakkom
发明人： Frank R. Bryant , Joseph M. Torgerson , Angela White Bakkom
IPC分类号： B41J2/05 , B41J2/14 , B41J2/16 , B41J2/175 , B41J2/015
CPC分类号： B41J2/17556 , B41J2/14016 , B41J2/1601 , B41J2/1628 , B41J2/1629 , B41J2/1631 , B41J2/1646 , B41J2202/13
摘要： An integrated circuit is formed on a substrate. The integrated circuit includes a transistor formed in the substrate. The transistor has a gate that forms at least one closed-loop. The integrated circuit also includes an ejection element that is coupled to the transistor wherein the ejection element is disposed over the substrate without an intervening field oxide layer.
摘要翻译：在基板上形成集成电路。集成电路包括形成在衬底中的晶体管。晶体管具有形成至少一个闭环的栅极。集成电路还包括耦合到晶体管的喷射元件，其中喷射元件设置在衬底上，而没有中间场氧化物层。

13. 发明授权

US06610555B1 Selectively doped electrostatic discharge layer for an integrated circuit sensor 有权
标题翻译：用于集成电路传感器的选择性掺杂静电放电层
公开(公告)号：US06610555B1
公开(公告)日：2003-08-26
申请号：US09724847
申请日：2000-11-28
申请人： Frank R. Bryant , Danielle A. Thomas
发明人： Frank R. Bryant , Danielle A. Thomas
IPC分类号： H01L2100
CPC分类号： G06K9/00053 , Y10S438/931 , Y10S438/953 , Y10S438/958
摘要： A structure and method for creating an integrated circuit passivation structure including, a circuit, a dielectric, and metal plates over which an insulating layer is disposed that electrically isolates the circuit, and a discharge layer that is deposited to form the passivation structure that protects the circuit from electrostatic discharges caused by, e.g., a finger, is disclosed. The discharge layer additionally contains dopants selectively deposited to increase electrostatic discharge carrying capacity while maintaining overall sensing resolution.
摘要翻译：一种用于产生集成电路钝化结构的结构和方法，该集成电路钝化结构包括：电路，电介质和金属板，在该绝缘层上设置电绝缘电路的绝缘层，以及沉积以形成钝化结构的放电层，公开了由例如手指引起的静电放电的电路。放电层还包含选择性沉积的掺杂剂以增加静电放电承载能力，同时保持总感测分辨率。

14. 发明授权

US5956615A Method of forming a metal contact to landing pad structure in an integrated circuit 失效
标题翻译：在集成电路中形成与接地焊盘结构的金属接触的方法
公开(公告)号：US5956615A
公开(公告)日：1999-09-21
申请号：US362655
申请日：1994-12-22
申请人： Loi N. Nguyen , Frank R. Bryant
发明人： Loi N. Nguyen , Frank R. Bryant
IPC分类号： H01L21/28 , H01L21/285 , H01L21/768 , H01L21/8239 , H01L23/485 , H01L23/522 , H01L23/528 , H01L27/02 , H01L21/44
CPC分类号： H01L21/28 , H01L21/28525 , H01L21/76895 , H01L23/485 , H01L23/5226 , H01L23/5283 , H01L27/0248 , H01L27/1052 , H01L2924/0002
摘要： A method is provided for forming an improved landing pad of a semiconductor integrated circuit, and an integrated circuit formed according to the same. A first opening is formed through a first dielectric layer to expose a portion of a diffused region. A landing pad is formed over the first dielectric layer and in the opening. The landing pad preferably comprises a doped polysilicon layer disposed in the first opening and over a portion of the first dielectric layer. The landing pad will provide for smaller geometries and meet stringent design rules such as that for contact space to gate. A second dielectric layer having an opening therethrough is formed over the landing pad having an opening therethrough exposing a portion of the landing pad. A conductive contact, such as aluminum, is formed in the contact opening. The conductive contact will electrically connect with the diffused region through the landing pad. Misalignment of the conductive contact opening over the landing pad may be tolerated without invading design rules. Additionally, the landing pad will enhance planarization to provide for better step coverage of the metal contact in the second opening.
摘要翻译：提供一种用于形成半导体集成电路的改进的着陆焊盘的方法，以及根据该集成电路形成的集成电路。通过第一介电层形成第一开口以暴露扩散区域的一部分。在第一介电层上和开口中形成着陆垫。着陆垫优选地包括设置在第一开口中并在第一介电层的一部分上方的掺杂多晶硅层。着陆垫将提供较小的几何形状，并符合严格的设计规则，例如接触空间到门。具有穿过其中的开口的第二电介质层形成在着陆焊盘上，具有通过其暴露出一部分着陆焊盘的开口。在接触开口中形成诸如铝的导电接触。导电触点将通过着陆焊盘与扩散区域电连接。可以容忍在着陆垫上的导电接触开口的不对准，而不会侵入设计规则。另外，着陆垫将增强平面化以提供第二开口中的金属接触件的更好的台阶覆盖。

15. 发明授权

US5909636A Method of forming a landing pad structure in an integrated circuit 失效
标题翻译：在集成电路中形成着陆焊盘结构的方法
公开(公告)号：US5909636A
公开(公告)日：1999-06-01
申请号：US802811
申请日：1997-02-18
申请人： Loi N. Nguyen , Frank R. Bryant , Artur P. Balasinski
发明人： Loi N. Nguyen , Frank R. Bryant , Artur P. Balasinski
IPC分类号： H01L21/28 , H01L21/285 , H01L21/3205 , H01L21/768 , H01L23/52 , H01L21/44
CPC分类号： H01L21/28525 , H01L2924/14
摘要： A method is provided for forming an improved landing pad of a semiconductor integrated circuit, and an integrated circuit formed according to the same. A first opening is formed through a first dielectric layer to expose a portion of a diffused region. A dual polysilicon landing pad is formed in the first opening and on a portion of the first dielectric layer adjacent the first opening. The dual landing pad is preferably formed from two polysilicon landing pads with an oxide formed in between a portion of the two polysilicon layers and over the first polysilicon layer. This landing pad will enhance the planarization of the wafer at this stage of the manufacturing and tolerate misalignment of subsequently formed metal contacts without invading design rules.
摘要翻译：提供一种用于形成半导体集成电路的改进的着陆焊盘的方法，以及根据该集成电路形成的集成电路。通过第一介电层形成第一开口以暴露扩散区域的一部分。在第一开口中以及与第一开口相邻的第一电介质层的一部分上形成双重多晶硅着陆焊盘。双层焊盘优选由两个多晶硅着陆焊盘形成，其中氧化物形成在两个多晶硅层的一部分之间并在第一多晶硅层上方。该着陆垫将在制造的这个阶段增强晶片的平面化，并且容许随后形成的金属触点的未对准而不会侵入设计规则。

16. 发明授权

US5702979A Method of forming a landing pad structure in an integrated circuit 失效
标题翻译：在集成电路中形成着陆焊盘结构的方法
公开(公告)号：US5702979A
公开(公告)日：1997-12-30
申请号：US361760
申请日：1994-12-22
申请人： Tsiu C. Chan , Frank R. Bryant , Loi N. Nguyen
发明人： Tsiu C. Chan , Frank R. Bryant , Loi N. Nguyen
IPC分类号： H01L21/28 , H01L21/285 , H01L21/3205 , H01L21/768 , H01L21/8239 , H01L23/485 , H01L23/52 , H01L23/522 , H01L23/528 , H01L27/02 , H01L21/44
CPC分类号： H01L21/28 , H01L21/28525 , H01L21/76895 , H01L23/485 , H01L23/5226 , H01L23/5283 , H01L27/0248 , H01L27/1052 , H01L2924/0002
摘要： A method is provided for forming an improved landing pad of a semiconductor integrated circuit, and an integrated circuit formed according to the same. A first opening is formed through a first dielectric layer to expose a portion of a diffused region. A first polysilicon landing pad is formed over the first dielectric layer and in the opening. This landing pad will provide for smaller geometries and meet stringent design rules such as that for contact space to gate. A dielectric pocket is formed over the polysilicon landing pad over the active region. A second conductive landing pad is formed over the polysilicon landing pad and the dielectric pocket. A second dielectric layer is formed over the landing pad having a second opening therethrough exposing a portion of the landing pad. A conductive contact, such as aluminum, is formed in the second contact opening. The conductive contact will electrically connect with the diffused region through the landing pad. Misalignment of the conductrive contact opening over the landing pad may be tolerated without invading design rules. The landing pad and the dielectric pocket will enhance planarization to provide for better step coverage of the metal contact in the second opening.
摘要翻译：提供一种用于形成半导体集成电路的改进的着陆焊盘的方法，以及根据该集成电路形成的集成电路。通过第一介电层形成第一开口以暴露扩散区域的一部分。在第一介电层上和开口中形成第一多晶硅着陆焊盘。该着陆垫将提供更小的几何形状，并满足严格的设计规则，例如接触空间到门。在有源区上方的多晶硅着陆垫上形成电介质袋。在多晶硅着陆焊盘和电介质槽上方形成第二导电焊盘。第二电介质层形成在着陆焊盘上，具有通过其暴露出一部分着陆焊盘的第二开口。在第二接触开口中形成诸如铝的导电接触。导电触点将通过着陆焊盘与扩散区域电连接。可以容忍在着陆垫上的导电触头开口的不对准，而不会侵入设计规则。着陆垫和电介质袋将增强平面化，以提供第二开口中的金属接触件的更好的台阶覆盖。

17. 发明授权

US5448091A Method of making contact alignment for nonvolatile memory devices 失效
标题翻译：非易失性存储器件接触对准方法
公开(公告)号：US5448091A
公开(公告)日：1995-09-05
申请号：US307475
申请日：1994-09-16
申请人： Frank R. Bryant , Tsiu C. Chan
发明人： Frank R. Bryant , Tsiu C. Chan
IPC分类号： G11C17/00 , H01L21/768 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792 , H01L29/68
CPC分类号： H01L21/76802 , H01L27/115 , Y10S257/90
摘要： A layout and fabrication technique for EPROMs and similar devices includes a preferred technique for partially self-aligning bit line contacts. In addition, a self-aligned, buried Vss line is provided which is in contact with the substrate for its entire length. This provides a highly conductive Vss line, allowing the size of such line to be diminished. The use of a buried Vss contact line and a partially self-aligned bit line contact contributes to a device layout having minimum cell sizes for a given feature size.
摘要翻译： EPROM和类似器件的布局和制造技术包括用于部分自对准位线触点的优选技术。另外，提供了自对准埋置的Vss线，其与衬底的整个长度接触。这提供了高导电性Vss线，允许这种线的尺寸减小。使用埋入的Vss接触线和部分自对准位线接触有助于针对给定特征尺寸具有最小单元尺寸的器件布局。

18. 发明授权

US5426065A Method of making transistor devices in an SRAM cell 失效
标题翻译：在SRAM单元中制造晶体管器件的方法
公开(公告)号：US5426065A
公开(公告)日：1995-06-20
申请号：US159462
申请日：1993-11-30
申请人： Tsiu C. Chan , Frank R. Bryant
发明人： Tsiu C. Chan , Frank R. Bryant
IPC分类号： H01L21/336 , H01L21/8244 , H01L27/10 , H01L27/11 , H01L29/78 , H01L21/8229
CPC分类号： H01L27/11 , Y10S148/163
摘要： An SRAM memory cell having first and second transfer gate transistors. The first transfer gate transistor includes a first source/drain connected to a bit line and the second transfer gate transistor has a first source/drain connected to a complement bit line. Each transfer gate transistor has a gate connected to a word line. The SRAM memory cell also includes first and second pull-down transistors configured as a storage latch. The first pull-down transistor has a first source/drain connected to a second source/drain of said first transfer gate transistor; the second pull-down transistor has a first source/drain connected to a second source/drain of said second transfer gate transistor. Both first and second pull-down transistors have a second source/drain connected to a power supply voltage node. The first and second transfer gate transistors each include a gate oxide layer having a first thickness, and the first and second pull-down transistors each include a gate oxide layer having a second thickness, wherein and the first thickness is different from the second thickness.
摘要翻译：一种具有第一和第二传输门晶体管的SRAM存储单元。第一传输门晶体管包括连接到位线的第一源极/漏极，第二传输门晶体管具有连接到补码位线的第一源极/漏极。每个传输门晶体管具有连接到字线的栅极。 SRAM存储单元还包括被配置为存储锁存器的第一和第二下拉晶体管。第一下拉晶体管具有连接到所述第一传输栅极晶体管的第二源极/漏极的第一源极/漏极; 所述第二下拉晶体管具有连接到所述第二传输栅极晶体管的第二源极/漏极的第一源极/漏极。第一和第二下拉晶体管都具有连接到电源电压节点的第二源极/漏极。第一和第二传输门晶体管各自包括具有第一厚度的栅极氧化物层，并且第一和第二下拉晶体管各自包括具有第二厚度的栅极氧化物层，其中第一厚度不同于第二厚度。

19. 发明授权

US5376571A Method of making contact alignment for nonvolatile memory devices 失效
标题翻译：非易失性存储器件接触对准方法
公开(公告)号：US5376571A
公开(公告)日：1994-12-27
申请号：US118843
申请日：1993-09-10
申请人： Frank R. Bryant , Tsiu C. Chan
发明人： Frank R. Bryant , Tsiu C. Chan
IPC分类号： G11C17/00 , H01L21/768 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792 , H01L21/441
CPC分类号： H01L21/76802 , H01L27/115 , Y10S257/90
摘要： A layout and fabrication technique for EPROMs and similar devices includes a preferred technique for partially self-aligning bit line contacts. In addition, a self-aligned, buried Vss line is provided which is in contact with the substrate for its entire length. This provides a highly conductive Vss line, allowing the size of such line to be diminished. The use of a buried Vss contact line and a partially self-aligned bit line contact contributes to a device layout having minimum cell sizes for a given feature size.
摘要翻译： EPROM和类似器件的布局和制造技术包括用于部分自对准位线触点的优选技术。另外，提供了自对准埋置的Vss线，其与衬底的整个长度接触。这提供了高导电性Vss线，允许这种线的尺寸减小。使用埋入的Vss接触线和部分自对准位线接触有助于针对给定特征尺寸具有最小单元尺寸的器件布局。

20. 发明授权

US5344790A Making integrated circuit transistor having drain junction offset 失效
标题翻译：制造具有漏极结偏移的集成电路晶体管
公开(公告)号：US5344790A
公开(公告)日：1994-09-06
申请号：US114754
申请日：1993-08-31
申请人： Frank R. Bryant , Robert L. Hodges
发明人： Frank R. Bryant , Robert L. Hodges
IPC分类号： H01L21/336 , H01L29/786
CPC分类号： H01L29/66757 , H01L29/78624
摘要： A method for fabricating an integrated circuit transistor begins with forming a gate electrode over an insulating layer grown on a conductive layer. Sidewall spacers are formed alongside vertical edges of the gate electrode and a mask is applied to a drain region. A relatively fast-diffusing dopant is then implanted into a source region in the conductive layer. Thereafter, the mask is removed and the drain region is implanted with a relatively slow-diffusing dopant. Finally, the conductive layer is annealed, causing the relatively fast-diffusing dopant to diffuse beneath the source sidewall spacer to a location approximately beneath the vertical edge of the source side of the gate electrode, and causing the relatively slow-diffusing dopant to extend beneath the drain sidewall spacer a lesser distance, so that the drain junction is laterally spaced from underneath the gate electrode. Due to the difference in diffusion rates between the relatively slow-diffusing dopant and the relatively fast-diffusing dopant, a transistor having a drain junction offset is formed.
摘要翻译：制造集成电路晶体管的方法开始于在导电层上生长的绝缘层上形成栅电极。侧壁间隔物沿着栅电极的垂直边缘形成，并且掩模施加到漏极区域。然后将相对快速扩散的掺杂剂注入到导电层中的源极区域中。此后，去除掩模，并用较慢扩散的掺杂剂注入漏区。最后，导电层被退火，导致相对快速扩散的掺杂剂在源侧壁间隔物下方扩散到栅电极的源极侧的垂直边缘附近的位置，并使相对较慢的扩散掺杂剂在下面延伸漏极侧壁间隔较小的距离，使得漏极结与栅极下方横向间隔开。由于相对较慢扩散的掺杂剂和相对快速扩散的掺杂剂之间的扩散速率的差异，形成具有漏极结偏移的晶体管。

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