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11. 发明授权

US5438224A Integrated circuit package having a face-to-face IC chip arrangement 失效
标题翻译：具有面对面IC芯片布置的集成电路封装
公开(公告)号：US5438224A
公开(公告)日：1995-08-01
申请号：US159910
申请日：1993-12-01
申请人： Marc V. Papageorge , Bruce J. Freyman , Frank J. Juskey , John R. Thome
发明人： Marc V. Papageorge , Bruce J. Freyman , Frank J. Juskey , John R. Thome
IPC分类号： H01L23/495 , H01L23/498 , H01L25/065 , H01L23/02 , H01L23/12 , H01L23/44 , H01L29/41
CPC分类号： H01L23/4985 , H01L23/49575 , H01L25/0657 , H01L2224/16 , H01L2225/06517 , H01L2225/06555 , H01L2225/06572 , H01L2225/06579 , H01L2924/01079 , H01L2924/15311
摘要： An integrated circuit package includes a stacked integrated circuit chip arrangement (140) placed on a circuit substrate. The stacked IC chip arrangement includes a first IC chip (110) and a second IC chip (120), each having an array of terminals (116, 126) and being positioned in a face-to-face manner. An interposed substrate (130) is positioned between the first IC chip (110) and the second IC chip (120) such that circuitry disposed on the interposed substrate (130) provides electrical connection among the arrays of terminals of the first IC chip (110) and the second IC chip (120) and external circuitry.
摘要翻译：集成电路封装包括放置在电路基板上的堆叠集成电路芯片布置（140）。堆叠的IC芯片装置包括第一IC芯片（110）和第二IC芯片（120），每个芯片具有端子阵列（116,126）并且以面对面的方式定位。插入的基板（130）位于第一IC芯片（110）和第二IC芯片（120）之间，使得设置在插入的基板（130）上的电路在第一IC芯片（110）的端子阵列之间提供电连接）和第二IC芯片（120）和外部电路。

12. 发明授权

US5296738A Moisture relief for chip carrier 失效
标题翻译：芯片载体防潮
公开(公告)号：US5296738A
公开(公告)日：1994-03-22
申请号：US927774
申请日：1992-08-10
申请人： Bruce J. Freyman , Frank J. Juskey , Barry M. Miles
发明人： Bruce J. Freyman , Frank J. Juskey , Barry M. Miles
IPC分类号： H01L21/56 , H01L21/58 , H01L23/00 , H01L23/13 , H01L23/28 , H01L23/31 , H05K13/02
CPC分类号： H01L23/564 , H01L23/13 , H01L23/3121 , H01L24/29 , H01L24/83 , H01L2224/2919 , H01L2224/32225 , H01L2224/48091 , H01L2224/48137 , H01L2224/48227 , H01L2224/4823 , H01L2224/49171 , H01L2224/73265 , H01L2224/8319 , H01L2224/8385 , H01L24/48 , H01L24/49 , H01L2924/00014 , H01L2924/01005 , H01L2924/01013 , H01L2924/01015 , H01L2924/01047 , H01L2924/01082 , H01L2924/014 , H01L2924/0665 , H01L2924/07802 , H01L2924/14 , H01L2924/15151 , H01L2924/181
摘要： An integrated circuit package (10) comprises a semiconductor die (14) having a top surface and a bottom surface, and a substrate (16) for receiving the semiconductor die. The substrate should have an aperture(s) (18) below the semiconductor die for providing moisture relief during temperature excursions. An adhesive (20) applied to the substrate allows for mounting the semiconductor die to the substrate. Then, the semiconductor die is wirebonded to the substrate. Finally, an encapsulant (12) for sealing the top surface of the semiconductor die is formed over the semiconductor die and portions of the substrate.
摘要翻译：集成电路封装（10）包括具有顶表面和底表面的半导体管芯（14）和用于接收半导体管芯的衬底（16）。衬底应在半导体管芯下方具有一个（18）的孔口，用于在温度偏移期间提供湿气释放。施加到基板上的粘合剂（20）允许将半导体管芯安装到基板上。然后，半导体管芯与引线接合。最后，在半导体管芯和衬底的部分之上形成用于密封半导体管芯的顶表面的密封剂（12）。

13. 发明授权

US08487435B2 Sheet-molded chip-scale package 有权
标题翻译：片状模制芯片级封装
公开(公告)号：US08487435B2
公开(公告)日：2013-07-16
申请号：US13252083
申请日：2011-10-03
申请人： Frank J. Juskey , Paul Bantz , Otto Berger
发明人： Frank J. Juskey , Paul Bantz , Otto Berger
IPC分类号： H01L29/40 , H01L21/44
CPC分类号： H01L23/5389 , H01L21/561 , H01L21/568 , H01L23/3114 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/13 , H01L24/19 , H01L24/20 , H01L24/93 , H01L25/16 , H01L2223/6677 , H01L2224/038 , H01L2224/0383 , H01L2224/0391 , H01L2224/0401 , H01L2224/05073 , H01L2224/05147 , H01L2224/05611 , H01L2224/05647 , H01L2224/119 , H01L2224/12105 , H01L2224/13022 , H01L2224/13023 , H01L2224/13026 , H01L2224/13082 , H01L2224/131 , H01L2224/13111 , H01L2224/13147 , H01L2224/16225 , H01L2224/81815 , H01L2224/93 , H01L2924/01005 , H01L2924/01006 , H01L2924/01029 , H01L2924/01033 , H01L2924/0105 , H01L2924/014 , H01L2924/09701 , H01L2924/14 , H01L2924/181 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/19105 , H01L21/56 , H01L2224/11 , H01L2224/03 , H01L2924/00014 , H01L2924/00
摘要： Embodiments include but are not limited to apparatuses and systems including a microelectronic device including a die having a first surface and a second surface opposite the first surface, a conductive pillar formed on the first surface of the die, and an encapsulant material encasing the die, including covering the first surface, the second surface, and at least a portion of a side surface of the conductive pillar. Methods for making the same also are described.
摘要翻译：实施例包括但不限于包括微电子器件的设备和系统，该微电子器件包括具有第一表面和与第一表面相对的第二表面的管芯，形成在管芯的第一表面上的导电柱和封装管芯的密封剂材料，包括覆盖导电柱的第一表面，第二表面和至少一部分侧表面。也对其制作方法进行了说明。

14. 发明授权

US06507102B2 Printed circuit board with integral heat sink for semiconductor package 有权
公开(公告)号：US06507102B2
公开(公告)日：2003-01-14
申请号：US10006642
申请日：2001-12-05
申请人： Frank J. Juskey , John R. McMillan , Ronald P. Huemoeller
发明人： Frank J. Juskey , John R. McMillan , Ronald P. Huemoeller
IPC分类号： H01L2310
CPC分类号： H05K1/0204 , H01L23/3128 , H01L23/3677 , H01L24/45 , H01L24/48 , H01L2224/32225 , H01L2224/45144 , H01L2224/48091 , H01L2224/48227 , H01L2224/48464 , H01L2224/73265 , H01L2924/00014 , H01L2924/01019 , H01L2924/01078 , H01L2924/01079 , H01L2924/15311 , H05K3/4046 , H05K2201/0355 , H05K2201/10416 , Y10T29/49128 , Y10T29/49155 , H01L2924/00 , H01L2224/05599
摘要： A low-cost printed circuit board for a semiconductor package having the footprint of a ball grid array package has an integral heat sink, or “slug,” for the mounting of one or more semiconductor chips, capable of efficiently conducting away at least five watts from the package in typical applications. It is made by forming an opening through a sheet, or substrate, of B-stage epoxy/fiberglass composite, or “pre-preg,” then inserting a slug of a thermally conductive material having the same size and shape as the opening into the opening. The slug-containing composite is sandwiched between two thin layers of a conductive metal, preferably copper, and the resulting sandwich is simultaneously pressed and heated between the platen of a heated press. The heat and pressure forces the resin to the surface of the composite and into the space between the slug and the walls of the composite, where it solidifies, bonding the edges of the slug to the substrate within the opening and adhering the conductive layers to the upper and lower surfaces of the substrate. The resulting laminate can thereafter be processed as a convention printed circuit board to incorporate conventional circuit board features, e.g., circuit traces, wire bonding pads, solder ball mounting lands, and via holes.

15. 发明申请

US20120080768A1 SHEET-MOLDED CHIP-SCALE PACKAGE 有权
标题翻译：片材成型包装
公开(公告)号：US20120080768A1
公开(公告)日：2012-04-05
申请号：US13252083
申请日：2011-10-03
申请人： Frank J. Juskey , Paul Bantz , Otto Berger
发明人： Frank J. Juskey , Paul Bantz , Otto Berger
IPC分类号： H01L29/02 , H01L21/56 , H01L23/498
CPC分类号： H01L23/5389 , H01L21/561 , H01L21/568 , H01L23/3114 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/13 , H01L24/19 , H01L24/20 , H01L24/93 , H01L25/16 , H01L2223/6677 , H01L2224/038 , H01L2224/0383 , H01L2224/0391 , H01L2224/0401 , H01L2224/05073 , H01L2224/05147 , H01L2224/05611 , H01L2224/05647 , H01L2224/119 , H01L2224/12105 , H01L2224/13022 , H01L2224/13023 , H01L2224/13026 , H01L2224/13082 , H01L2224/131 , H01L2224/13111 , H01L2224/13147 , H01L2224/16225 , H01L2224/81815 , H01L2224/93 , H01L2924/01005 , H01L2924/01006 , H01L2924/01029 , H01L2924/01033 , H01L2924/0105 , H01L2924/014 , H01L2924/09701 , H01L2924/14 , H01L2924/181 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/19105 , H01L21/56 , H01L2224/11 , H01L2224/03 , H01L2924/00014 , H01L2924/00
摘要： Embodiments include but are not limited to apparatuses and systems including a microelectronic device including a die having a first surface and a second surface opposite the first surface, a conductive pillar formed on the first surface of the die, and an encapsulant material encasing the die, including covering the first surface, the second surface, and at least a portion of a side surface of the conductive pillar. Methods for making the same also are described.
摘要翻译：实施例包括但不限于包括微电子器件的设备和系统，该微电子器件包括具有第一表面和与第一表面相对的第二表面的管芯，形成在管芯的第一表面上的导电柱和封装管芯的密封剂材料，包括覆盖导电柱的第一表面，第二表面和至少一部分侧表面。也对其制作方法进行了说明。

16. 发明授权

US07489021B2 Lead frame with included passive devices 有权
标题翻译：引线框架包括无源器件
公开(公告)号：US07489021B2
公开(公告)日：2009-02-10
申请号：US10563172
申请日：2004-02-17
申请人： Frank J. Juskey , Daniel K. Lau , Lawrence R. Thompson
发明人： Frank J. Juskey , Daniel K. Lau , Lawrence R. Thompson
IPC分类号： H01L23/495 , H01L23/34 , H01L21/00
CPC分类号： H01L23/3107 , H01L23/49541 , H01L23/49589 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/50 , H01L2224/45124 , H01L2224/45144 , H01L2224/48091 , H01L2224/48247 , H01L2224/48463 , H01L2224/48465 , H01L2224/4911 , H01L2224/49171 , H01L2224/85207 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H01L2924/181 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/19105 , H01L2924/19107 , Y10S257/924 , H01L2924/00014 , H01L2924/00 , H01L2924/00012
摘要： An semiconductor device package (10) includes a semiconductor device (die) (12) and passive devices (14) electrically connected to a common lead frame (17). The lead frame (17) is formed from a stamped and/or etched metallic structure and includes a plurality of conductive leads (16) and a plurality of interposers (20). The passive devices (14) are electrically connected to the interposers (20), and I/O pads (22) on the die (12) are electrically connected to the leads (16). The die (12), passive devices (14), and lead frame (17) are encapsulated in a molding compound (28), which forms a package body (30). Bottom surfaces (38) of the leads (16) are exposed at a bottom face (34) of the package (10).
摘要翻译：半导体器件封装（10）包括电连接到公共引线框架（17）的半导体器件（管芯）（12）和无源器件（14）。引线框架（17）由冲压和/或蚀刻的金属结构形成，并且包括多个导电引线（16）和多个插入件（20）。无源器件（14）电连接到插入件（20），并且管芯（12）上的I / O焊盘（22）电连接到引线（16）。模具（12），无源器件（14）和引线框架（17）被封装在形成封装主体（30）的模制化合物（28）中。引线（16）的底表面（38）在封装（10）的底面（34）处露出。

17. 发明申请

US20080036034A1 Lead Frame with Included Passive Devices 有权
标题翻译：包括被动设备的引线框架
公开(公告)号：US20080036034A1
公开(公告)日：2008-02-14
申请号：US10563172
申请日：2004-02-17
申请人： Frank J. Juskey , Daniel K. Lau , Lawrence R. Thompson
发明人： Frank J. Juskey , Daniel K. Lau , Lawrence R. Thompson
IPC分类号： H01L23/495 , H01L21/00 , H01L29/00
CPC分类号： H01L23/3107 , H01L23/49541 , H01L23/49589 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/50 , H01L2224/45124 , H01L2224/45144 , H01L2224/48091 , H01L2224/48247 , H01L2224/48463 , H01L2224/48465 , H01L2224/4911 , H01L2224/49171 , H01L2224/85207 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H01L2924/181 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/19105 , H01L2924/19107 , Y10S257/924 , H01L2924/00014 , H01L2924/00 , H01L2924/00012
摘要： An semiconductor device package (10) includes a semiconductor device (die) (12) and passive devices (14) electrically connected to a common lead frame (17). The lead frame (17) is formed from a stamped and/or etched metallic structure and includes a plurality of conductive leads (16) and a plurality of interposers (20). The passive devices (14) are electrically connected the interposers (20), and I/O pads (22) on the die (12) are electrically connected to the leads (16). The die (12), passive devices (14), and lead frame (17) are encapsulated in a molding compound (28), which forms a package body (30). Bottom surfaces (38) of the leads (16) are exposed at a bottom face (34) of the package (10).
摘要翻译：半导体器件封装（10）包括电连接到公共引线框架（17）的半导体器件（管芯）（12）和无源器件（14）。引线框架（17）由冲压和/或蚀刻的金属结构形成，并且包括多个导电引线（16）和多个插入件（20）。无源器件（14）与插入件（20）电连接，并且管芯（12）上的I / O焊盘（22）电连接到引线（16）。模具（12），无源器件（14）和引线框架（17）被封装在形成封装主体（30）的模制化合物（28）中。引线（16）的底表面（38）在封装（10）的底面（34）处露出。

18. 发明授权

US06337228B1 Low-cost printed circuit board with integral heat sink for semiconductor package 有权
标题翻译：低成本印刷电路板，集成散热片用于半导体封装
公开(公告)号：US06337228B1
公开(公告)日：2002-01-08
申请号：US09310660
申请日：1999-05-12
申请人： Frank J. Juskey , John R. McMillan , Ronald P. Huemoeller
发明人： Frank J. Juskey , John R. McMillan , Ronald P. Huemoeller
IPC分类号： H01L2144
CPC分类号： H05K1/0204 , H01L23/3128 , H01L23/3677 , H01L24/45 , H01L24/48 , H01L2224/32225 , H01L2224/45144 , H01L2224/48091 , H01L2224/48227 , H01L2224/48464 , H01L2224/73265 , H01L2924/00014 , H01L2924/01019 , H01L2924/01078 , H01L2924/01079 , H01L2924/15311 , H05K3/4046 , H05K2201/0355 , H05K2201/10416 , Y10T29/49128 , Y10T29/49155 , H01L2924/00 , H01L2224/05599
摘要： A low-cost printed circuit board for a semiconductor package having the footprint of a ball grid array package has an integral heat sink, or “slug,” for the mounting of one or more semiconductor chips, capable of efficiently conducting away at least five watts from the package in typical applications. It is made by forming an opening through a sheet, or substrate, of B-stage epoxy/fiberglass composite, or “pre-preg,” then inserting a slug of a thermally conductive material having the same size and shape as the opening into the opening. The slug-containing composite is sandwiched between two thin layers of a conductive metal, preferably copper, and the resulting sandwich is simultaneously pressed and heated between the platen of a heated press. The heat and pressure forces the resin to the surface of the composite and into the space between the slug and the walls of the composite, where it solidifies, bonding the edges of the slug to the substrate within the opening and adhering the conductive layers to the upper and lower surfaces of the substrate. The resulting laminate can thereafter be processed as a convention printed circuit board to incorporate conventional circuit board features, e.g., circuit traces, wire bonding pads, solder ball mounting lands, and via holes.
摘要翻译：用于具有球栅阵列封装的占位面积的半导体封装的低成本印刷电路板具有用于安装一个或多个半导体芯片的整体散热器或“块状”，能够有效地将至少5瓦从典型应用中的包装。通过形成通过B阶环氧树脂/玻璃纤维复合材料的片材或基底的开口或“预浸渍”形成开口，然后将具有与开口相同的尺寸和形状的导热材料块塞入开放含块状复合材料夹在导电金属（优选铜）的两个薄层之间，并且所得到的夹层同时被压制并在加热压机的压板之间加热。热和压力迫使树脂到复合材料的表面并进入组合体和组合物的壁之间的空间中，在该空间中它凝固，将块状物的边缘粘合到开口内的衬底上，并将导电层粘附到衬底的上表面和下表面。此后，所得到的层压板可以作为常规印刷电路板加工，以结合常规的电路板特征，例如电路迹线，引线接合焊盘，焊球安装焊盘和通孔。

19. 发明授权

US5336931A Anchoring method for flow formed integrated circuit covers 失效
标题翻译：流量形成集成电路盖的锚固方法
公开(公告)号：US5336931A
公开(公告)日：1994-08-09
申请号：US115971
申请日：1993-09-03
申请人： Frank J. Juskey , Douglas W. Hendricks
发明人： Frank J. Juskey , Douglas W. Hendricks
IPC分类号： H01L23/24 , H01L23/31 , H01L23/28 , H01L23/29
CPC分类号： H01L23/3121 , H01L23/24 , H01L24/97 , H01L2224/32225 , H01L2224/45124 , H01L2224/45144 , H01L2224/48091 , H01L2224/48227 , H01L2224/48472 , H01L2224/49171 , H01L2224/73265 , H01L2224/97 , H01L24/45 , H01L24/48 , H01L24/49 , H01L2924/01013 , H01L2924/01027 , H01L2924/01038 , H01L2924/01039 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/09701 , H01L2924/12042 , H01L2924/14 , H01L2924/181 , H01L2924/18301
摘要： A flow formed encapsulated integrated circuit package (100) includes a printed circuit substrate (160) having upper and lower opposed surfaces and one or more anchor holes (150). The one or more anchor holes (150) have an upper aperture in the upper surface and a lower aperture in the lower surface. One or more integrated circuit die (130) are electrically and mechanically attached to the upper surface of the substrate (160). In addition, a solder resist mask (190) is attached to the lower surface of the substrate which covers the aperture of the one or more anchor holes (150). Flow formed material (110) is formed around the integrated circuit die (130) so as to encapsulate the one or more integrated circuits (150), the flow formed material (110) covering at a least a portion of the upper surface of the printed circuit substrate (160) and extending substantially into the anchor hole (150).
摘要翻译：流形成的封装集成电路封装（100）包括具有上下相对表面和一个或多个锚定孔（150）的印刷电路基板（160）。一个或多个锚定孔（150）在上表面具有上孔，在下表面具有下孔。一个或多个集成电路管芯（130）电和机械地附接到衬底（160）的上表面。此外，阻焊掩模（190）附着到覆盖一个或多个锚定孔（150）的孔的基板的下表面。形成流体的材料（110）围绕集成电路管芯（130）形成，以封装一个或多个集成电路（150），流动形成的材料（110）覆盖在印刷的上表面的至少一部分电路基板（160）并且基本上延伸到锚定孔（150）中。

20. 发明授权

US5019673A Flip-chip package for integrated circuits 失效
标题翻译：用于集成电路的倒装芯片封装
公开(公告)号：US5019673A
公开(公告)日：1991-05-28
申请号：US570751
申请日：1990-08-22
申请人： Frank J. Juskey , Barry M. Miles , Marc V. Papageorge
发明人： Frank J. Juskey , Barry M. Miles , Marc V. Papageorge
IPC分类号： H01L23/28 , H01L21/60 , H01L23/12 , H01L23/485
CPC分类号： H01L24/10 , H01L24/13 , H01L24/81 , H01L2224/13 , H01L2224/13099 , H01L2224/16237 , H01L2224/81801 , H01L2924/01005 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01087 , H01L2924/014 , H01L2924/14
摘要： A flip-chip package for integrated circuits is provided by over-molding an integrated circuit assembly which includes a flip-chip mounted to a very thin chip carrier. The flip-chip includes an array of bumped pads which fill an array of matching conductive through holes on the chip carrier and securely couple thereto. The chip carrier includes an array of bumped contacts on its back surface which correspond to the bumped pads of the flip-chip. The transfer over molding of the integrated circuit assembly provides a layer of epoxy around the exposed surfaces of the flip-chip providing an environmentally protected and removable integrated circuit package.
摘要翻译：用于集成电路的倒装芯片封装通过覆盖模制集成电路组件来提供，集成电路组件包括安装到非常薄的芯片载体上的倒装芯片。倒装芯片包括一组凸起的焊盘，其填充芯片载体上匹配的导电通孔的阵列并且牢固地耦接到芯片载体上。芯片载体在其后表面上包括与倒装芯片的凸起焊盘相对应的凸起触点阵列。集成电路组件的成型转移在倒装芯片的暴露表面周围提供环氧树脂层，其提供环境保护和可移除的集成电路封装。

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