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11. 发明授权

US5691920A Method and system for performance monitoring of dispatch unit efficiency in a processing system 失效
标题翻译：处理系统调度单位效率性能监测方法及系统
公开(公告)号：US5691920A
公开(公告)日：1997-11-25
申请号：US538070
申请日：1995-10-02
申请人： Frank Eliot Levine , Charles Philip Roth , Edward Hugh Welbon
发明人： Frank Eliot Levine , Charles Philip Roth , Edward Hugh Welbon
IPC分类号： G06F11/34 , G06F15/00
CPC分类号： G06F11/3409 , G06F11/348 , G06F11/3423 , G06F11/3476 , G06F2201/86 , G06F2201/88 , G06F2201/885
摘要： A method and system for determining the efficiency of operation of a dispatch unit in a processing system, the processing system including at least one performance monitor counter (PMC) and at least one monitor mode control register (MMCR) to configure the operations of the at least one PMC, includes counting a number of instructions dispatched by the dispatch unit during a predetermined sampling period, counting a number of times a predetermined number of instructions are dispatched by the dispatch unit per cycle during the predetermined sampling period, and determining the efficiency of the dispatch unit according to the counted number of instructions and the counted number of times the predetermined number of instructions are dispatched by the dispatch unit.
摘要翻译：一种用于确定处理系统中的调度单元的操作效率的方法和系统，所述处理系统包括至少一个性能监视计数器（PMC）和至少一个监视模式控制寄存器（MMCR），以配置所述at 至少一个PMC包括在预定采样周期内对由调度单元发送的指令数进行计数，对在预定采样周期期间每个周期由调度单元调度预定数量的指令的次数进行计数，并且确定所述调度单元根据所计数的指令数和由所述调度单元调度所述预定指令数的次数。

12. 发明授权

US06708296B1 Method and system for selecting and distinguishing an event sequence using an effective address in a processing system 失效
标题翻译：用于在处理系统中使用有效地址来选择和区分事件序列的方法和系统
公开(公告)号：US06708296B1
公开(公告)日：2004-03-16
申请号：US08538071
申请日：1995-10-02
申请人： Frank Carl Gover , Frank Eliot Levine , Bret R. Olszewski , Charles Philip Roth , Edward Hugh Welbon , Charles Wright
发明人： Frank Carl Gover , Frank Eliot Levine , Bret R. Olszewski , Charles Philip Roth , Edward Hugh Welbon , Charles Wright
IPC分类号： G06F1300
CPC分类号： G06F11/3466 , G06F11/28 , G06F2201/88
摘要： A method and system for providing a match on a selected event in performance monitoring of a processing system, the processing system including at least one performance monitor counter (PMC) is disclosed. The method and system comprises initializing the at least one PMC and controlling counting in the at least one PMC based upon the nth occurrence of a match to a specified address, where n is grater than or equal to one.
摘要翻译：公开了一种用于在处理系统的性能监视中提供所选事件匹配的方法和系统，所述处理系统包括至少一个性能监视计数器（PMC）。所述方法和系统包括：基于与指定地址匹配的第n次出现，其中n大于或等于1，初始化所述至少一个PMC并控制所述至少一个PMC中的计数。

13. 发明授权

US6085338A CPI infinite and finite analysis 失效
标题翻译： CPI无限有限分析
公开(公告)号：US6085338A
公开(公告)日：2000-07-04
申请号：US766143
申请日：1996-12-17
申请人： Frank Eliot Levine , Roy Stuart Moore , Charles Philip Roth , Edward Hugh Welbon
发明人： Frank Eliot Levine , Roy Stuart Moore , Charles Philip Roth , Edward Hugh Welbon
IPC分类号： G06F11/34 , G06F11/00
CPC分类号： G06F11/3409 , G06F11/348 , G06F2201/81 , G06F2201/86 , G06F2201/88 , G06F2201/885
摘要： A performance monitor implementing a plurality of counters counts several events to provide an instruction fetch bandwidth analysis, a cycles per instruction (CPI) infinite and finite analysis, an operand fetch bandwidth analysis, an instruction parallelism analysis, and a trailing edge analysis. Such analyses are performed on the performance of a data processing system in order that the designer may develop an improved processor architecture.
摘要翻译：实现多个计数器的性能监视器计数几个事件以提供指令获取带宽分析，每个指令的周期（CPI）无限和有限分析，操作数获取带宽分析，指令并行性分析和后沿分析。对数据处理系统的性能执行这样的分析，以便设计者可以开发改进的处理器架构。

14. 发明授权

US5991708A Performance monitor and method for performance monitoring within a data processing system 失效
标题翻译：性能监视器和数据处理系统中的性能监视方法
公开(公告)号：US5991708A
公开(公告)日：1999-11-23
申请号：US888802
申请日：1997-07-07
申请人： Frank Eliot Levine , Charles Philip Roth , Edward Hugh Welbon
发明人： Frank Eliot Levine , Charles Philip Roth , Edward Hugh Welbon
IPC分类号： G06F11/34 , G06F11/25
CPC分类号： G06F11/3409 , G06F11/348 , G06F2201/81 , G06F2201/86 , G06F2201/88 , G06F2201/885
摘要： The present invention provides a performance monitor including a threshold indicator, a granularity indicator, an event detector, and an event counter. The threshold indicator indicates a number of threshold increments, which each correspond to a number of occurrences of a first event. The granularity indicator indicates the number of occurrences of the first event corresponding to each of the threshold increments indicated by the threshold indicator. The granularity indicator has at least a first state and a second state such that the granularity indicator indicates that a first number of occurrences of the first event correspond to a threshold increment in the first state and that a different second number of occurrences of the first event correspond to a threshold increment in the second state. In response to a number of occurrences of the first event detected by the event detector during a selected interval exceeding the number of occurrences indicated by the threshold value and the granularity indicator, the event counter is incremented. In one embodiment, each occurrence of the first event corresponds to a processor clock cycle and the selected interval is defined as the duration of a memory access.
摘要翻译：本发明提供一种包括阈值指示符，粒度指示符，事件检测器和事件计数器的性能监视器。阈值指示符指示阈值增量的数量，其中每一个阈值增量对应于第一事件的发生次数。粒度指示符指示与由阈值指示符指示的每个阈值增量相对应的第一事件的发生次数。粒度指示符至少具有第一状态和第二状态，使得粒度指示符指示第一事件的第一次出现次数对应于第一状态中的阈值增量，并且第一事件的不同次数出现对应于第二状态的阈值增量。响应于在所选择的间隔期间由事件检测器检测到的第一事件的数量超过由阈值和粒度指示符指示的出现次数的事件计数器增加。在一个实施例中，第一事件的每次出现对应于处理器时钟周期，并且所选择的间隔被定义为存储器访问的持续时间。

15. 发明授权

US5987598A Method and system for tracking instruction progress within a data processing system 失效
标题翻译：跟踪数据处理系统内的指令进度的方法和系统
公开(公告)号：US5987598A
公开(公告)日：1999-11-16
申请号：US888798
申请日：1997-07-07
申请人： Frank Eliot Levine , Charles Philip Roth , Edward Hugh Welbon
发明人： Frank Eliot Levine , Charles Philip Roth , Edward Hugh Welbon
IPC分类号： G06F11/30 , G06F11/34 , G06F11/00
CPC分类号： G06F11/3055 , G06F11/302 , G06F11/3024 , G06F11/3466 , G06F11/3476
摘要： A processor and method for tracking instruction execution within a processor are described. The processor includes at least one execution unit that executes instructions and an instruction status indicator that dynamically indicates a status of an instruction during processing. The instruction status indicator has at least a first state to which the instruction status indicator is set in order to indicate that execution of the instruction is stalled. In one embodiment, the processor further includes a reason code indicator associated with the instruction status indicator that specifies an event occurrence that caused the indicated instruction status. In another embodiment, the processor further includes a history buffer that indicates the number of processor cycles that the status indicated by the instruction status indicator has remained unchanged.
摘要翻译：描述了用于跟踪处理器内的指令执行的处理器和方法。处理器包括执行指令的至少一个执行单元和在处理期间动态地指示指令的状态的指令状态指示符。指令状态指示符至少具有第一状态，指令状态指示器被设置到第一状态，以指示指令的执行停止。在一个实施例中，处理器还包括与指示导致所指示的指令状态的事件发生相关联的指令状态指示符的原因代码指示符。在另一个实施例中，处理器还包括历史缓冲器，其指示由指令状态指示符指示的状态保持不变的处理器周期数。

16. 发明授权

US5802273A Trailing edge analysis 失效
标题翻译：后期分析
公开(公告)号：US5802273A
公开(公告)日：1998-09-01
申请号：US767662
申请日：1996-12-17
申请人： Frank Eliot Levine , Roy Stuart Moore , Charles Philip Roth , Edward Hugh Welbon
发明人： Frank Eliot Levine , Roy Stuart Moore , Charles Philip Roth , Edward Hugh Welbon
IPC分类号： G06F11/34
CPC分类号： G06F11/3409 , G06F2201/81 , G06F2201/86 , G06F2201/88 , G06F2201/885
摘要： A performance monitor implementing a plurality of counters counts several events to provide an instruction fetch bandwidth analysis, a cycles per instruction (CPI) infinite and finite analysis, an operand fetch bandwidth analysis, an instruction parallelism analysis, and a trailing edge analysis. Such analyses are performed on the performance of a data processing system in order that the designer may develop an improved processor architecture.
摘要翻译：实现多个计数器的性能监视器计数几个事件以提供指令获取带宽分析，每个指令的周期（CPI）无限和有限分析，操作数获取带宽分析，指令并行性分析和后沿分析。对数据处理系统的性能执行这样的分析，以便设计者可以开发改进的处理器架构。

17. 发明授权

US5797019A Method and system for performance monitoring time lengths of disabled interrupts in a processing system 失效
标题翻译：处理系统中禁用中断的性能监视时间长度的方法和系统
公开(公告)号：US5797019A
公开(公告)日：1998-08-18
申请号：US539023
申请日：1995-10-02
申请人： Frank Eliot Levine , Charles Philip Roth , Edward Hugh Welbon
发明人： Frank Eliot Levine , Charles Philip Roth , Edward Hugh Welbon
IPC分类号： G06F11/34
CPC分类号： G06F11/3419 , G06F11/3409 , G06F11/348 , G06F2201/86 , G06F2201/865 , G06F2201/88 , G06F2201/885
摘要： A method and system for identifying inhibited interrupts in a processor system, the processor system including at least one performance monitor counter (PMC) and at least one monitor mode control register (MMCR) to configure the operations of the at least one PMC, includes initializing the at least one PMC and counting a number of cycles or occurrences with the at least one PMC that exceptions are ignored during a predetermined sampling period. In a second aspect the method and system provides for initializing at least one PMC and counting a number of cycles or occurrences with the at least one PMC that an interrupt is pending during the predetermined sampling period. The counted number of cycles/occurrences assists in identifying potential areas of improving system performance in order to reduce the counted values.
摘要翻译：一种用于识别处理器系统中的禁止中断的方法和系统，所述处理器系统包括至少一个性能监视计数器（PMC）和至少一个监视模式控制寄存器（MMCR）以配置所述至少一个PMC的操作，包括初始化所述至少一个PMC并且计数与所述至少一个PMC的周期数或出现次数，所述异常在预定采样周期期间被忽略。在第二方面，该方法和系统提供初始化至少一个PMC并且计数与所述至少一个PMC的周期数或出现次数，以使得在预定采样周期期间中断待处理。计数的周期/事件数量有助于确定提高系统性能的潜在领域，以减少计数值。

18. 发明授权

US5729726A Method and system for performance monitoring efficiency of branch unit operation in a processing system 失效
标题翻译：在处理系统中分支机构运行的性能监测效率的方法和系统
公开(公告)号：US5729726A
公开(公告)日：1998-03-17
申请号：US538509
申请日：1995-10-02
申请人： Frank Eliot Levine , Charles Philip Roth , Edward Hugh Welbon
发明人： Frank Eliot Levine , Charles Philip Roth , Edward Hugh Welbon
IPC分类号： G06F11/34
CPC分类号： G06F11/3466 , G06F11/3419 , G06F11/348 , G06F2201/86 , G06F2201/88
摘要： A method and system for determining the effectiveness of operation of a branch of a branch unit in a processing system the processing system including at least one performance monitor counter (PMC) and at least one monitor mode control register (MMCR) to configure the operations of the at least one of the PMC, includes accumulating count data during branch unit operation with the at least one during a predetermined sampling period, and determining effectiveness of branch prediction based on the accumulated count data.
摘要翻译：一种用于确定处理系统中分支单元的分支的操作的有效性的方法和系统，所述处理系统包括至少一个性能监视计数器（PMC）和至少一个监视模式控制寄存器（MMCR），以配置所述PMC中的至少一个包括在预定采样周期期间与所述至少一个分支单元操作期间累积计数数据，以及基于所述累积计数数据来确定分支预测的有效性。

19. 发明授权

US5894575A Method and system for initial state determination for instruction trace reconstruction 失效
标题翻译：指令跟踪重构初始状态确定方法和系统
公开(公告)号：US5894575A
公开(公告)日：1999-04-13
申请号：US758196
申请日：1996-11-25
申请人： Frank Eliot Levine , Bradley David McCredie , William John Starke , Edward Hugh Welbon
发明人： Frank Eliot Levine , Bradley David McCredie , William John Starke , Edward Hugh Welbon
IPC分类号： G06F11/36 , H04B17/00
CPC分类号： G06F11/3636
摘要： A method and system for determining an initial architectural state for instruction trace reconstruction. Performance projections for processor systems and memory subsystems are important for a correct understanding of work loads within the system. An instruction trace is generally utilized to determine distribution of instructions, identification of register dependencies, branch path analyses and timing. One well-known technique for reconstructing an instruction trace can be accomplished by monitoring bus traffic to determine instruction addresses, data addresses and data during the trace. However, the initial architectural state (the state of all caches, buffers and registers) must be determined in order to accurately reconstruct an instruction trace. At least one cache within the processor system is divided into two portions, the content of that cache is invalidated and each cache entry thereafter is duplicated within each portion of the divided cache. Upon initiation of an instruction trace, one half of the cache is frozen, preserving the initial state of the system with respect to that cache without requiring the cache to be invalidated and refilled during the instruction trace, so that the initial state may be utilized to reconstruct an instruction trace in combination with the monitored bus traffic.
摘要翻译：一种用于确定指令跟踪重构的初始架构状态的方法和系统。处理器系统和内存子系统的性能预测对于正确了解系统内的工作负载非常重要。通常使用指令轨迹来确定指令的分配，寄存器依赖性的识别，分支路径分析和定时。可以通过监视总线流量来确定跟踪期间的指令地址，数据地址和数据来实现重建指令轨迹的一种众所周知的技术。但是，必须确定初始架构状态（所有高速缓存，缓冲器和寄存器的状态），以便精确地重构指令轨迹。处理器系统内的至少一个高速缓存被分成两部分，该高速缓存的内容被无效，并且之后的每个高速缓存条目在分割高速缓存的每个部分内被复制。在开始指令跟踪时，缓存的一半被冻结，保持系统相对于该高速缓存的初始状态，而不需要在指令跟踪期间使高速缓存无效并重新填充，使得初始状态可被用于结合监控的总线流量重建指令轨迹。

20. 发明授权

US5752062A Method and system for performance monitoring through monitoring an order of processor events during execution in a processing system 失效
标题翻译：通过在处理系统中执行期间监视处理器事件的顺序来进行性能监视的方法和系统
公开(公告)号：US5752062A
公开(公告)日：1998-05-12
申请号：US537645
申请日：1995-10-02
申请人： Frank Carl Gover , Frank Eliot Levine , Edward Hugh Welbon
发明人： Frank Carl Gover , Frank Eliot Levine , Edward Hugh Welbon
IPC分类号： G06F11/34 , G06F11/72
CPC分类号： G06F11/3466 , G06F11/3409 , G06F11/3476 , G06F2201/86 , G06F2201/88 , G06F2201/885
摘要： A method and system for reconstructing a relationship among events in a processing system, the processing system including at least one performance monitor counter (PMC) and at least one monitor mode control register (MMCR) to configure the operations of the at least one PMC, includes controlling a mode of updating the at least one PMC through a bit set within the at least one MMCR, the bit set having a plurality of logic levels. Further included are determining if the bit set is at a first logic level, and placing the at least one PMC in a history mode if the bit set is at the first logic level.
摘要翻译：一种用于重建处理系统中的事件之间的关系的方法和系统，所述处理系统包括至少一个性能监视计数器（PMC）和至少一个监视模式控制寄存器（MMCR），以配置所述至少一个PMC的操作，包括通过在所述至少一个MMCR内设置的位来控制更新所述至少一个PMC的模式，所述位集合具有多个逻辑电平。还包括确定位集合是否处于第一逻辑电平，以及如果位集合处于第一逻辑电平，则将至少一个PMC置于历史模式。

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