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    • 11. 发明申请
    • DATA TRANSFER EQUIPMENT
    • 数据传输设备
    • WO1985005471A1
    • 1985-12-05
    • PCT/JP1985000267
    • 1985-05-15
    • FANUC LTDIKEDA, YoshiakiKUWASAWA, Mitsuru
    • FANUC LTD
    • G05B15/02
    • G06F13/4243G05B19/414G05B2219/33182G06F13/4239
    • The invention transfers serial data sent from a first apparatus (10) onto predetermined bits of predetermined addresses of RAM (300) of a second apparatus (30) for each of the bits. Data transfer equipment transfers each of the bits data in serial data from the first apparatus (10) onto predetermined bits of predetermined addresses of RAM (300) in the second apparatus (30) in synchronism with clock pulses sent from the first apparatus (10), and comprises: a counter (206) that is incremented by said clock pulses; an address generating circuit (210) which generates address of said RAM (300) responding to the output of said counter (206); a bit address generating circuit (211) which generates a bit address to designate a bit position in an address of said RAM (300) responsive to the output of said counter (206); a timing control circuit (209) which generates a timing signal for a read cycle and for a subsequent write cycle responsive to the output of said counter (206) during a period in which an address is being generated by said address generating circuit (210); and a read modify write circuit (214) which replaces data of a bit position designated by a bit address of said bit address generating circuit (211) by a corresponding bit data of serial data sent from the first apparatus (10) among a plurality of bits in parallel data corresponding to the address (210) of said address generating circuit read from said RAM (300) during the read cycle specified by said timing control circuit (209), and which transfers said parallel data that is replaced onto the original address of said RAM during the write cycle specified by said timing control circuit (209), such that individual bits of serial data sent from the first apparatus (10) are transferred to predetermined bits of predetermined addresses of RAM (300) in the second apparatus (30).
    • 14. 发明申请
    • OUTPUT SYSTEM FOR DETERMINING AXIAL SPEED
    • 用于确定轴向速度的输出系统
    • WO1988007229A1
    • 1988-09-22
    • PCT/JP1988000045
    • 1988-01-22
    • FANUC LTDIKEDA, YoshiakiKUWASAWA, Mitsuru
    • FANUC LTD
    • G05B19/405
    • G05B19/416
    • An output system for determining an axial speed for a CNC apparatus which controls the speed depending upon a residual error between the position instruction and the detected position data in order to control positions of the axes. This system comprises means for determining the present speeds of axes from the residual errors, means for determining the present actual speed by combining the present speeds of the axes, and means for producing an output that represents a ratio of the present actual speed to a predetermined maximum speed. An error register stores a residual error (residual quantity) between the position data detected by the position detector and position instructions for the axes from the MPU in the CNC apparatus. A speed instruction is generated from the error register to control the speed. In this case, there exists a predetermined relationship between the residual error and the present speeds of the axes, and this is utilized to derive the present speeds of the axes from the residual errors. When the present speeds of the axes is obtained, the actual speed of the work table can be determined by combining the speeds of the axes. The actual speed thus obtained is converted into an output that represents its ratio to the system's maximum speed which has been set according to a parameter.
    • 18. 发明申请
    • SYSTEM FOR PROCESSING MST FUNCTIONAL INSTRUCTION
    • 处理MST功能指令的系统
    • WO1988010451A1
    • 1988-12-29
    • PCT/JP1988000584
    • 1988-06-14
    • FANUC LTDISOBE, ShinichiIKEDA, Yoshiaki
    • FANUC LTD
    • G05B19/18
    • G05B19/408G05B2219/35252
    • A system for processing MST functional instruction in a numerical control system which consists of a numerical controller (CNC, 10) and a PMC (programmable machine controller, 20). The numerical controller (10) produces strobe signals MF, SF and TF in the logic state opposite to that of completion signals MFIN, SFIN and TFIN. The PMC (20) judges that an instruction is produced when the strobe signal logic becomes opposite to the completion signal that is being produced. When the execution of MST function is finished, the completion signal is rendered in the same logic state as that of the strobe signals MF, SF and TF. When the completion signal becomes the same logic as the strobe signal, the numerical controller (10) determines that the processing of MST function is finished. Therefore, it is determined that the instruction is issued when the completion signals and the strobe signals are different from the respective output signals. Further, when the strobe signals and the completion signals are in the same logic state, it is determined that the processing is finished. Therefore, no cycle is required for confirming the signals, and the processing time is shortened.