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11. 发明申请

US20080256275A1 Multi-Chip Module With Third Dimension Interconnect 审中-公开
标题翻译：具有三维互连的多芯片模块
公开(公告)号：US20080256275A1
公开(公告)日：2008-10-16
申请号：US12049323
申请日：2008-03-15
申请人： Harm Peter Hofstee , Charles Ray Johns , James Allan Kahle
发明人： Harm Peter Hofstee , Charles Ray Johns , James Allan Kahle
IPC分类号： G06F13/00
CPC分类号： G06F9/4862 , G06F15/16 , H04L29/06027 , H04L63/168 , H04L67/10 , H04L67/34
摘要： A computer architecture and programming model for high speed processing over broadband networks are provided. The architecture employs a consistent modular structure, a common computing module and uniform software cells. The common computing module includes a control processor, a plurality of processing units, a plurality of local memories from which the processing units process programs, a direct memory access controller and a shared main memory. A synchronized system and method for the coordinated reading and writing of data to and from the shared main memory by the processing units also are provided. A hardware sandbox structure is provided for security against the corruption of data among the programs being processed by the processing units. The uniform software cells contain both data and applications and are structured for processing by any of the processors of the network. Each software cell is uniquely identified on the network.
摘要翻译：提供了一种用于宽带网络高速处理的计算机体系结构和编程模型。该架构采用一致的模块化结构，通用的计算模块和统一的软件单元。公共计算模块包括控制处理器，多个处理单元，处理单元处理程序的多个本地存储器，直接存储器存取控制器和共享主存储器。还提供了一种用于由处理单元协调地读取和从共享主存储器写入数据的同步系统和方法。提供了一种硬件沙盒结构，用于防止由处理单元处理的程序中的数据损坏的安全性。统一软件单元包含数据和应用程序，并且被构造为由网络的任何处理器进行处理。每个软件单元在网络上唯一标识。

12. 发明申请

US20080235647A1 MODULAR DESIGN METHOD AND APPARATUS 失效
标题翻译：模块化设计方法和装置
公开(公告)号：US20080235647A1
公开(公告)日：2008-09-25
申请号：US12130268
申请日：2008-05-30
申请人： Harm Peter Hofstee , James Allan Kahle , Takeshi Yamazaki
发明人： Harm Peter Hofstee , James Allan Kahle , Takeshi Yamazaki
IPC分类号： G06F17/50
CPC分类号： G06F17/5045
摘要： Disclosed is a procedure or design approach for functional modules that may be used in connection with a multiprocessor integrated circuit chip. The approach includes keeping the dimensions of each module substantially the same and having the bus, power, clock and I/O connection configured the same on all modules. Further requirements for ease of use are to generalize the capability of each module as much as possible and to decentralize functions such as testing to be primarily performed within each module. The use of such considerations or rules substantially eases the design of a given type of custom chips, and based upon an initial chip design greatly facilitates the design of further custom chips, similar in application, but subsequent to the successful completion of the initial chip. The standardization modules and replication of the modules on a given chip also reduces physical verification time in initial chip design as well as redesign time of the initial chip when requirements for chip capability are redefined or otherwise changed. Any subsequent or further custom chips can include more or less of specific modules based upon already established parameters.
摘要翻译：公开了可以与多处理器集成电路芯片结合使用的功能模块的过程或设计方法。该方法包括保持每个模块的尺寸基本相同，并使总线，电源，时钟和I / O连接在所有模块上配置相同。对易用性的进一步要求是尽可能地推广每个模块的能力，并将诸如测试之类的功能分散在每个模块内主要执行。这种考虑或规则的使用大大简化了给定类型的定制芯片的设计，并且基于初始的芯片设计极大地促进了其他定制芯片的设计，其应用类似，但是在初始芯片的成功完成之后。给定芯片上的标准化模块和模块的复制也减少了初始芯片设计中的物理验证时间，以及在重新定义或改变芯片能力要求时初始芯片的重新设计时间。任何后续或进一步的定制芯片可以基于已经建立的参数包括或多或少的特定模块。

13. 发明授权

US07398482B2 Modular design method and apparatus 失效
标题翻译：模块化设计方法和装置
公开(公告)号：US07398482B2
公开(公告)日：2008-07-08
申请号：US11191580
申请日：2005-07-28
申请人： Harm Peter Hofstee , James Allan Kahle , Takeshi Yamazaki
发明人： Harm Peter Hofstee , James Allan Kahle , Takeshi Yamazaki
IPC分类号： G06F17/50
CPC分类号： G06F17/5045
摘要： Disclosed is a procedure or design approach for functional modules that may be used in connection with a multiprocessor integrated circuit chip. The approach includes keeping the dimensions of each module substantially the same and having the bus, power, clock and I/O connection configured the same on all modules. Further requirements for ease of use are to generalize the capability of each module as much as possible and to decentralize functions such as testing to be primarily performed within each module. The use of such considerations or rules substantially eases the design of a given type of custom chips, and based upon an initial chip design greatly facilitates the design of further custom chips, similar in application, but subsequent to the successful completion of the initial chip. The standardization modules and replication of the modules on a given chip also reduces physical verification time in initial chip design as well as redesign time of the initial chip when requirements for chip capability are redefined or otherwise changed. Any subsequent or further custom chips can include more or less of specific modules based upon already established parameters.
摘要翻译：公开了可以与多处理器集成电路芯片结合使用的功能模块的过程或设计方法。该方法包括保持每个模块的尺寸基本相同，并使总线，电源，时钟和I / O连接在所有模块上配置相同。对易用性的进一步要求是尽可能地推广每个模块的能力，并将诸如测试之类的功能分散在每个模块内主要执行。这种考虑或规则的使用大大简化了给定类型的定制芯片的设计，并且基于初始的芯片设计极大地促进了其他定制芯片的设计，其应用类似，但是在初始芯片的成功完成之后。给定芯片上的标准化模块和模块的复制也减少了初始芯片设计中的物理验证时间，以及在重新定义或改变芯片能力要求时初始芯片的重新设计时间。任何后续或进一步的定制芯片可以基于已经建立的参数包括或多或少的特定模块。

14. 发明授权

US07093080B2 Method and apparatus for coherent memory structure of heterogeneous processor systems 失效
标题翻译：异构处理器系统的相干存储器结构的方法和装置
公开(公告)号：US07093080B2
公开(公告)日：2006-08-15
申请号：US10682386
申请日：2003-10-09
申请人： Michael Norman Day , Harm Peter Hofstee , Charles Ray Johns , James Allan Kahle , David J. Shippy , Thuong Quang Truong
发明人： Michael Norman Day , Harm Peter Hofstee , Charles Ray Johns , James Allan Kahle , David J. Shippy , Thuong Quang Truong
IPC分类号： G06F12/00
CPC分类号： G06F12/0835
摘要： Disclosed is a coherent cache system that operates in conjunction with non-homogeneous processing units. A set of processing units of a first configuration has conventional cache and directly accesses common or shared system physical and virtual address memory through the use of a conventional MMU (Memory Management Unit). Additional processors of a different configuration and/or other devices that need to access system memory are configured to store accessed data in compatible caches. Each of the caches is compatible with a given protocol coherent memory management bus interspersed between the caches and the system memory.
摘要翻译：公开了与非均匀处理单元结合操作的一致的缓存系统。一组第一配置的处理单元具有常规高速缓存，并且通过使用常规MMU（存储器管理单元）直接访问公用或共享系统物理和虚拟地址存储器。需要访问系统存储器的不同配置和/或其他设备的其他处理器被配置为将访问的数据存储在兼容的高速缓存中。每个缓存与散列在高速缓存和系统存储器之间的给定协议相干存储器管理总线兼容。

15. 发明授权

US06785841B2 Processor with redundant logic 失效
标题翻译：具有冗余逻辑的处理器
公开(公告)号：US06785841B2
公开(公告)日：2004-08-31
申请号：US09734371
申请日：2000-12-14
申请人： Chekib Akrout , Harm Peter Hofstee , James Allan Kahle
发明人： Chekib Akrout , Harm Peter Hofstee , James Allan Kahle
IPC分类号： G06F1100
CPC分类号： G06F11/2043 , G06F11/2028 , G06F11/2038
摘要： A system including a central processor and a plurality of attached processors all on a single die are disclosed. Each of the attached processors is preferably functionally equivalent to each of the other attached processors. The system further includes at least one redundant processor that is connectable to the central processor. The redundant processor may be substantially equivalent to each of the attached processors. Upon detecting a failure in one of the attached processors, the system is configured to disable the non-functional processor and enable the redundant processor. The attached processors may be connected to a memory interface unit via a parallel bus or a pipelined bus in which each attached processor is connected to a stage of the pipelined bus. The attached processors may each include a load/store unit and logic suitable for performing a mathematical function.
摘要翻译：公开了一种包括中央处理器和多个附属处理器的系统，其全部在单个管芯上。每个连接的处理器优选地在功能上等同于其他附加处理器中的每一个。该系统还包括可连接到中央处理器的至少一个冗余处理器。冗余处理器可以基本上等同于附接的每个处理器。一旦检测到所附加的处理器之一的故障，则该系统被配置为禁用非功能处理器并启用冗余处理器。连接的处理器可以经由并行总线或流水线总线连接到存储器接口单元，其中每个连接的处理器连接到流水线总线的级。附加的处理器可以各自包括适于执行数学功能的加载/存储单元和逻辑。

16. 发明授权

US09703516B2 Configurable interface controller 有权
公开(公告)号：US09703516B2
公开(公告)日：2017-07-11
申请号：US13269583
申请日：2011-10-08
申请人： Harm Peter Hofstee , Charles Ray Johns , James Allan Kahle
发明人： Harm Peter Hofstee , Charles Ray Johns , James Allan Kahle
IPC分类号： G06F3/00 , G06F3/14 , G09G5/14
CPC分类号： G06F3/1423 , G06F3/1454 , G09G5/14 , G09G2360/121 , G09G2370/04
摘要： A flexible input/output controller logic interfaces with existing input/output controllers (IOC's) in order to configure the amount of data sent to and received from the IOC's. The flexible I/O interface receives data from a component at a rate determined by the particular component. The flexible I/O interface then feeds the received data to a traditional I/O controller at a rate suitable for the I/O controller. Thus, the interface to the individual I/O controllers is maintained. The flexible I/O logic balances bandwidth between a plurality of individual I/O controllers in order to better utilize the overall system I/O bandwidth. In one embodiment, the I/O configuration managed by the flexible I/O logic is determined during system-build, while in another embodiment, the I/O configuration is set during system initialization.

17. 发明申请

US20120030386A1 Configurable Interface Controller 审中-公开
标题翻译：可配置接口控制器
公开(公告)号：US20120030386A1
公开(公告)日：2012-02-02
申请号：US13269583
申请日：2011-10-08
申请人： Harm Peter Hofstee , Charles Ray Johns , James Allan Kahle
发明人： Harm Peter Hofstee , Charles Ray Johns , James Allan Kahle
IPC分类号： G06F13/36
CPC分类号： G06F3/1423 , G06F3/1454 , G09G5/14 , G09G2360/121 , G09G2370/04
摘要： A flexible input/output controller logic interfaces with existing input/output controllers (IOC's) in order to configure the amount of data sent to and received from the IOC's. The flexible I/O interface receives data from a component at a rate determined by the particular component. The flexible I/O interface then feeds the received data to a traditional I/O controller at a rate suitable for the I/O controller. Thus, the interface to the individual I/O controllers is maintained. The flexible I/O logic balances bandwidth between a plurality of individual I/O controllers in order to better utilize the overall system I/O bandwidth. In one embodiment, the I/O configuration managed by the flexible I/O logic is determined during system-build, while in another embodiment, the I/O configuration is set during system initialization.
摘要翻译：灵活的输入/输出控制器逻辑与现有的输入/输出控制器（IOC）进行接口，以便配置向国际奥委会发送和接收的数据量。灵活的I / O接口以特定组件确定的速率从组件接收数据。然后，灵活的I / O接口以适合于I / O控制器的速率将接收的数据馈送到传统的I / O控制器。因此，保持与各个I / O控制器的接口。灵活的I / O逻辑平衡多个独立I / O控制器之间的带宽，以便更好地利用整个系统I / O带宽。在一个实施例中，在系统构建期间确定由灵活I / O逻辑管理的I / O配置，而在另一实施例中，在系统初始化期间设置I / O配置。

18. 发明授权

US07689783B2 System and method for sharing memory by heterogeneous processors 有权
标题翻译：异构处理器共享内存的系统和方法
公开(公告)号：US07689783B2
公开(公告)日：2010-03-30
申请号：US11840284
申请日：2007-08-17
申请人： Harm Peter Hofstee , Charles Ray Johns , James Allan Kahle
发明人： Harm Peter Hofstee , Charles Ray Johns , James Allan Kahle
IPC分类号： G06F12/06
CPC分类号： G06F12/0284 , G06F13/1652
摘要： A system for sharing memory by heterogeneous processors, each of which is adapted to process its own instruction set, is presented. A common bus is used to couple the common memory to the various processors. In one embodiment, a cache for more than one of the processors is stored in the shared memory. In another embodiment, some of the processors include a local memory area that is mapped to the shared memory pool. In yet another embodiment, local memory included on one or more of the processors is partially shared so that some of the local memory is mapped to the shared memory area, while remaining memory in the local memory is private to the particular processor.
摘要翻译：提出了一种用于通过异构处理器共享存储器的系统，每个处理器适于处理其自己的指令集。公共总线用于将公共存储器耦合到各种处理器。在一个实施例中，用于多于一个处理器的高速缓存存储在共享存储器中。在另一个实施例中，一些处理器包括映射到共享存储器池的本地存储器区域。在另一个实施例中，包括在一个或多个处理器中的本地存储器被部分地共享，使得一些本地存储器被映射到共享存储器区域，而本地存储器中的剩余存储器对于特定处理器是专用的。

19. 发明授权

US07650491B2 Method and system for controlled distribution of application code and content data within a computer network 有权
标题翻译：计算机网络内应用程序代码和内容数据受控分配的方法和系统
公开(公告)号：US07650491B2
公开(公告)日：2010-01-19
申请号：US12325192
申请日：2008-11-29
申请人： David John Craft , Pradeep K. Dubey , Harm Peter Hofstee , James Allan Kahle
发明人： David John Craft , Pradeep K. Dubey , Harm Peter Hofstee , James Allan Kahle
IPC分类号： H04L9/00 , G06F13/00
CPC分类号： H04L63/0823 , H04L63/126 , H04L63/145 , H04L2463/102
摘要： A secure communication methodology is presented. The client device is configured to download application code and/or content data from a server operated by a service provider. Embedded within the client is a client private key, a client serial number, and a copy of a server public key. The client forms a request, which includes the client serial number, encrypts the request with the server public key, and sends the download request to the server. The server decrypts the request with the server's private key and authenticates the client. The received client serial number is used to search for a client public key that corresponds to the embedded client private key. The server encrypts its response, which includes the requested information, with the client public key of the requesting client, and only the private key in the requesting client can be used to decrypt the information downloaded from the server.
摘要翻译：提出了一种安全的通信方法。客户端设备被配置为从由服务提供商操作的服务器下载应用代码和/或内容数据。嵌入在客户端中的是客户端私钥，客户端序列号和服务器公钥的副本。客户端形成请求，其中包括客户端序列号，使用服务器公钥加密请求，并将下载请求发送到服务器。服务器使用服务器的私钥对请求进行解密，并对客户端进行身份验证。接收到的客户端序列号用于搜索与嵌入式客户端私钥对应的客户端公钥。服务器将其响应（包括所请求的信息）与请求客户端的客户端公钥加密，并且只有请求客户端中的私钥可以用于解密从服务器下载的信息。

20. 发明授权

US07603703B2 Method and system for controlled distribution of application code and content data within a computer network 失效
公开(公告)号：US07603703B2
公开(公告)日：2009-10-13
申请号：US09833342
申请日：2001-04-12
申请人： David John Craft , Pradeep K. Dubey , Harm Peter Hofstee , James Allan Kahle
发明人： David John Craft , Pradeep K. Dubey , Harm Peter Hofstee , James Allan Kahle
IPC分类号： H04K1/00 , H04L9/00
CPC分类号： H04L63/0823 , H04L63/126 , H04L63/145 , H04L2463/102
摘要： A secure communication methodology is presented. The client device is configured to download application code and/or content data from a server operated by a service provider. Embedded within the client is a client private key, a client serial number, and a copy of a server public key. The client forms a request, which includes the client serial number, encrypts the request with the server public key, and sends the download request to the server. The server decrypts the request with the server's private key and authenticates the client. The received client serial number is used to search for a client public key that corresponds to the embedded client private key. The server encrypts its response, which includes the requested information, with the client public key of the requesting client, and only the private key in the requesting client can be used to decrypt the information downloaded from the server.

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