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11. 发明授权

US06344993B1 Dual floating gate EEPROM cell array with steering gates shared by adjacent cells 失效
标题翻译：具有由相邻单元共享的转向门的双浮栅EEPROM单元阵列
公开(公告)号：US06344993B1
公开(公告)日：2002-02-05
申请号：US09904945
申请日：2001-07-13
申请人： Eliyahou Harari , Daniel C. Guterman , George Samachisa , Jack H. Yuan
发明人： Eliyahou Harari , Daniel C. Guterman , George Samachisa , Jack H. Yuan
IPC分类号： G11C1604
CPC分类号： G11C16/0475 , G11C11/5621 , G11C11/5628 , G11C11/5635 , G11C11/5642 , G11C16/0458 , G11C2211/5612 , H01L27/115
摘要： An EEPROM system having an array of memory cells that individually include two floating gates, bit line source and drain diffusions extending along columns, steering gates also extending along columns and select gates forming word lines along rows of floating gates. The dual gate cell increases the density of data that can be stored. Rather than providing a separate steering gate for each column of floating gates, an individual steering gate is shared by two adjacent columns of floating gates that have a diffusion between them. The steering gate is thus shared by two floating gates of different but adjacent memory cells. In one array embodiment, the floating gates are formed on the surface of the substrate, where the added width of the steering gates makes them easier to form, removes them as a limitation upon scaling the array smaller, require fewer electrical contacts along their length because of increased conductance, are easier to contact, and reduces the number of conductive traces that are needed to connect with them. In arrays that erase the floating gates to the select gates, rather than to the substrate, the wider steering gates advantageously uncouple the diffusions they cover from the select gates. This use of a single steering gate for two floating gates also allows the floating gates, in another embodiment, to be formed on side walls of trenches in the substrate with the common steering gate between them, to further increase the density of data that can be stored. Multiple bits of data can also be stored on each floating gate.
摘要翻译：具有存储单元阵列的EEPROM系统，其独立地包括两个浮动栅极，沿列延伸的位线源极和漏极扩散，还沿着列延伸的转向栅极以及沿着浮动栅极行沿着形成字线的选择栅极。双门单元增加了可以存储的数据的密度。不是为每列浮动栅栏提供单独的转向门，而是由两个相邻的悬浮门之间共享一个单独的转向门，这两个浮动门在它们之间具有扩散。因此，转向门由不同但相邻的存储单元的两个浮动门共享。在一个阵列实施例中，浮动栅极形成在基板的表面上，其中增加的转向门的宽度使得它们更容易形成，作为对阵列的缩小的限制，将它们移除，因为它们的尺寸较小，因此需要更少的沿着它们的长度的电触点，因为增加电导，更容易接触，并减少与它们连接所需的导电迹线的数量。在将浮动栅极擦除到选择栅极而不是衬底的阵列中，较宽的转向栅极有利地使其从选择栅极覆盖的扩散分离。单个转向门用于两个浮动栅极的这种使用也允许浮动栅极在另一个实施例中形成在衬底中的沟槽的侧壁上，其间具有公共转向栅极，以进一步增加数据的密度存储。多个数据位也可以存储在每个浮动门上。

12. 发明授权

US6151248A Dual floating gate EEPROM cell array with steering gates shared by adjacent cells 有权
公开(公告)号：US6151248A
公开(公告)日：2000-11-21
申请号：US343328
申请日：1999-06-30
申请人： Eliyahou Harari , Daniel C. Guterman , George Samachisa , Jack H. Yuan
发明人： Eliyahou Harari , Daniel C. Guterman , George Samachisa , Jack H. Yuan
IPC分类号： G11C11/56 , G11C16/04 , H01L27/115
CPC分类号： G11C16/0475 , G11C11/5621 , G11C11/5628 , G11C11/5635 , G11C11/5642 , G11C16/0458 , H01L27/115 , G11C2211/5612
摘要： An EEPROM system having an array of memory cells that individually include two floating gates, bit line source and drain diffusions extending along columns, steering gates also extending along columns and select gates forming word lines along rows of floating gates. The dual gate cell increases the density of data that can be stored. Rather than providing a separate steering gate for each column of floating gates, an individual steering gate is shared by two adjacent columns of floating gates that have a diffusion between them. The steering gate is thus shared by two floating gates of different but adjacent memory cells. In one array embodiment, the floating gates are formed on the surface of the substrate, where the added width of the steering gates makes them easier to form, removes them as a limitation upon scaling the array smaller, require fewer electrical contacts along their length because of increased conductance, are easier to contact, and reduces the number of conductive traces that are needed to connect with them. In arrays that erase the floating gates to the select gates, rather than to the substrate, the wider steering gates advantageously uncouple the diffusions they cover from the select gates. This use of a single steering gate for two floating gates also allows the floating gates, in another embodiment, to be formed on side walls of trenches in the substrate with the common steering gate between them, to further increase the density of data that can be stored. Multiple bits of data can also be stored on each floating gate.

13. 发明授权

US5965913A Dense vertical programmable read only memory cell structures and processes for making them 失效
公开(公告)号：US5965913A
公开(公告)日：1999-10-12
申请号：US844002
申请日：1997-04-18
申请人： Jack H. Yuan , Gheorghe Samachisa , Daniel C. Guterman , Eliyahou Harari
发明人： Jack H. Yuan , Gheorghe Samachisa , Daniel C. Guterman , Eliyahou Harari
IPC分类号： H01L27/04 , H01L21/822 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792 , H01L29/78 , H01L27/01 , H01L29/10 , H01L29/40
CPC分类号： H01L27/11521 , H01L21/28273 , H01L27/115 , H01L27/11519
摘要： A memory array of PROM, EPROM or EEPROM cells has each cell formed in a trench of a thick oxide layer deposited on a silicon substrate, in a manner that a significant portion of opposing areas of the floating gate and control gate of each cell which provide capacitive coupling between them are formed vertically. This allows the density of the array to be increased since the amount of semiconductor substrate area occupied by each cell is decreased without having to sacrifice the amount or quality of the capacitive coupling. Further, a technique of forming capacitive coupling between the floating gate and an erase gate in a flash EEPROM array cell with improved endurance is disclosed.

14. 发明授权

US5512505A Method of making dense vertical programmable read only memory cell structure 失效
标题翻译：制作密集垂直可编程只读存储单元结构的方法
公开(公告)号：US5512505A
公开(公告)日：1996-04-30
申请号：US423218
申请日：1995-04-17
申请人： Jack H. Yuan , Gheorghe Samachisa , Daniel C. Guterman , Eliyahou Harari
发明人： Jack H. Yuan , Gheorghe Samachisa , Daniel C. Guterman , Eliyahou Harari
IPC分类号： H01L21/8247 , H01L27/115
CPC分类号： H01L27/11521 , H01L27/115 , Y10S148/05
摘要： A memory array of PROM, EPROM or EEPROM cells has each cell formed in a trench of a thick oxide layer deposited on a silicon substrate, in a manner that a significant portion of opposing areas of the floating gate and control gate of each cell which provide capacitive coupling between them are formed vertically. This allows the density of the array to be increased since the amount of semiconductor substrate area occupied by each cell is decreased without having to sacrifice the amount or quality of the capacitive coupling. Further, a technique of forming capacitive coupling between the floating gate and an erase gate in a flash EEPROM array cell with improved endurance is disclosed.
摘要翻译： PROM，EPROM或EEPROM单元的存储器阵列具有以沉积在硅衬底上的厚氧化物层的沟槽中的每个单元的方式使每个单元的浮置栅极和控制栅极的相对区域的大部分提供它们之间的电容耦合垂直形成。这允许阵列的密度增加，因为每个单元占用的半导体衬底面积的数量减少，而不必牺牲电容耦合的量或质量。此外，公开了一种在具有改善的耐久性的快闪EEPROM阵列单元中在浮动栅极和擦除栅极之间形成电容耦合的技术。

15. 发明授权

US5847425A Dense vertical programmable read only memory cell structures and processes for making them 失效
公开(公告)号：US5847425A
公开(公告)日：1998-12-08
申请号：US341411
申请日：1994-11-17
申请人： Jack H. Yuan , Gheorghe Samachisa , Daniel C. Guterman , Eliyahou Harari
发明人： Jack H. Yuan , Gheorghe Samachisa , Daniel C. Guterman , Eliyahou Harari
IPC分类号： H01L27/04 , H01L21/822 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L27/11521 , H01L21/28273 , H01L27/115 , H01L27/11519
摘要： A memory array of PROM, EPROM or EEPROM cells has each cell formed in a trench of a thick oxide layer deposited on a silicon substrate, in a manner that a significant portion of opposing areas of the floating gate and control gate of each cell which provide capacitive coupling between them are formed vertically. This allows the density of the array to be increased since the amount of semiconductor substrate area occupied by each cell is decreased without having to sacrifice the amount or quality of the capacitive coupling. Further, a technique of forming capacitive coupling between the floating gate and an erase gate in a flash EEPROM array cell with improved endurance is disclosed.

16. 发明授权

US5380672A Dense vertical programmable read only memory cell structures and processes for making them 失效
标题翻译：密集的垂直可编程只读存储单元结构和制造它们的过程
公开(公告)号：US5380672A
公开(公告)日：1995-01-10
申请号：US117219
申请日：1993-09-03
申请人： Jack H. Yuan , Gheorghe Samachisa , Daniel C. Guterman , Eliyahou Harari
发明人： Jack H. Yuan , Gheorghe Samachisa , Daniel C. Guterman , Eliyahou Harari
IPC分类号： H01L27/04 , H01L21/822 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792 , H01L21/265
CPC分类号： H01L27/11521 , H01L21/28273 , H01L27/115 , H01L27/11519
摘要： A memory array of PROM, EPROM or EEPROM cells has each cell formed in a trench of a thick oxide layer deposited on a silicon substrate, in a manner that a significant portion of opposing areas of the floating gate and control gate of each cell which provide capacitive coupling between them are formed vertically. This allows the density of the array to be increased since the amount of semiconductor substrate area occupied by each cell is decreased without having to sacrifice the amount or quality of the capacitive coupling. Further, a technique of forming capacitive coupling between the floating gate and an erase gate in a flash EEPROM array cell with improved endurance is disclosed.
摘要翻译： PROM，EPROM或EEPROM单元的存储器阵列具有以沉积在硅衬底上的厚氧化物层的沟槽中的每个单元的方式使每个单元的浮置栅极和控制栅极的相对区域的大部分提供它们之间的电容耦合垂直形成。这允许阵列的密度增加，因为每个单元占用的半导体衬底面积的数量减少，而不必牺牲电容耦合的量或质量。此外，公开了一种在具有改善的耐久性的快闪EEPROM阵列单元中在浮动栅极和擦除栅极之间形成电容耦合的技术。

17. 发明授权

US5343063A Dense vertical programmable read only memory cell structure and processes for making them 失效
标题翻译：密集的垂直可编程只读存储单元结构和制造它们的过程
公开(公告)号：US5343063A
公开(公告)日：1994-08-30
申请号：US629250
申请日：1990-12-18
申请人： Jack H. Yuan , Gheorghe Samachisa , Daniel C. Guterman , Eliyahou Harari
发明人： Jack H. Yuan , Gheorghe Samachisa , Daniel C. Guterman , Eliyahou Harari
IPC分类号： H01L27/04 , H01L21/822 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792 , H01L29/68 , H01L29/78
CPC分类号： H01L27/11521 , H01L21/28273 , H01L27/115 , H01L27/11519
摘要： A memory array of PROM, EPROM or EEPROM cells has each cell formed in a trench of a thick oxide layer deposited on a silicon substrate, in a manner that a significant portion of opposing areas of the floating gate and control gate of each cell which provide capacitive coupling between them are formed vertically. This allows the density of the array to be increased since the amount of semiconductor substrate area occupied by each cell is decreased without having to sacrifice the amount or quality of the capacitive coupling. Further, a technique of forming capacitive coupling between the floating gate and an erase gate in a flash EEPROM array cell with improved endurance is disclosed.
摘要翻译： PROM，EPROM或EEPROM单元的存储器阵列具有以沉积在硅衬底上的厚氧化物层的沟槽中的每个单元的方式使每个单元的浮置栅极和控制栅极的相对区域的大部分提供它们之间的电容耦合垂直形成。这允许阵列的密度增加，因为每个单元占用的半导体衬底面积的数量减少，而不必牺牲电容耦合的量或质量。此外，公开了一种在具有改善的耐久性的快闪EEPROM阵列单元中在浮动栅极和擦除栅极之间形成电容耦合的技术。

18. 发明授权

US07211866B2 Scalable self-aligned dual floating gate memory cell array and methods of forming the array 有权
标题翻译：可扩展自对准双浮栅存储单元阵列和形成阵列的方法
公开(公告)号：US07211866B2
公开(公告)日：2007-05-01
申请号：US11111129
申请日：2005-04-20
申请人： Jack H. Yuan , Eliyahou Harari , Yupin K. Fong , George Samachisa
发明人： Jack H. Yuan , Eliyahou Harari , Yupin K. Fong , George Samachisa
IPC分类号： H01L27/01
CPC分类号： H01L27/11521 , H01L21/28273 , H01L27/115 , H01L27/11531 , H01L27/11548 , H01L29/42328 , H01L29/7887
摘要： An integrated non-volatile memory circuit is formed by first growing a thin dielectric layer on a semiconductor substrate surface, followed by depositing a layer of conductive material such as doped polysilicon on this dielectric layer, the conductive material then being separated into rows and columns of individual floating gates. Cell source and drain diffusions in the substrate are continuously-elongated across the rows. Field dielectric deposited between the rows of floating gates provides electrical isolation between the rows. Shallow trenches may be included between rows without interrupting the conductivity of the diffusions along their lengths. A deep dielectric filled trench is formed in the substrate between the array and peripheral circuits as electrical isolation. Various techniques are included that increase the field coupling area between the floating gates and a control gate. Other techniques increase the thickness of dielectric between control gates in order to decrease the field coupling between them.
摘要翻译：通过首先在半导体衬底表面上生长薄的电介质层，然后在该电介质层上沉积诸如掺杂多晶硅的导电材料层，然后将导电材料分离成行和列，形成集成的非易失性存储器电路个别浮动门。衬底中的电荷源和漏极扩散在整个行上连续伸长。沉积在浮动栅极行之间的场电介质在行之间提供电隔离。可以在行之间包括浅沟槽，而不会中断沿其长度的扩散的导电性。在阵列和外围电路之间的衬底中形成深电介质填充沟槽作为电隔离。包括增加浮动栅极和控制栅极之间的场耦合区域的各种技术。其他技术增加了控制栅之间的电介质厚度，以减小它们之间的场耦合。

19. 发明授权

US06894343B2 Floating gate memory cells utilizing substrate trenches to scale down their size 有权
标题翻译：浮栅存储单元利用衬底沟槽来缩小其尺寸
公开(公告)号：US06894343B2
公开(公告)日：2005-05-17
申请号：US09860704
申请日：2001-05-18
申请人： Eliyahou Harari , Jack H. Yuan , George Samachisa
发明人： Eliyahou Harari , Jack H. Yuan , George Samachisa
IPC分类号： H01L21/8247 , H01L27/115 , H01L29/788
CPC分类号： H01L27/11521 , H01L27/115 , H01L27/11553
摘要： Several embodiments of flash EEPROM split-channel cell arrays are described that position the channels of cell select transistors along sidewalls of trenches in the substrate, thereby reducing the cell area. Select transistor gates are formed as part of the word lines and extend downward into the trenches with capacitive coupling between the trench sidewall channel portion and the select gate. In one embodiment, trenches are formed between every other floating gate along a row, the two trench sidewalls providing the select transistor channels for adjacent cells, and a common source/drain diffusion being positioned at the bottom of the trench. A third gate provides either erase or steering capabilities. In another embodiment, trenches are formed between every floating gate along a row, a source/drain diffusion extending along the bottom of the trench and upwards along one side with the opposite side of the trench being the select transistor channel for a cell. Techniques for manufacturing such flash EEPROM split-channel cell arrays are also described.
摘要翻译：描述了闪存EEPROM分离通道单元阵列的几个实施例，其将单元选择晶体管的通道定位在衬底中的沟槽的侧壁，从而减小单元面积。选择晶体管栅极形成为字线的一部分，并且通过沟槽侧壁沟道部分和选择栅极之间的电容耦合向下延伸到沟槽中。在一个实施例中，在沿着一行的每隔一个浮置栅极之间形成沟槽，所述两个沟槽侧壁为相邻电池提供选择晶体管沟道，以及位于沟槽底部的公共源/漏扩散。第三个门提供擦除或转向功能。在另一个实施例中，在沿着一排的每个浮置栅极之间形成沟槽，沿沟槽的底部延伸的源极/漏极扩散器和沿着一侧的向上并且沟槽的相对侧为用于电池的选择晶体管沟道。还描述了用于制造这种快闪EEPROM分离通道单元阵列的技术。

20. 发明授权

US06953970B2 Scalable self-aligned dual floating gate memory cell array and methods of forming the array 失效
标题翻译：可扩展自对准双浮栅存储单元阵列和形成阵列的方法
公开(公告)号：US06953970B2
公开(公告)日：2005-10-11
申请号：US10799180
申请日：2004-03-12
申请人： Jack H. Yuan , Eliyahou Harari , Yupin K. Fong , George Samachisa
发明人： Jack H. Yuan , Eliyahou Harari , Yupin K. Fong , George Samachisa
IPC分类号： H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792 , H01L31/0392 , H01L27/01 , H01L27/12
CPC分类号： H01L27/11521 , H01L21/28273 , H01L27/115 , H01L27/11531 , H01L27/11548 , H01L29/42328 , H01L29/7887
摘要： An integrated non-volatile memory circuit is formed by first growing a thin dielectric layer on a semiconductor substrate surface, followed by depositing a layer of conductive material such as doped polysilicon on this dielectric layer, the conductive material then being separated into rows and columns of individual floating gates. Cell source and drain diffusions in the substrate are continuously elongated across the rows. Field dielectric deposited between the rows of floating gates provides electrical isolation between the rows. Shallow trenches may be included between rows without interrupting the conductivity of the diffusions along their lengths. A deep dielectric filled trench is formed in the substrate between the array and peripheral circuits as electrical isolation. Various techniques are included that increase the field coupling area between the floating gates and a control gate. Other techniques increase the thickness of dielectric between control gates in order to decrease the field coupling between them.
摘要翻译：通过首先在半导体衬底表面上生长薄的电介质层，然后在该电介质层上沉积诸如掺杂多晶硅的导电材料层，然后将导电材料分离成行和列，形成集成的非易失性存储器电路个别浮动门。衬底中的电荷源和漏极扩散在整个行中连续延伸。沉积在浮动栅极行之间的场电介质在行之间提供电隔离。可以在行之间包括浅沟槽，而不会中断沿其长度的扩散的导电性。在阵列和外围电路之间的衬底中形成深电介质填充沟槽作为电隔离。包括增加浮动栅极和控制栅极之间的场耦合区域的各种技术。其他技术增加了控制栅之间的电介质厚度，以减小它们之间的场耦合。

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