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11. 发明授权

US07281074B2 Method and apparatus to quiesce USB activities using interrupt descriptor caching and asynchronous notifications 有权
公开(公告)号：US07281074B2
公开(公告)日：2007-10-09
申请号：US11171833
申请日：2005-06-29
申请人： Paul S. Diefenbaugh , James Kardach , Barnes Cooper , Leslie E. Cline
发明人： Paul S. Diefenbaugh , James Kardach , Barnes Cooper , Leslie E. Cline
IPC分类号： G06F13/10 , G06F13/38 , G06F13/14
CPC分类号： G06F13/24 , G06F13/12
摘要： In one embodiment, a data processing system includes, but is not limited to, a processor, a memory coupled to the processor, and a universal serial bus (USB) controller coupled to the processor and the memory. The USB controller includes a local memory to cache at least one activity descriptor of at least a portion of a periodic schedule having multiple frames stored in the main memory. The USB controller defers to service an active USB device described by one of the activity descriptors until a corresponding frame is scheduled to be serviced subsequently. Other methods and apparatuses are also described.

12. 发明授权

US07231468B2 Future activity list for peripheral bus host controller 有权
标题翻译：外设总线主机控制器的未来活动列表
公开(公告)号：US07231468B2
公开(公告)日：2007-06-12
申请号：US10456185
申请日：2003-06-06
申请人： Leslie E. Cline
发明人： Leslie E. Cline
IPC分类号： G06F3/00 , G06F13/00
CPC分类号： G06F13/124 , Y02D10/14
摘要： One embodiment includes a future activity list (FAL) maintained within a peripheral bus host controller. The FAL includes information indicating for a number of peripheral bus frames whether those frames will have activity or are null. For frames that will have activity, the host controller performs a system memory read to gather information required to process the active frame. For frames that are null, the host controller does not perform the system memory read. A bus master status bit is pegged (continually set to “true”) by the host controller only when the host controller is processing an active frame. Because the bus master status bit is not pegged by the host controller during null frames, there is greater opportunity for an operating system to enter lower power states.
摘要翻译：一个实施例包括维护在外围总线主机控制器内的未来活动列表（FAL）。 FAL包括指示多个外围总线帧的信息，无论这些帧是否具有活动或为空。对于具有活动的帧，主机控制器执行系统内存读取，以收集处理活动帧所需的信息。对于为空的帧，主机控制器不执行系统内存读取。只有当主机控制器处理活动帧时，总线主控状态位被主机控制器固定（连续设置为“真”）。由于总线主控状态位在空帧期间不被主机控制器挂起，所以操作系统进入较低功率状态的机会更大。

13. 发明授权

US07225347B2 Method and apparatus for enabling a low power mode for a processor 有权
标题翻译：用于为处理器启用低功率模式的方法和装置
公开(公告)号：US07225347B2
公开(公告)日：2007-05-29
申请号：US11300716
申请日：2005-12-13
申请人： Xia Dai , John W. Horigan , Millind Mittal , Leslie E. Cline
发明人： Xia Dai , John W. Horigan , Millind Mittal , Leslie E. Cline
IPC分类号： G06F1/26 , G06F1/32
CPC分类号： G06F1/3203 , G06F12/0891
摘要： In accordance with an embodiment of the present invention, a triggering event is initiated to place a processor in a low power state. The processor may or may not flush a cache upon entering the low power state depending on a power status signal. The power status signal may indicated the relative priority of power reduction associated with placing the processor in the low power state without first flushing the cache versus an increase in soft error rate in the cache associated with reducing the voltage in the low power state.
摘要翻译：根据本发明的实施例，启动触发事件以将处理器置于低功率状态。根据电源状态信号，处理器可能进入或不进入低功率状态时刷新高速缓存。功率状态信号可以指示与将低处理器置于低功率状态相关联的功率降低的相对优先级，而无需首先刷新高速缓存，而与高功率状态中的电压降低相关联的高速缓存中的软错误率的增加。

14. 发明授权

US06748548B2 Computer peripheral device that remains operable when central processor operations are suspended 有权
标题翻译：当中央处理器操作暂停时，可以保持可操作的计算机外围设备
公开(公告)号：US06748548B2
公开(公告)日：2004-06-08
申请号：US09752627
申请日：2000-12-29
申请人： David Bormann , Leslie E. Cline , Frank Hart , Siripong Sritanyarantana
发明人： David Bormann , Leslie E. Cline , Frank Hart , Siripong Sritanyarantana
IPC分类号： G06F126
CPC分类号： G06F1/3215 , G06F13/4022
摘要： A peripheral device having a circuit to detect the power management state of a central processor, a first interface to receive data, and a second interface to couple the peripheral device to the central processor. The peripheral device prevents data transfers that would cause the central processor to change from a second power management state to a first power management state if the central processor is in the second power management state.
摘要翻译：具有检测中央处理器的电源管理状态的电路的外围设备，用于接收数据的第一接口以及将外围设备耦合到中央处理器的第二接口。如果中央处理器处于第二电源管理状态，则外围设备防止将导致中央处理器从第二电源管理状态改变到第一电源管理状态的数据传输。

15. 发明申请

US20110127834A1 INTERVENTION OF INDEPENDENT SELF-REGULATION OF POWER CONSUMPTION DEVICES 审中-公开
标题翻译：独立自我调节功率消耗装置的干预措施
公开(公告)号：US20110127834A1
公开(公告)日：2011-06-02
申请号：US13023355
申请日：2011-02-08
申请人： Leslie E. Cline , Sitaram Yadavalli , Ishmael Santos , Jim Hermerding
发明人： Leslie E. Cline , Sitaram Yadavalli , Ishmael Santos , Jim Hermerding
IPC分类号： H02J4/00
CPC分类号： G06F1/3203 , G06F1/206 , Y02D10/16 , Y10T307/438
摘要： Methods and apparatuses for intervening in the self power or thermal regulations of a plurality of independent power consumption devices are described herein. The novel methods may include monitoring power consumption and thermal conditions of the plurality of power consumption (i.e., power/heat dissipation) devices that are configured to independently self-regulate their power/thermal production. A determination may then be made as to whether an aggregate of the power and/or thermal production of the plurality of power consumption devices exceed a threshold. And if the aggregate of the power or thermal production of the power consumption devices was determined to exceed the threshold, terminating, at least partially, the independent self-regulating of the thermal production and intervening in the thermal regulation of one or more of the power consumption devices. In contrast, if the aggregate of the power and/or thermal production of the plurality of power consumption devices is determined to be below the threshold then the power consumption devices may be allowed to self-regulate their power consumptions, and in some instances, one or more of the individual power clamps for the one or more of the power consumption devices may be relaxed or raised.
摘要翻译：本文描述了用于干预多个独立功率消耗装置的自身功率或热规定的方法和装置。新颖的方法可以包括监视被配置为独立地自我调节其功率/热产生的多个功率消耗（即，功率/散热）设备的功率消耗和热条件。然后可以确定多个功率消耗装置的功率和/或热产生的总和是否超过阈值。而且如果功率消耗装置的功率或热产生的总和被确定为超过阈值，则至少部分终止热产生的独立自我调节并且介入一个或多个功率的热调节消费设备。相比之下，如果确定多个功率消耗装置的功率和/或热产生的总和低于阈值，则可以允许功率消耗装置自我调节其功率消耗，并且在一些情况下，一个或更多个用于一个或多个功率消耗装置的单个功率夹可以被放宽或提高。

16. 发明授权

US07523327B2 System and method of coherent data transfer during processor idle states 有权
标题翻译：处理器空闲状态期间相干数据传输的系统和方法
公开(公告)号：US07523327B2
公开(公告)日：2009-04-21
申请号：US11074233
申请日：2005-03-05
申请人： Leslie E. Cline , Siripong Sritanyaratana , Alon Naveh , Shai Rotem , Eric C. Samson , Michael N. Derr
发明人： Leslie E. Cline , Siripong Sritanyaratana , Alon Naveh , Shai Rotem , Eric C. Samson , Michael N. Derr
IPC分类号： G06F1/32
CPC分类号： G06F12/0835 , G06F2212/1028 , Y02D10/13
摘要： Systems and methods of managing power provide for placing a processor in a non-snoopable state, where the processor is associated with a system memory. One or more data transfers between a controller and the system memory can be serviced while the processor is in the non-snoopable state. In one embodiment, it is determined that the processor has flushed an internal cache of the processor to the system memory before placing the processor in the non-snoopable state.
摘要翻译：管理电源的系统和方法提供将处理器置于不可窥探状态，其中处理器与系统存储器相关联。当处理器处于非可窥探状态时，可以在控制器和系统存储器之间进行一个或多个数据传输。在一个实施例中，在将处理器置于非可窥探状态之前，确定处理器将处理器的内部高速缓冲器刷新到系统存储器。

17. 发明授权

US07149909B2 Power management for an integrated graphics device 有权
公开(公告)号：US07149909B2
公开(公告)日：2006-12-12
申请号：US10143406
申请日：2002-05-09
申请人： Ying Cui , Eric C. Samson , Ariel Berkovits , Aditya Navale , David A. Wyatt , Leslie E. Cline , Joseph W. Tsang , Mark A. Blake , David I. Poisner , William A. Stevens , Vijay R. Sar-Dessai
发明人： Ying Cui , Eric C. Samson , Ariel Berkovits , Aditya Navale , David A. Wyatt , Leslie E. Cline , Joseph W. Tsang , Mark A. Blake , David I. Poisner , William A. Stevens , Vijay R. Sar-Dessai
IPC分类号： G06F1/32
CPC分类号： G06F1/3228 , G06F1/3215 , G06F1/324 , G06F1/325 , G06F1/3296 , Y02D10/126 , Y02D10/172
摘要： In one embodiment of the invention, an integrated device is described that employs a mechanism to control power consumption of a graphics memory controller hub (GMCH) through both voltage and frequency adjustment of clock signal received from a clock generator. The GMCH comprises a graphics core and a circuit to alter operational behavior, such as the frequency of a render clock signal supplied to the graphics core. The circuit is adapted to monitor idleness of the graphics core and reduce a frequency level of the render clock signal if the idleness exceeds a determined percentage of time.

18. 发明授权

US07027057B2 Entering and exiting power managed states without disrupting accelerated graphics port transactions 失效
公开(公告)号：US07027057B2
公开(公告)日：2006-04-11
申请号：US10640196
申请日：2003-08-12
申请人： Satchit Jain , Debra T. Cohen , Leslie E. Cline , Barnes Cooper , Anil V. Nanduri
发明人： Satchit Jain , Debra T. Cohen , Leslie E. Cline , Barnes Cooper , Anil V. Nanduri
IPC分类号： G06F13/14 , G06F1/26 , G06F1/32 , G06F13/28 , G09F5/39
CPC分类号： G06T17/00 , G06F1/3203
摘要： An interface between an accelerated graphics port graphics controller (AGP-GC) and a core controller to prevent entry into a low power state from interfering with transfers to or from the AGP-GC that have been requested but not completed. The core controller can communicate to the AGP-GC an intent to enter a low power state, while the AGP-GC can communicate to the core controller the busy status of the AGP-GC. When the AGP-GC receives notice of an intent to enter a low power state, it can stop issuing requests to the core controller. When the core controller detects that the AGP-GC is busy, the core controller can postpone entry into the low power state until the AGP-GC completes any requests that are in progress. In an alternate use of the interface, if the AGP-GC wishes to make a request during a low power state, it can signal the core controller of this need by indicating a busy status, which can trigger the core controller to initiate an exit from the low power state.

19. 发明授权

US06976181B2 Method and apparatus for enabling a low power mode for a processor 有权
标题翻译：用于为处理器启用低功率模式的方法和装置
公开(公告)号：US06976181B2
公开(公告)日：2005-12-13
申请号：US10027939
申请日：2001-12-20
申请人： Xia Dai , John W. Horigan , Millind Mittal , Leslie E. Cline
发明人： Xia Dai , John W. Horigan , Millind Mittal , Leslie E. Cline
IPC分类号： G06F1/32 , G06F12/08 , G06F1/26
CPC分类号： G06F1/3203 , G06F12/0891
摘要： In accordance with an embodiment of the present invention, a triggering event is initiated to place a processor in a low power state. The processor may or may not flush a cache upon entering the low power state depending on a power status signal. The power status signal may indicate the relative priority of power reduction associated with placing the processor in the low power state without first flushing the cache versus an increase in soft error rate in the cache associated with reducing the voltage in the low power state.
摘要翻译：根据本发明的实施例，启动触发事件以将处理器置于低功率状态。根据电源状态信号，处理器可能进入或不进入低功率状态时刷新高速缓存。功率状态信号可以指示与将处理器置于低功率状态相关联的功率降低的相对优先级，而不首先冲洗高速缓存，而与高功率状态中的电压降低相关联的高速缓存中的软错误率的增加。

20. 发明授权

US06738068B2 Entering and exiting power managed states without disrupting accelerated graphics port transactions 有权
标题翻译：进入和退出电源管理状态，而不会中断加速图形端口事务
公开(公告)号：US06738068B2
公开(公告)日：2004-05-18
申请号：US09751441
申请日：2000-12-29
申请人： Debra T. Cohen , Leslie E. Cline , Barnes Cooper , Satchit Jain , Anil V. Nanduri
发明人： Debra T. Cohen , Leslie E. Cline , Barnes Cooper , Satchit Jain , Anil V. Nanduri
IPC分类号： G06F1314
CPC分类号： G06T17/00 , G06F1/3203
摘要： An interface between an accelerated graphics port graphics controller (AGP-GC) and a core controller to prevent entry into a low power state from interfering with transfers to or from the AGP-GC that have been requested but not completed. The core controller can communicate to the AGP-GC an intent to enter a low power state, while the AGP-GC can communicate to the core controller the busy status of the AGP-GC. When the AGP-GC receives notice of an intent to enter a low power state, it can stop issuing requests to the core controller. When the core controller detects that the AGP-GC is busy, the core controller can postpone entry into the low power state until the AGP-GC completes any requests that are in progress. In an alternate use of the interface, if the AGP-GC wishes to make a request during a low power state, it can signal the core controller of this need by indicating a busy status, which can trigger the core controller to initiate an exit from the low power state.
摘要翻译：加速图形端口图形控制器（AGP-GC）和核心控制器之间的接口，以防止进入低功率状态，干扰来自AGP-GC的请求但尚未完成的传输。核心控制器可以与AGP-GC进行通信，意图进入低功率状态，而AGP-GC可以与核心控制器通信AGP-GC的忙碌状态。当AGP-GC接收到进入低功率状态的意图时，可以停止向核心控制器发出请求。当核心控制器检测到AGP-GC正忙时，核心控制器可以推迟进入低功率状态，直到AGP-GC完成任何正在进行的请求。在接口的替代使用中，如果AGP-GC希望在低功率状态期间发出请求，则可以通过指示忙状态来向核心控制器通知该核心控制器，这可以触发核心控制器发起退出低功率状态。

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