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11. 发明申请

US20090219768A1 SEMICONDUCTOR MEMORY DEVICE HAVING SHARED BIT LINE SENSE AMPLIFIER SCHEME AND DRIVING METHOD THEREOF 审中-公开
标题翻译：具有共享位线检测放大器方案的半导体存储器件及其驱动方法
公开(公告)号：US20090219768A1
公开(公告)日：2009-09-03
申请号：US12466180
申请日：2009-05-14
申请人： Dong-Keun Kim , Chang-Ho Do
发明人： Dong-Keun Kim , Chang-Ho Do
IPC分类号： G11C7/00
CPC分类号： G11C7/12 , G11C7/06 , G11C7/065 , G11C7/18 , G11C11/4091 , G11C11/4094 , G11C11/4097 , G11C2207/002
摘要： A semiconductor memory device has a shared bit line sense amplifier. The semiconductor memory device includes: a bit line sense amplifier for amplifying data applied on bit line pair; an upper bit line disconnection unit for selectively disconnecting the bit line sense amplifier from bit line pair of an upper cell array in response to an upper bit line disconnection signal; a lower bit line disconnection unit for selectively disconnecting the bit line sense amplifier from bit line pair of a lower cell array in response to a lower bit line disconnection signal; an upper bit line equalization unit for equalizing the bit line pair of the upper cell array in response to the lower bit line disconnection signal; and a lower bit line equalization unit for equalizing the bit line pair of the lower cell array in response to the upper bit line disconnection signal.
摘要翻译：半导体存储器件具有共享位线读出放大器。半导体存储器件包括：位线读出放大器，用于放大施加在位线对上的数据; 高位线断路单元，用于响应于高位线断开信号，选择性地将位线读出放大器与上单元阵列的位线对断开; 低位线断开单元，用于响应于较低位线断开信号，选择性地将位线读出放大器与下单元阵列的位线对断开; 高位线均衡单元，用于响应于较低位线断开信号对上位单元阵列的位线对进行均衡; 以及低位线均衡单元，用于响应于高位线断开信号来均衡下单元阵列的位线对。

12. 发明授权

US07532530B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US07532530B2
公开(公告)日：2009-05-12
申请号：US11528521
申请日：2006-09-28
申请人： Dong-Keun Kim
发明人： Dong-Keun Kim
IPC分类号： G11C7/02
CPC分类号： G11C7/18 , G11C7/1078 , G11C7/1096 , G11C7/12 , G11C11/4074 , G11C11/4094 , G11C11/4096 , G11C11/4097
摘要： A semiconductor memory device can reduce a data writing time. The semiconductor memory device includes a bit line sense amplifier connected to a pair of bit lines. A pair of first local lines id connected to the pair of bit lines by a first switching unit. A pair of second local lines is connected to the pair of first local lines by a second switching unit. A writing driver drives the second local lines using a normal-driving voltage in response to a data signal through a global line. The writing driver drives the second local lines using an over-driving voltage having a higher level than that of the normal-driving voltage during a predetermined period.
摘要翻译：半导体存储器件可以减少数据写入时间。半导体存储器件包括连接到一对位线的位线读出放大器。通过第一切换单元连接到该对位线的一对第一本地线路id。一对第二本地线路通过第二切换单元与一对第一本地线路连接。写入驱动器响应于通过全局线的数据信号，使用正常驱动电压来驱动第二本地线路。写入驱动器在预定时段内使用具有比正常驱动电压高的电平的过驱动电压来驱动第二本地线路。

13. 发明申请

US20060141790A1 Chemical mechanical polishing method 有权
公开(公告)号：US20060141790A1
公开(公告)日：2006-06-29
申请号：US11321848
申请日：2005-12-28
申请人： Dong-Keun Kim , Chung-Ki Min , Yong-Sun Ko , Kyung-Hyun Kim
发明人： Dong-Keun Kim , Chung-Ki Min , Yong-Sun Ko , Kyung-Hyun Kim
IPC分类号： H01L21/302 , H01L21/461
CPC分类号： H01L21/76819 , C09G1/02 , H01L21/31053
摘要： In an embodiment, a chemical mechanical polishing method for a substrate having a first layer and a stepped portion. A surface of the first layer is positioned above an upper face of the stepped portion. A polishing process for selectively removing the stepped portion is performed on the first layer by using a first slurry composition that has a self-stopping characteristic so that the first layer is changed into a second layer having a substantially flat surface. A second polishing process is performed using a second slurry composition that does not have the self-stopping characteristic, until the upper face of the stepped portion is exposed.

14. 发明申请

US20050248672A1 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US20050248672A1
公开(公告)日：2005-11-10
申请号：US10877880
申请日：2004-06-25
申请人： Dong-Keun Kim , Chang-Ho Do
发明人： Dong-Keun Kim , Chang-Ho Do
IPC分类号： G11C11/4091 , G11C7/12 , G11C7/18 , H04N5/3745 , H04N5/335
CPC分类号： G11C7/18 , G11C7/12
摘要： A semiconductor memory device having a shared bit line sense amplifier structure is provided. The semiconductor memory device includes: a plurality of cell arrays each of which has a plurality of bit line pairs, in which the cell arrays includes a first cell array disposed at an edge portion of a cell region and a second cell array disposed adjacent to the first cell array; a first precharging unit for precharging some bit line pairs of the first or second cell array; a second precharging unit for precharging the other bit line pairs of the first cell array; and an auxiliary precharging unit for assisting a precharge operation of the second precharging unit.
摘要翻译：提供具有共享位线读出放大器结构的半导体存储器件。半导体存储器件包括：多个单元阵列，每个单元阵列具有多个位线对，其中单元阵列包括设置在单元区域的边缘部分处的第一单元阵列和邻近单元阵列设置的第二单元阵列第一个单元格阵列; 用于对所述第一或第二单元阵列的某些位线对进行预充电的第一预充电单元; 第二预充电单元，用于对第一单元阵列的其它位线对进行预充电; 以及用于辅助第二预充电单元的预充电操作的辅助预充电单元。

15. 发明授权

US08139415B2 Phase-change memory device 有权
标题翻译：相变存储器件
公开(公告)号：US08139415B2
公开(公告)日：2012-03-20
申请号：US12488637
申请日：2009-06-22
申请人： Dong-Keun Kim
发明人： Dong-Keun Kim
IPC分类号： G11C16/04
CPC分类号： G11C8/10 , G11C8/14 , G11C13/0004
摘要： A phase-change memory device is capable of reducing current consumption and preventing performance deterioration caused due to line load by improving a process of selecting memory cells for a write/read operation. The phase-change memory device has a plurality of cell matrixes and includes word line decoding units that are each shared by a plurality of cell matrixes arranged in a row direction and are configured to activate one of global row signals according to a first row address, local row switch units that are provided to the respective cell matrixes and are configured to connect local current lines to corresponding word lines in response to the activated global row signal, bus connecting units that are provided to the respective cell matrixes and are configured to connect the local current lines to global current lines, and enabling units configured to activate one of the global current lines according to a second row address.
摘要翻译：相变存储器件能够通过改善对写入/读取操作选择存储单元的处理来降低电流消耗并防止由于线路负载引起的性能劣化。相变存储器件具有多个单元矩阵，并且包括字线解码单元，每个字线解码单元由行行方向排列的多个单元矩阵共享，并且被配置为根据第一行地址激活全局行信号之一，本地行开关单元，其被提供给相应的单元矩阵，并且被配置为响应于激活的全局行信号将局部当前行连接到对应的字线，提供给相应的单元矩阵的总线连接单元被配置为将局部当前线路到全局当前线路，以及启用被配置为根据第二行地址激活全局当前线路之一的单元。

16. 发明申请

US20090059694A1 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US20090059694A1
公开(公告)日：2009-03-05
申请号：US12005915
申请日：2007-12-28
申请人： Dong-Keun Kim , Seung-Lo Kim
发明人： Dong-Keun Kim , Seung-Lo Kim
IPC分类号： G11C7/00 , G11C8/00
CPC分类号： G11C8/08 , G11C8/06 , G11C8/12
摘要： A semiconductor memory device includes: a reference signal delay unit configured to delay a reference signal for a predetermined operation to output a delayed reference signal; an address delay unit configured to delay a bank address to output a delayed bank address; and a decoding unit configured to receive the delayed reference signal to output a signal for determining a timing of a predetermined operation on a bank selected by the delayed bank address.
摘要翻译：半导体存储器件包括：参考信号延迟单元，被配置为延迟用于预定操作的参考信号以输出延迟的参考信号; 地址延迟单元，被配置为延迟存储体地址以输出延迟的存储体地址; 以及解码单元，被配置为接收延迟的参考信号，以输出用于确定由延迟的存储体地址选择的存储体上的预定操作的定时的信号。

17. 发明授权

US07495983B2 Semiconductor memory device having bit line equalizer in cell array 有权
标题翻译：具有单元阵列中的位线均衡器的半导体存储器件
公开(公告)号：US07495983B2
公开(公告)日：2009-02-24
申请号：US11647370
申请日：2006-12-29
申请人： Dong-Keun Kim
发明人： Dong-Keun Kim
IPC分类号： G11C7/00
CPC分类号： G11C7/12 , G11C7/18
摘要： A semiconductor memory device includes at least one cell array and first and second bit line sense amplifying units. A cell array includes a plurality of bit line pairs and a plurality of bit line equalizers connected to each other through a signal line. Each bit line equalizer equalizes a corresponding bit line pair. The first and the second bit line sense amplifying units are alternately connected to the bit line pairs and receive respective bit line equalization signals.
摘要翻译：半导体存储器件包括至少一个单元阵列和第一和第二位线读出放大单元。单元阵列包括通过信号线彼此连接的多个位线对和多个位线均衡器。每个位线均衡器均衡相应的位线对。第一和第二位线检测放大单元交替地连接到位线对并接收相应的位线均衡信号。

18. 发明申请

US20080081460A1 Method of manufaturing a semiconductor device 审中-公开
标题翻译：制造半导体器件的方法
公开(公告)号：US20080081460A1
公开(公告)日：2008-04-03
申请号：US11903610
申请日：2007-09-24
申请人： Chang-Yeon Yoo , Chung-Ki Min , Yung-Jun Kim , Joon-Sang Park , Dong-Keun Kim , Tae-Eun Kim
发明人： Chang-Yeon Yoo , Chung-Ki Min , Yung-Jun Kim , Joon-Sang Park , Dong-Keun Kim , Tae-Eun Kim
IPC分类号： H01L21/4763
CPC分类号： H01L21/76819
摘要： In a method of manufacturing a semiconductor device, a preliminary insulating layer is formed on a substrate. A photoresist pattern is formed on the preliminary insulating layer. A central portion of the preliminary insulating layer is partially etched using the photoresist pattern as an etch mask to form a preliminary insulating layer pattern including a central portion and a peripheral portion on the substrate. The peripheral portion of the photoresist pattern is higher than that of the central portion of the preliminary insulating layer pattern. The preliminary insulating layer pattern is polished to form a planarized insulating layer on the substrate.
摘要翻译：在半导体装置的制造方法中，在基板上形成预备绝缘层。在初级绝缘层上形成光刻胶图形。使用光致抗蚀剂图案作为蚀刻掩模来部分地蚀刻初步绝缘层的中心部分，以在衬底上形成包括中心部分和周边部分的初步绝缘层图案。光致抗蚀剂图案的周边部分比初级绝缘层图案的中心部分高。对初始绝缘层图案进行研磨以在基板上形成平坦化的绝缘层。

19. 发明申请

US20070133989A1 GPON system and method for bandwidth allocation in GPON system 审中-公开
标题翻译： GPON系统中的GPON系统和带宽分配方法
公开(公告)号：US20070133989A1
公开(公告)日：2007-06-14
申请号：US11592274
申请日：2006-11-03
申请人： Yu-Gun Kim , Byeong-Hoon Kim , Tae-Sung Park , Jeong-Won Park , Jai-Young Park , Jong-Kook Kim , Dong-Keun Kim , Su-Hyung Kim , Jae-Young Lee , Jae-Hyun Kim , Hoon-Jae Yeon
发明人： Yu-Gun Kim , Byeong-Hoon Kim , Tae-Sung Park , Jeong-Won Park , Jai-Young Park , Jong-Kook Kim , Dong-Keun Kim , Su-Hyung Kim , Jae-Young Lee , Jae-Hyun Kim , Hoon-Jae Yeon
IPC分类号： H04J14/00
CPC分类号： H04J3/1694 , H04J14/0226 , H04J14/0247 , H04J14/0252 , H04J14/0282
摘要： In a gigabit-capable passive optical network (GPON) system and in a method for bandwidth allocation in a passive optical network (PON) system, a minimum bandwidth is allocated to optical network units (ONUs) for minimal transmission assurance dependent on a traffic characteristic of each ONU, and when there is a traffic-container (T-CONT) class of an ONU not allocated bandwidth after minimum bandwidth allocation to all ONUs, an extra bandwidth remaining after minimum bandwidth allocation is dynamically allocated to each T-CONT class according to a weight of the T-CONT class. Thus, efficient bandwidth allocation, considering fairness between ONUs and priority of each T-CONT, is realized.
摘要翻译：在无源光网络（PON）系统中的千兆位无源光网络（GPON）系统和用于带宽分配的方法中，最小带宽被分配给光网络单元（ONU），以根据流量特性进行最小的传输保证，并且当在所有ONU的最小带宽分配之后没有分配带宽的ONU的业务容器（T-CONT）类别时，在每个T-CONT类别之后动态分配最小带宽分配后剩余的额外带宽，达到T-CONT类的重量。因此，考虑到ONU之间的公平性和每个T-CONT的优先级，实现了有效的带宽分配。

20. 发明授权

US09298251B2 Methods of spreading plurality of interrupts, interrupt request signal spreader circuits, and systems-on-chips having the same 有权
标题翻译：扩展多个中断的方法，中断请求信号扩展器电路和具有该中断的片上系统
公开(公告)号：US09298251B2
公开(公告)日：2016-03-29
申请号：US13677775
申请日：2012-11-15
申请人： Jae-Gon Lee , Dong-Keun Kim , Si-Young Kim , Jung-Hun Heo
发明人： Jae-Gon Lee , Dong-Keun Kim , Si-Young Kim , Jung-Hun Heo
IPC分类号： G06F1/00 , G06F1/32 , G06F13/24 , G06F9/48 , G06F9/50
CPC分类号： G06F1/3243 , G06F1/3203 , G06F1/3287 , G06F9/4812 , G06F9/5094 , G06F13/24 , Y02D10/152 , Y02D10/22 , Y02D50/20
摘要： In a method of power control for a system-on-chip, output of at least one of a first wakeup request signal and a second wakeup request signal is controlled such that a time interval between the output of the first wakeup request signal and the output of the second wakeup request signal is greater than or equal to a time interval threshold. The first wakeup request signal and the second wakeup request signal are one of concurrent and consecutive wakeup request signals.
摘要翻译：在片上系统的功率控制方法中，控制第一唤醒请求信号和第二唤醒请求信号中的至少一个的输出，使得第一唤醒请求信号的输出与输出之间的时间间隔的第二唤醒请求信号大于或等于时间间隔阈值。第一唤醒请求信号和第二唤醒请求信号是并发和连续的唤醒请求信号之一。

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