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11. 发明申请

US20120206983A1 TRACKING SCHEME FOR MEMORY 有权
标题翻译：记忆追踪方案
公开(公告)号：US20120206983A1
公开(公告)日：2012-08-16
申请号：US13026021
申请日：2011-02-11
申请人： Yong ZHANG , Derek C. TAO , Dongsik JEONG , Young Suk KIM , Kuoyuan (Peter) HSU
发明人： Yong ZHANG , Derek C. TAO , Dongsik JEONG , Young Suk KIM , Kuoyuan (Peter) HSU
IPC分类号： G11C7/06 , G11C7/00
CPC分类号： G11C7/227 , G11C11/419
摘要： A memory has a tracking circuit for a read tracking operation. The memory includes a memory bit cell array, a tracking column, a tracking row, a sense amplifier row coupled to the memory bit cell array and the tracking row, and a sense amplifier enable logic. The memory further includes a tracking bit line coupled to the tracking column and the sense amplifier enable logic, and a tracking word line coupled to the tracking row and the sense amplifier enable logic. The tracking circuit is configured to track a column time delay along the tracking column before a row time delay along the tracking row.
摘要翻译：存储器具有用于读取跟踪操作的跟踪电路。存储器包括存储位单元阵列，跟踪列，跟踪行，耦合到存储器位单元阵列和跟踪行的读出放大器行以及读出放大器使能逻辑。存储器还包括耦合到跟踪列和读出放大器使能逻辑的跟踪位线，以及耦合到跟踪行和读出放大器使能逻辑的跟踪字线。跟踪电路被配置为沿着跟踪行在行时间延迟之前跟踪沿着跟踪列的列时间延迟。

12. 发明申请

US20120049374A1 METHOD AND APPARATUS FOR MEMORY CELL LAYOUT 有权
标题翻译：用于存储单元布局的方法和装置
公开(公告)号：US20120049374A1
公开(公告)日：2012-03-01
申请号：US12862387
申请日：2010-08-24
申请人： Jacklyn CHANG , Kuoyuan HSU , Derek C. TAO
发明人： Jacklyn CHANG , Kuoyuan HSU , Derek C. TAO
IPC分类号： H01L23/535 , H01L21/82
CPC分类号： H01L27/1104 , G11C11/412 , H01L27/0207
摘要： A semiconductor device has first and second interconnect structures in first and second columns, respectively, of an array. Each of the first and second interconnect structures has a reference voltage node and first, second, third, and fourth conductors that are coupled to each other and formed at a first layer, a second layer, a third layer, and a fourth layer, respectively, over a substrate having a plurality of devices defining a plurality of bit cells. The reference voltage node of each interconnect structure provides a respectively separate reference voltage to a bit cell corresponding to said interconnect structure. None of the first, second, third, and fourth conductors in either interconnect structure is connected to a corresponding conductor in the other interconnect structure. The second layer is above the first layer, the third layer is above the second layer, and the fourth layer is above the third layer.
摘要翻译：半导体器件分别在阵列的第一和第二列中具有第一和第二互连结构。第一和第二互连结构中的每一个具有参考电压节点和彼此耦合并分别形成在第一层，第二层，第三层和第四层上的第一，第二，第三和第四导体在具有限定多个位单元的多个器件的衬底上。每个互连结构的参考电压节点向对应于所述互连结构的位单元提供分别分离的参考电压。在互连结构中的第一，第二，第三和第四导体中的任一个都不连接到另一个互连结构中的相应导体。第二层在第一层之上，第三层位于第二层之上，第四层位于第三层之上。

13. 发明申请

US20140015582A1 SLICER AND METHOD OF OPERATING THE SAME 有权
标题翻译： SLICER及其操作方法
公开(公告)号：US20140015582A1
公开(公告)日：2014-01-16
申请号：US13547396
申请日：2012-07-12
申请人： Ming-Chieh HUANG , Chan-Hong CHERN , Tao Wen CHUNG , Chih-Chang LIN , Tsung-Ching HUANG , Derek C. TAO
发明人： Ming-Chieh HUANG , Chan-Hong CHERN , Tao Wen CHUNG , Chih-Chang LIN , Tsung-Ching HUANG , Derek C. TAO
IPC分类号： H03K3/356
CPC分类号： H03K5/08 , H03K3/356139 , H04L27/01
摘要： This description relates to a slicer including a first latch. The first latch includes an evaluating transistor configured to receive a first clock signal and a developing transistor configured to receive a second clock signal. The first clock signal is different from the second clock signal. The first latch includes first and second input transistors configured to receive first and second complementary inputs. The first latch includes at least one pre-charging transistor configured to receive a third clock signal. The first latch further at least one cross-latched pair of transistors, the at least one cross-latched transistor pair connected between the evaluating transistor and the first and second output nodes. The slicer includes a second latch connected to the first and second output nodes and to a third output node. The slicer includes a buffer connected to the third output node and configured to generate a final output signal.
摘要翻译：该描述涉及包括第一锁存器的限幅器。第一锁存器包括被配置为接收第一时钟信号的评估晶体管和被配置为接收第二时钟信号的显影晶体管。第一时钟信号与第二时钟信号不同。第一锁存器包括被配置为接收第一和第二互补输入的第一和第二输入晶体管。第一锁存器包括配置成接收第三时钟信号的至少一个预充电晶体管。第一锁存器还包括至少一个交叉锁存晶体管对，该至少一个交叉锁存晶体管对连接在评估晶体管与第一和第二输出节点之间。切片器包括连接到第一和第二输出节点和第三输出节点的第二锁存器。切片器包括连接到第三输出节点并被配置为产生最终输出信号的缓冲器。

14. 发明申请

US20120182819A1 RECYCLING CHARGES 有权
标题翻译：回收费
公开(公告)号：US20120182819A1
公开(公告)日：2012-07-19
申请号：US13429082
申请日：2012-03-23
申请人： Young Seog KIM , Kuoyuan (Peter) HSU , Derek C. TAO , Young Suk KIM
发明人： Young Seog KIM , Kuoyuan (Peter) HSU , Derek C. TAO , Young Suk KIM
IPC分类号： G11C5/14 , G05F3/02
CPC分类号： G11C11/412
摘要： A circuit includes a first node; a second node; a first PMOS transistor having a source coupled to the first node, a drain coupled to a first control transistor, and a gate driven by a first voltage; and a first NMOS transistor having a source coupled to the second node, a drain coupled to the first control transistor, and a gate driven by a second voltage. The first PMOS transistor is configured to automatically turn off based on the first voltage and a first node voltage at the first node. The first NMOS transistor is configured to automatically turn off based on the second voltage and a second node voltage at the second node. When the first PMOS transistor, the control transistor, and the first NMOS transistor are on, the first node voltage is lowered while the second voltage is raised.
摘要翻译：电路包括第一节点; 第二个节点; 具有耦合到第一节点的源极的第一PMOS晶体管，耦合到第一控制晶体管的漏极和由第一电压驱动的栅极; 以及第一NMOS晶体管，其具有耦合到第二节点的源极，耦合到第一控制晶体管的漏极和由第二电压驱动的栅极。第一PMOS晶体管被配置为基于第一节点处的第一电压和第一节点电压自动关闭。第一NMOS晶体管被配置为基于第二节点处的第二电压和第二节点电压自动关闭。当第一PMOS晶体管，控制晶体管和第一NMOS晶体管导通时，第一节点电压降低，而第二电压升高。

15. 发明申请

US20120020169A1 TWO-PORT SRAM WRITE TRACKING SCHEME 有权
标题翻译：双端口SRAM写入跟踪方案
公开(公告)号：US20120020169A1
公开(公告)日：2012-01-26
申请号：US12839624
申请日：2010-07-20
申请人： Bing WANG , Kuoyuan (Peter) HSU , Derek C. TAO
发明人： Bing WANG , Kuoyuan (Peter) HSU , Derek C. TAO
IPC分类号： G11C7/10
CPC分类号： G11C11/419 , G11C11/413
摘要： A Static Random Access Memory (SRAM) includes at least two memory cells sharing a read bit line (RBL) and a write bit line (WBL). Each memory cell is coupled to a respective read word line (RWL) and a respective write word line (WWL). A write tracking control circuit is coupled to the memory cells for determining a write time of the memory cells. The write tracking control circuit is capable of receiving an input voltage and providing an output voltage. The respective RWL and the respective WWL of each memory cell are asserted during a write tracking operation.
摘要翻译：静态随机存取存储器（SRAM）包括共享读位线（RBL）和写位线（WBL）的至少两个存储器单元。每个存储单元耦合到相应的读字线（RWL）和相应的写字线（WWL）。写跟踪控制电路耦合到存储器单元，以确定存储器单元的写入时间。写跟踪控制电路能够接收输入电压并提供输出电压。在写跟踪操作期间，各存储单元的相应RWL和相应的WWL被断言。

16. 发明申请

US20120019312A1 RECYCLING CHARGES 有权
公开(公告)号：US20120019312A1
公开(公告)日：2012-01-26
申请号：US12843366
申请日：2010-07-26
申请人： Young Seog KIM , Kuoyuan (Peter) HSU , Derek C. TAO , Young Suk KIM
发明人： Young Seog KIM , Kuoyuan (Peter) HSU , Derek C. TAO , Young Suk KIM
IPC分类号： G05F3/02
CPC分类号： G11C11/412
摘要： A circuit includes a first node; a second node; a first PMOS transistor having a source coupled to the first node, a drain coupled to a first control transistor, and a gate driven by a first voltage; and a first NMOS transistor having a source coupled to the second node, a drain coupled to the first control transistor, and a gate driven by a second voltage. The first PMOS transistor is configured to automatically turn off based on the first voltage and a first node voltage at the first node. The first NMOS transistor is configured to automatically turn off based on the second voltage and a second node voltage at the second node. When the first PMOS transistor, the control transistor, and the first NMOS transistor are on, the first node voltage is lowered while the second voltage is raised.

17. 发明申请

US20120014201A1 DUAL RAIL MEMORY 有权
标题翻译：双轨记忆
公开(公告)号：US20120014201A1
公开(公告)日：2012-01-19
申请号：US12835197
申请日：2010-07-13
申请人： Derek C. TAO , Kuoyuan (Peter) HSU , Dong Sik JEONG , Young Suk KIM , Young Seog KIM , Yukit TANG
发明人： Derek C. TAO , Kuoyuan (Peter) HSU , Dong Sik JEONG , Young Suk KIM , Young Seog KIM , Yukit TANG
IPC分类号： G11C5/14
CPC分类号： G11C5/14
摘要： A memory comprising: a plurality of memory cells arranged in a plurality of rows and a plurality of columns. A column of the plurality of columns including a first power supply node configured to provide a first voltage, a second power supply node configured to provide a second voltage, a plurality of internal supply nodes electrically coupled together and configured to receive the first voltage or the second voltage for a plurality of memory cells in the column and a plurality of internal ground nodes. The internal ground nodes electrically coupled together and configured to provide at least two current paths for the plurality of memory cells in the column.
摘要翻译：一种存储器，包括：布置成多行和多列的多个存储单元。所述多列的列包括被配置为提供第一电压的第一电源节点，被配置为提供第二电压的第二电源节点，电耦合在一起并被配置为接收第一电压或该列中的多个存储单元的第二电压和多个内部接地节点。内部接地节点电耦合在一起并且被配置为为列中的多个存储器单元提供至少两个电流路径。

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