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11. 发明授权

US6018803A Method and apparatus for detecting bus utilization in a computer system based on a number of bus events per sample period 失效
标题翻译：基于每个采样周期的总线事件数量来检测计算机系统中的总线利用的方法和装置
公开(公告)号：US6018803A
公开(公告)日：2000-01-25
申请号：US768913
申请日：1996-12-17
申请人： James P. Kardach
发明人： James P. Kardach
IPC分类号： G06F1/32 , G06F11/34
CPC分类号： G06F1/3228 , G06F1/3215 , G06F11/349 , G06F2201/81
摘要： A bus utilization detection circuit and method. An input is configured to be coupled to a bus to detect bus events. A circuit coupled to the input determines a number of bus events during a first sample period to indicate a percent bus utilization. If the number of bus events during the first sample period meets a first predetermined threshold value, then an activity event is generated. In another embodiment, an activity event is generated only if during a second sample period, the number of first sample periods for which the percent bus utilization meets the first threshold value meets a second threshold value.
摘要翻译：一种总线利用检测电路及方法。输入被配置为耦合到总线以检测总线事件。耦合到输入的电路确定在第一采样周期期间的总线事件数量，以指示百分比总线利用率。如果在第一采样周期期间总线事件的数量满足第一预定阈值，则生成活动事件。在另一个实施例中，仅当在第二采样周期期间，百分比总线利用率满足第一阈值的第一采样周期的数量满足第二阈值时才产生活动事件。

12. 发明授权

US6014751A Method and apparatus for maintaining cache coherency in an integrated circuit operating in a low power state 失效
标题翻译：用于在低功率状态下工作的集成电路中保持高速缓存一致性的方法和装置
公开(公告)号：US6014751A
公开(公告)日：2000-01-11
申请号：US841858
申请日：1997-05-05
申请人： James P. Kardach , John Horigan , Ravi Eakambaram , Tosaku Nakanishi , Chih-Hung Chung , Borys S. Senyk
发明人： James P. Kardach , John Horigan , Ravi Eakambaram , Tosaku Nakanishi , Chih-Hung Chung , Borys S. Senyk
IPC分类号： G06F1/04 , G06F1/32 , G06F12/08 , G06F1/10
CPC分类号： G06F1/3237 , G06F1/3203 , G06F1/324 , G06F12/0835 , Y02B60/1217 , Y02B60/1221
摘要： A method and apparatus for operating an integrated in a reduced-power consumption state are described. The apparatus comprises power-reduction logic which, to place the integrated circuit in the reduced-power consumption state, gates a clock signal to both first and second sets of functional units within the integrated circuit. The first set of functional units is distinguished in that it is required to perform cache coherency operations within integrated circuit. The apparatus includes an input which is coupled to receive a signal indicating a memory access, to a memory resource accessible by the integrated circuit, by a further device external to the integrated circuit. In response to the assertion of this signal, the power-reduction logic propagates the clock signal to the first set of functional units, to enable this set of functional units to perform a cache coherency operation which may be necessitated by the memory access by the external device.
摘要翻译：描述用于操作集成在降低功耗状态的方法和装置。该装置包括功率降低逻辑，为了将集成电路置于降低功耗状态，将集成电路中的第一组和第二组功能单元的时钟信号置于门限。第一组功能单元的特征在于需要在集成电路内执行高速缓存一致性操作。该装置包括输入，该输入被耦合以通过集成电路外部的另外的设备将指示存储器访问的信号接收到由集成电路可访问的存储器资源。响应于该信号的断言，功率降低逻辑将时钟信号传播到第一组功能单元，以使得该组功能单元能够执行高速缓存一致性操作，这可能由外部存储器访问所必需设备。

13. 发明授权

US5918043A Method and apparatus for asynchronously stopping the clock in a processor 失效
标题翻译：用于在处理器中异步停止时钟的方法和装置
公开(公告)号：US5918043A
公开(公告)日：1999-06-29
申请号：US874559
申请日：1997-06-13
申请人： James P. Kardach , Tosaku Nakanishi , Jimmy S. Cheng
发明人： James P. Kardach , Tosaku Nakanishi , Jimmy S. Cheng
IPC分类号： G06F1/04 , G06F1/10 , G06F1/26 , G06F11/00 , G06F11/267
CPC分类号： G06F11/2236 , G06F1/04 , G06F1/10 , G06F1/26 , G06F11/004
摘要： An apparatus and method for controlling the stopping of the clock signal utilized by the processing unit of a computer system comprises the use of a novel external pin which can be enabled to initiate a sequence of events that results in the halting of the internal clock signal. The invention includes a microcode engine that responds to the/assertion of the external pin by executing a sequence of steps which stops the current instruction on an instruction boundary. A logic circuit then generates a signal that masks the clock signal produced by the system's phase-locked loop. An interrupt mechanism is also utilized to prioritize the occurrence of the external signal among other system interrupts. The interrupt mechanism insures that the processor never has its clock stopped in the middle of a bus cycle.
摘要翻译：用于控制由计算机系统的处理单元使用的时钟信号的停止的装置和方法包括使用新颖的外部引脚，该引脚能够启动导致停止内部时钟信号的事件序列。本发明包括微代码引擎，其通过执行在指令边界上停止当前指令的一系列步骤来响应/断言外部引脚。然后，逻辑电路产生屏蔽由系统的锁相环产生的时钟信号的信号。中断机制也用于优先考虑外部信号在其他系统中断中的发生。中断机制确保处理器在总线周期的中间没有停止其时钟。

14. 发明授权

US5655127A Method and apparatus for control of power consumption in a computer system 失效
标题翻译：用于控制计算机系统中功耗的方法和装置
公开(公告)号：US5655127A
公开(公告)日：1997-08-05
申请号：US612673
申请日：1996-03-08
申请人： Jeffrey L. Rabe , Zohar Bogin , Ajay V. Bhatt , James P. Kardach , Nilesh V. Shah
发明人： Jeffrey L. Rabe , Zohar Bogin , Ajay V. Bhatt , James P. Kardach , Nilesh V. Shah
IPC分类号： G06F1/32 , G06F1/26
CPC分类号： G06F1/3209 , G06F1/3203 , G06F1/3287 , Y02B60/1282 , Y02B60/32
摘要： A computer system having a responsive low-power mode and a full-power mode of operation. The computer system includes a power consumption controller, a processor and a communication device. The power consumption controller generates an interrupt signal in response to a low power event or a fully operational event. The power consumption controller also generates a clock control signal. The clock control signal is deasserted during the full-power mode of operation and alternatively asserted for a first duration and deasserted for a second duration during the low-power mode of operation. In response to an asserted clock control signal, the processor suppresses the internal clock signal to at least one functional block within the processor and in response to a deasserted clock control signal, the processor transmits the internal clock signal to at least one functional block within the processor. By transmitting the internal clock signal to at least one functional block within the processor during the low-power mode of operation, the processor may respond to communication signals from a communication device during the low-power mode of operation.
摘要翻译：一种具有响应低功率模式和全功率工作模式的计算机系统。计算机系统包括功率消耗控制器，处理器和通信设备。功率消耗控制器响应于低功率事件或完全运行的事件而产生中断信号。功耗控制器还产生时钟控制信号。时钟控制信号在全功率工作模式期间被断言，并且在低功率操作模式期间另行断言第一持续时间并且断言第二持续时间。响应于断言的时钟控制信号，处理器将内部时钟信号抑制到处理器内的至少一个功能块，并且响应于无效时钟控制信号，处理器将内部时钟信号发送到内部时钟信号中的至少一个功能块处理器。通过在低功率操作模式期间将内部时钟信号发送到处理器内的至少一个功能块，处理器可以在低功率操作模式期间响应来自通信设备的通信信号。

15. 发明授权

US08522063B2 Non main CPU/OS based operational environment 有权
公开(公告)号：US08522063B2
公开(公告)日：2013-08-27
申请号：US13454993
申请日：2012-04-24
申请人： James P. Kardach , Brian V. Belmont , Muthu K. Kumar , Riley W. Jackson , Gunner Danneels , Richard A. Forand , Vivek Gupta , Jeffrey L. Huckins , Kristoffer D. Flemming , Uma M. Gadamsetty
发明人： James P. Kardach , Brian V. Belmont , Muthu K. Kumar , Riley W. Jackson , Gunner Danneels , Richard A. Forand , Vivek Gupta , Jeffrey L. Huckins , Kristoffer D. Flemming , Uma M. Gadamsetty
IPC分类号： G06F1/00 , H04B1/38
CPC分类号： G06F1/3296 , G06F1/266 , G06F1/3203 , G06F1/3293 , G06F13/102 , G06F13/4072 , G10L19/04 , H04R1/1091 , H04R2201/109 , Y02D10/122 , Y02D10/151 , Y02D50/20
摘要： A computing system is described that includes a main system bus that remains active while said computing system operates within a non main CPU/OS based operational state. The computing system also includes a controller that operates functional tasks while the computing system is within the non main CPU/OS based operational state. The computing system also includes an I/O unit coupled to the main system bus that remains active while the computing system operates within the non main CPU/OS based operational state.

16. 发明申请

US20120210036A1 NON MAIN CPU/OS BASED OPERATIONAL ENVIRONMENT 有权
标题翻译：非主CPU /操作系统的操作环境
公开(公告)号：US20120210036A1
公开(公告)日：2012-08-16
申请号：US13454993
申请日：2012-04-24
申请人： James P. Kardach , Brian V. Belmont , Muthu K. Kumar , Riley W. Jackson , Gunner Danneels , Richard A. Forand , Vivek Gupta , Jeffrey L. Huckins , Kristoffer D. Flemming , Uma M. Gadamsetty
发明人： James P. Kardach , Brian V. Belmont , Muthu K. Kumar , Riley W. Jackson , Gunner Danneels , Richard A. Forand , Vivek Gupta , Jeffrey L. Huckins , Kristoffer D. Flemming , Uma M. Gadamsetty
IPC分类号： G06F13/14
CPC分类号： G06F1/3296 , G06F1/266 , G06F1/3203 , G06F1/3293 , G06F13/102 , G06F13/4072 , G10L19/04 , H04R1/1091 , H04R2201/109 , Y02D10/122 , Y02D10/151 , Y02D50/20
摘要： A computing system is described that includes a main system bus that remains active while said computing system operates within a non main CPU/OS based operational state. The computing system also includes a controller that operates functional tasks while the computing system is within the non main CPU/OS based operational state. The computing system also includes an I/O unit coupled to the main system bus that remains active while the computing system operates within the non main CPU/OS based operational state.
摘要翻译：描述了一种计算系统，其包括在所述计算系统在基于非主CPU / OS的非操作状态下操作时保持活动的主系统总线。计算系统还包括在计算系统处于基于非主CPU / OS的非操作状态之内的情况下操作功能任务的控制器。计算系统还包括耦合到主系统总线的I / O单元，其在计算系统在基于非主CPU / OS的非主操作状态下运行时保持活动。

17. 发明授权

US07631199B2 Various methods and apparatuses for power states in a controller 失效
标题翻译：用于控制器中功率状态的各种方法和装置
公开(公告)号：US07631199B2
公开(公告)日：2009-12-08
申请号：US11173784
申请日：2005-06-30
申请人： James P. Kardach , Barnes Cooper , Seh Kwa , Animesh Mishra , Paul Diefenbaugh
发明人： James P. Kardach , Barnes Cooper , Seh Kwa , Animesh Mishra , Paul Diefenbaugh
IPC分类号： G06F1/00 , G06F1/32
CPC分类号： G06F1/3203 , G06F1/325
摘要： Various methods, apparatuses, and systems are described in which a chipset controller has circuitry to control communications with a peripheral device in a computing device. The chipset controller has logic configured 1) to detect a plug-in event when the peripheral device connects to the chipset controller and 2) to transition the chipset controller from a low power consumption state to a higher power consumption state based on the logic detecting the plug-in event.
摘要翻译：描述了各种方法，装置和系统，其中芯片组控制器具有控制与计算设备中的外围设备的通信的电路。芯片组控制器具有逻辑配置1）当外围设备连接到芯片组控制器时检测插件事件，以及2）基于逻辑检测来将芯片组控制器从低功耗状态转换到更高功耗状态插件事件。

18. 发明申请

US20090019185A1 Non Main CPU/OS Based Operational Environment 有权
标题翻译：非主CPU / OS操作环境
公开(公告)号：US20090019185A1
公开(公告)日：2009-01-15
申请号：US12235473
申请日：2008-09-22
申请人： James P. Kardach , Brian V. Belmont , Muthu K. Kumar , Riley W. Jackson , Gunner Danneels , Richard A. Forand , Vivek Gupta , Jeffrey L. Huckins , Kristoffer D. Flemming , Uma M. Gadamsetty
发明人： James P. Kardach , Brian V. Belmont , Muthu K. Kumar , Riley W. Jackson , Gunner Danneels , Richard A. Forand , Vivek Gupta , Jeffrey L. Huckins , Kristoffer D. Flemming , Uma M. Gadamsetty
IPC分类号： G06F3/00
CPC分类号： G06F1/3296 , G06F1/266 , G06F1/3203 , G06F1/3293 , G06F13/102 , G06F13/4072 , G10L19/04 , H04R1/1091 , H04R2201/109 , Y02D10/122 , Y02D10/151 , Y02D50/20
摘要： A computing system is described that includes a main system bus that remains active while said computing system operates within a non main CPU/OS based operational state. The computing system also includes a controller that operates functional tasks while the computing system is within the non main CPU/OS based operational state. The computing system also includes an I/O unit coupled to the main system bus that remains active while the computing system operates within the non main CPU/OS based operational state.
摘要翻译：描述了一种计算系统，其包括在所述计算系统在基于非主CPU / OS的非操作状态下操作时保持活动的主系统总线。计算系统还包括在计算系统处于基于非主CPU / OS的非操作状态之内的情况下操作功能任务的控制器。计算系统还包括耦合到主系统总线的I / O单元，其在计算系统在基于非主CPU / OS的非主操作状态下运行时保持活动。

19. 发明授权

US07454639B2 Various apparatuses and methods for reduced power states in system memory 有权
标题翻译：用于在系统存储器中降低功率状态的各种装置和方法
公开(公告)号：US07454639B2
公开(公告)日：2008-11-18
申请号：US11174060
申请日：2005-06-30
申请人： Sandeep Jain , James P. Kardach
发明人： Sandeep Jain , James P. Kardach
IPC分类号： G06F1/00 , G06F1/26 , G06F1/32
CPC分类号： G06F1/3275 , G06F1/3225 , Y02D10/14
摘要： A method, apparatus, and system are described in which a memory controller may have two or more registers to create and track zones of memory in a volatile memory device. The memory controller controls a power consumption state of a first zone of memory in the volatile memory device and a second zone of memory within the first volatile memory device on an individual basis; and one or more memory arrays contained within the first volatile memory device.
摘要翻译：描述了一种方法，装置和系统，其中存储器控制器可以具有两个或更多个寄存器来创建和跟踪易失性存储器设备中的存储器区域。存储器控制器在单独的基础上控制易失性存储器设备中的第一存储器区域和第一易失性存储器设备内的第二存储器区域的功耗状态; 以及包含在第一易失性存储器件内的一个或多个存储器阵列。

20. 发明授权

US07430673B2 Power management system for computing platform 有权
标题翻译：计算平台电源管理系统
公开(公告)号：US07430673B2
公开(公告)日：2008-09-30
申请号：US11173220
申请日：2005-06-30
申请人： James P. Kardach , Barnes Cooper , Paul Diefenbaugh , Seh Kwa , Animesh Mishra
发明人： James P. Kardach , Barnes Cooper , Paul Diefenbaugh , Seh Kwa , Animesh Mishra
IPC分类号： G06F1/00 , G06F1/26 , G06F1/32
CPC分类号： G06F1/3203 , G06F1/324 , G06F1/325 , Y02D10/126 , Y02D50/20
摘要： A power management system for a computing platform is described. In one embodiment, the power management system provides additional device states which the device controllers of the platform assume when the device controllers are operational but idle. These additional device states are states in which the device controller commits to certain types of inactivity. In another embodiment, the power management system provides additional platform modes which guarantee processor inactivity and/or deference of particular platform events while the mode is in effect.
摘要翻译：描述了一种用于计算平台的电源管理系统。在一个实施例中，电源管理系统提供当设备控制器可操作但空闲时，平台的设备控制器假设的附加设备状态。这些附加设备状态是设备控制器执行某些类型的不活动状态。在另一个实施例中，电源管理系统提供额外的平台模式，其在模式有效时保证处理器不活动和/或尊重特定平台事件。

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