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11. 发明申请

US20100158182A1 Method and System for Reducing Duty Cycle Distortion Amplification in Forwarded Clocks 有权
标题翻译：降低转发时钟占空比失真放大的方法和系统
公开(公告)号：US20100158182A1
公开(公告)日：2010-06-24
申请号：US12343426
申请日：2008-12-23
申请人： Drew G. Doblar , Dawei Huang , Deqiang Song
发明人： Drew G. Doblar , Dawei Huang , Deqiang Song
IPC分类号： H03D3/24
CPC分类号： H04L7/0008 , G06F1/10 , H04L25/061
摘要： A method and apparatus for reducing the amplification of the duty cycle distortion of high frequency clock signals when is provided. A data signal is sent to a receiver via a first channel. A clock signal is sent to the receiver via a second channel. The clock signal is filtered to substantially remove therefrom low frequency components before the clock signal is used by the receiver to recover data from the data signal.
摘要翻译：提供一种用于降低高频时钟信号的占空比失真的放大的方法和装置。数据信号通过第一通道发送到接收器。时钟信号通过第二通道发送到接收器。在时钟信号被接收机使用以从数据信号恢复数据之前，时钟信号被滤波以基本上从其中去除低频分量。

12. 发明授权

US08599909B2 Serial link voltage margin determination in mission mode 有权
标题翻译：任务模式下的串行链路电压裕度确定
公开(公告)号：US08599909B2
公开(公告)日：2013-12-03
申请号：US12850535
申请日：2010-08-04
申请人： Drew G. Doblar , Dawei Huang , Deqiang Song
发明人： Drew G. Doblar , Dawei Huang , Deqiang Song
IPC分类号： H04B3/46
CPC分类号： H04L25/03057 , H04L25/061 , H04L25/14
摘要： This disclosure describes systems and methods for determining a voltage margin (or margin) of a serializer/deserializer (SerDes) receiver in mission mode using a SerDes receiver. This is done by time-division multiplexing a margin determination and a tap weight adaptation onto the same hardware (or software, or combination of hardware and software). In other words, some parts of a SerDes receiver (e.g., an error slicer and an adaptation module) can be used for two different tasks at different times without degrading the effectiveness or bandwidth of the receiver. Hence, the disclosed systems and methods allow a SerDes receiver to determine the SerDes margin in mission mode and without any additional hardware or circuitry on the receiver chip.
摘要翻译：本公开描述了使用SerDes接收机在任务模式下确定串行器/解串器（SerDes）接收器的电压余量（或余量）的系统和方法。这通过在相同的硬件（或软件或硬件和软件的组合）上进行裕度确定和抽头权重适配的时分复用来完成。换句话说，SerDes接收机的一些部分（例如，错误限制器和适配模块）可以在不同的时间用于两个不同的任务，而不降低接收机的有效性或带宽。因此，所公开的系统和方法允许SerDes接收机在任务模式下确定SerDes余量，并且在接收器芯片上没有任何额外的硬件或电路。

13. 发明授权

US08446985B2 Method and system for reducing duty cycle distortion amplification in forwarded clocks 有权
标题翻译：用于减少转发时钟中占空比失真放大的方法和系统
公开(公告)号：US08446985B2
公开(公告)日：2013-05-21
申请号：US12343426
申请日：2008-12-23
申请人： Drew G. Doblar , Dawei Huang , Deqiang Song
发明人： Drew G. Doblar , Dawei Huang , Deqiang Song
IPC分类号： H03H7/30 , H03H7/40 , H03K5/159
CPC分类号： H04L7/0008 , G06F1/10 , H04L25/061
摘要： A method and apparatus for reducing the amplification of the duty cycle distortion of high frequency clock signals when is provided. A data signal is sent to a receiver via a first channel. A clock signal is sent to the receiver via a second channel. The clock signal is filtered to substantially remove therefrom low frequency components before the clock signal is used by the receiver to recover data from the data signal.
摘要翻译：提供一种用于降低高频时钟信号的占空比失真的放大的方法和装置。数据信号通过第一通道发送到接收器。时钟信号通过第二通道发送到接收器。在时钟信号被接收机使用以从数据信号恢复数据之前，时钟信号被滤波以基本上从其中去除低频分量。

14. 发明申请

US20090238318A1 MECHANISM FOR CONSTRUCTING AN OVERSAMPLED WAVEFORM FOR A SET OF SIGNALS RECEIVED BY A RECEIVER 有权
标题翻译：用于构造接收器接收到的一组信号的OVERSAMPED WAVEFORM的机制
公开(公告)号：US20090238318A1
公开(公告)日：2009-09-24
申请号：US12053121
申请日：2008-03-21
申请人： Deqiang Song , Dawei Huang , Drew G. Doblar , Michael Stephen Harwood , Nirmal C. Warke
发明人： Deqiang Song , Dawei Huang , Drew G. Doblar , Michael Stephen Harwood , Nirmal C. Warke
IPC分类号： H04L7/00
CPC分类号： H04L25/068
摘要： A mechanism is provided for constructing an oversampled waveform for a set of incoming signals received by a receiver. In one implementation, the oversampled waveform is constructed by way of cooperation between the receiver and a waveform construction mechanism (WCM). The receiver receives the incoming signals, samples a subset of the incoming signals at a time, stores the subsets of sample values into a set of registers, and subsequently provides the subsets of sample values to the WCM. The WCM in turn sorts through the subsets of sample values, organizes them into proper orders, and “stitches” them together to construct the oversampled waveform for the set of incoming signals. With proper cooperation between the receiver and the WCM, and with proper processing logic on the WCM, it is possible to construct the oversampled waveform for the incoming signals without requiring large amounts of resources on the receiver.
摘要翻译：提供了一种用于为接收机接收的一组输入信号构造过采样波形的机制。在一个实现中，过采样波形通过接收器和波形构造机构（WCM）之间的协作来构造。接收机接收输入信号，一次对入局信号的子集进行采样，将样本值的子集存储到一组寄存器中，随后将样本值的子集提供给WCM。 WCM依次对样本值的子集进行排序，将它们组织成正确的顺序，并将它们“缝合”在一起，以构成输入信号集合的过采样波形。通过接收机和WCM之间的适当协作，并且在WCM上具有适当的处理逻辑，可以为输入信号构造过采样波形，而不需要接收机上的大量资源。

15. 发明授权

US08634500B2 Direct feedback equalization with dynamic referencing 有权
标题翻译：直接反馈均衡与动态参考
公开(公告)号：US08634500B2
公开(公告)日：2014-01-21
申请号：US13431009
申请日：2012-03-27
申请人： Zuxu Qin , Rajesh Kumar , Dawei Huang , Jing Shi , Deqiang Song
发明人： Zuxu Qin , Rajesh Kumar , Dawei Huang , Jing Shi , Deqiang Song
IPC分类号： H03K9/00
CPC分类号： H04L25/062 , H04L2025/0349
摘要： A receiver circuit includes a first slicer coupled to receive data signals from a signal path and a reference voltage from a reference voltage path that is separate from the signal path. The first slicer is configured output a logic value based on a comparison between a voltage of the data signal and the reference voltage. The receiver circuit further includes a reference voltage generator configured to generate the reference voltage. The reference voltage generator is configured to dynamically generate the reference voltage based on logic values of previously received signals during operation in a first mode. During operation in a second mode, the reference voltage generator is configured to generate and provide the reference voltage as a static voltage.
摘要翻译：接收器电路包括耦合以从信号路径接收数据信号的第一限幅器和与信号路径分离的参考电压路径的参考电压。第一限幅器被配置为基于数据信号的电压与参考电压之间的比较来输出逻辑值。接收器电路还包括被配置为产生参考电压的参考电压发生器。参考电压发生器被配置为基于在第一模式中的操作期间先前接收到的信号的逻辑值来动态地产生参考电压。在第二模式的操作期间，参考电压发生器被配置为产生并提供参考电压作为静态电压。

16. 发明申请

US20130259162A1 Direct Feedback Equalization with Dynamic Referencing 有权
标题翻译：直接反馈均衡与动态参考
公开(公告)号：US20130259162A1
公开(公告)日：2013-10-03
申请号：US13431009
申请日：2012-03-27
申请人： Zuxu Qin , Rajesh Kumar , Dawei Huang , Jing Shi , Deqiang Song
发明人： Zuxu Qin , Rajesh Kumar , Dawei Huang , Jing Shi , Deqiang Song
IPC分类号： H04L25/10 , H04B1/16
CPC分类号： H04L25/062 , H04L2025/0349
摘要： A receiver circuit includes a first slicer coupled to receive data signals from a signal path and a reference voltage from a reference voltage path that is separate from the signal path. The first slicer is configured output a logic value based on a comparison between a voltage of the data signal and the reference voltage. The receiver circuit further includes a reference voltage generator configured to generate the reference voltage. The reference voltage generator is configured to dynamically generate the reference voltage based on logic values of previously received signals during operation in a first mode. During operation in a second mode, the reference voltage generator is configured to generate and provide the reference voltage as a static voltage.
摘要翻译：接收器电路包括耦合以从信号路径接收数据信号的第一限幅器和与信号路径分离的参考电压路径的参考电压。第一限幅器被配置为基于数据信号的电压与参考电压之间的比较来输出逻辑值。接收器电路还包括被配置为产生参考电压的参考电压发生器。参考电压发生器被配置为基于在第一模式中的操作期间先前接收到的信号的逻辑值来动态地产生参考电压。在第二模式的操作期间，参考电压发生器被配置为产生并提供参考电压作为静态电压。

17. 发明授权

US08249188B2 Mechanism for constructing an oversampled waveform for a set of signals received by a receiver 有权
标题翻译：用于为接收机接收的一组信号构造过采样波形的机制
公开(公告)号：US08249188B2
公开(公告)日：2012-08-21
申请号：US13175589
申请日：2011-07-01
申请人： Deqiang Song , Dawei Huang , Drew G. Doblar , Michael Stephen Harwood , Nirmal C. Warke
发明人： Deqiang Song , Dawei Huang , Drew G. Doblar , Michael Stephen Harwood , Nirmal C. Warke
IPC分类号： H04L27/00
CPC分类号： H04L25/068
摘要： A mechanism is provided for constructing an oversampled waveform for a set of incoming signals received by a receiver. In one implementation, the oversampled waveform is constructed by way of cooperation between the receiver and a waveform construction mechanism (WCM). The receiver receives the incoming signals, samples a subset of the incoming signals at a time, stores the subsets of sample values into a set of registers, and subsequently provides the subsets of sample values to the WCM. The WCM in turn sorts through the subsets of sample values, organizes them into proper orders, and “stitches” them together to construct the oversampled waveform for the set of incoming signals. With proper cooperation between the receiver and the WCM, and with proper processing logic on the WCM, it is possible to construct the oversampled waveform for the incoming signals without requiring large amounts of resources on the receiver.
摘要翻译：提供了一种用于为接收机接收的一组输入信号构造过采样波形的机制。在一个实现中，过采样波形通过接收器和波形构造机构（WCM）之间的协作来构造。接收机接收输入信号，一次对入局信号的子集进行采样，将样本值的子集存储到一组寄存器中，随后将样本值的子集提供给WCM。 WCM依次对样本值的子集进行排序，将它们组织成正确的顺序，并将它们“缝合”在一起，以构成输入信号集合的过采样波形。通过接收机和WCM之间的适当协作，并且在WCM上具有适当的处理逻辑，可以为输入信号构造过采样波形，而不需要接收机上的大量资源。

18. 发明申请

US20110150060A1 Voltage Margin Monitoring for an ADC-Based Serializer/Deserializer in Mission Mode 审中-公开
标题翻译：任务模式下基于ADC的串行器/解串器的电压裕度监控
公开(公告)号：US20110150060A1
公开(公告)日：2011-06-23
申请号：US12645612
申请日：2009-12-23
申请人： Dawei Huang , Deqiang Song , Drew G. Doblar , Agustin Del Alamo
发明人： Dawei Huang , Deqiang Song , Drew G. Doblar , Agustin Del Alamo
IPC分类号： H04B17/00 , H04L27/01
CPC分类号： H04L25/03057
摘要： Various embodiments herein include one or more of systems, methods, software, and/or data structures to determine voltage margin for a high-speed serial data link. Advantageously, the margin determination may be made during normal operation of the data link (“mission mode”) such that the performance of the data link is not affected by the voltage margin measurements. That is, the margin measurements may be performed “on line” rather than “off line.” To facilitate the voltage margin measurement, a plurality of digital samples from an analog to digital converter (ADC) may be evaluated to determine the most probable bit values (i.e., digital 1's and 0's) that are represented by the digital samples. Then, a method may be used to remove or compensate for ISI effects from one or more of the digital samples, thereby providing an accurate representation of the voltage margin present in a data link. Subsequently, the voltage margin may be periodically monitored over time to detect degradation of the data link.
摘要翻译：本文的各种实施例包括用于确定高速串行数据链路的电压裕度的系统，方法，软件和/或数据结构中的一个或多个。有利地，可以在数据链路的正常操作期间（“任务模式”）进行裕量确定，使得数据链路的性能不受电压余量测量的影响。也就是说，边沿测量可以“在线”而不是“离线”执行。为了便于测量电压裕度，可以评估来自模数转换器（ADC）的多个数字样本以确定最可能的位由数字样本表示的值（即数字1和0）。然后，可以使用一种方法去除或补偿来自一个或多个数字样本的ISI效应，从而提供数据链路中存在的电压余量的精确表示。随后，可以随时间周期地监视电压裕度，以检测数据链路的劣化。

19. 发明申请

US20120033685A1 SERIAL LINK VOLTAGE MARGIN DETERMINATION IN MISSION MODE 有权
标题翻译：在任务模式下串行链路电压测量
公开(公告)号：US20120033685A1
公开(公告)日：2012-02-09
申请号：US12850535
申请日：2010-08-04
申请人： Drew G. Doblar , Dawei Huang , Deqiang Song
发明人： Drew G. Doblar , Dawei Huang , Deqiang Song
IPC分类号： H04J3/04 , G01R19/00
CPC分类号： H04L25/03057 , H04L25/061 , H04L25/14
摘要： This disclosure describes systems and methods for determining a voltage margin (or margin) of a serializer/deserializer (SerDes) receiver in mission mode using a SerDes receiver. This is done by time-division multiplexing a margin determination and a tap weight adaptation onto the same hardware (or software, or combination of hardware and software). In other words, some parts of a SerDes receiver (e.g., an error slicer and an adaptation module) can be used for two different tasks at different times without degrading the effectiveness or bandwidth of the receiver. Hence, the disclosed systems and methods allow a SerDes receiver to determine the SerDes margin in mission mode and without any additional hardware or circuitry on the receiver chip.
摘要翻译：本公开描述了使用SerDes接收机在任务模式下确定串行器/解串器（SerDes）接收器的电压余量（或余量）的系统和方法。这通过在相同的硬件（或软件或硬件和软件的组合）上进行裕度确定和抽头权重适配的时分复用来完成。换句话说，SerDes接收机的一些部分（例如，错误限制器和适配模块）可以在不同的时间用于两个不同的任务，而不降低接收机的有效性或带宽。因此，所公开的系统和方法允许SerDes接收机在任务模式下确定SerDes余量，并且在接收器芯片上没有任何额外的硬件或电路。

20. 发明申请

US20110261900A1 MECHANISM FOR CONSTRUCTING AN OVERSAMPLED WAVEFORM FOR A SET OF SIGNALS RECEIVED BY A RECEIVER 有权
标题翻译：用于构造接收器接收到的一组信号的OVERSAMPED WAVEFORM的机制
公开(公告)号：US20110261900A1
公开(公告)日：2011-10-27
申请号：US13175589
申请日：2011-07-01
申请人： Deqiang Song , Dawei Huang , Drew G. Doblar , Michael Stephen Harwood , Nirmal C. Warke
发明人： Deqiang Song , Dawei Huang , Drew G. Doblar , Michael Stephen Harwood , Nirmal C. Warke
IPC分类号： H04L27/00
CPC分类号： H04L25/068
摘要： A mechanism is provided for constructing an oversampled waveform for a set of incoming signals received by a receiver. In one implementation, the oversampled waveform is constructed by way of cooperation between the receiver and a waveform construction mechanism (WCM). The receiver receives the incoming signals, samples a subset of the incoming signals at a time, stores the subsets of sample values into a set of registers, and subsequently provides the subsets of sample values to the WCM. The WCM in turn sorts through the subsets of sample values, organizes them into proper orders, and “stitches” them together to construct the oversampled waveform for the set of incoming signals. With proper cooperation between the receiver and the WCM, and with proper processing logic on the WCM, it is possible to construct the oversampled waveform for the incoming signals without requiring large amounts of resources on the receiver.
摘要翻译：提供了一种用于为接收机接收的一组输入信号构造过采样波形的机制。在一个实现中，过采样波形通过接收器和波形构造机构（WCM）之间的协作来构造。接收机接收输入信号，一次对入局信号的子集进行采样，将样本值的子集存储到一组寄存器中，随后将样本值的子集提供给WCM。 WCM依次对样本值的子集进行排序，将它们组织成正确的顺序，并将它们“缝合”在一起，以构成输入信号集合的过采样波形。通过接收机和WCM之间的适当协作，并且在WCM上具有适当的处理逻辑，可以为输入信号构造过采样波形，而不需要接收机上的大量资源。

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