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11. 发明授权

US07930531B2 Multi-partition USB device that re-boots a PC to an alternate operating system for virus recovery 有权
标题翻译：多分区USB设备，将PC重新启动到备用操作系统进行病毒恢复
公开(公告)号：US07930531B2
公开(公告)日：2011-04-19
申请号：US11838192
申请日：2007-08-13
申请人： David Q. Chow , Charles C. Lee , Frank Yu , Tzu-Yih Chu , Ming-Shiang Shen
发明人： David Q. Chow , Charles C. Lee , Frank Yu , Tzu-Yih Chu , Ming-Shiang Shen
IPC分类号： G06F1/00
CPC分类号： G06F21/568 , G06F21/575 , G06F2221/2105 , G06F2221/2153
摘要： A multi-partition Universal Serial Bus (USB) device has a flash memory with multiple partitions of storage. Some partitions are for different operating systems and store OS images. Another partition has a control program while a user partition stores user data and user configuration information. The control program can test the multi-partition USB device and instruct the host computer BIOS to mount a partition from its flash memory as a drive of the host computer. The host computer can then be rebooted. The OS image from the flash memory is loaded into main memory during rebooting, and the host computer executes a new operating system using the new OS image. The user can press buttons on the multi-partition USB device to select which OS to load, and to begin rebooting. Virus removal programs in the alternate OS can help recover from a virus in the primary OS.
摘要翻译：多分区通用串行总线（USB）设备具有具有多个存储分区的闪存。一些分区用于不同的操作系统并存储操作系统映像。另一个分区具有控制程序，而用户分区则存储用户数据和用户配置信息。控制程序可以测试多分区USB设备，并指示主机BIOS将其闪存中的分区作为主机的驱动器安装。然后可以重新启动主机。重新启动时，闪存中的OS映像将加载到主内存中，主机使用新的操作系统映像执行新的操作系统。用户可以按多分区USB设备上的按钮选择要加载的操作系统，并开始重新启动。备用操作系统中的病毒清除程序可以帮助从主操作系统中的病毒恢复。

12. 发明申请

US20080198545A1 Open-frame solid-state drive housing with intrinsic grounding to protect exposed chips 失效
标题翻译：开放式固态驱动器外壳，具有固有的接地保护裸露的芯片
公开(公告)号：US20080198545A1
公开(公告)日：2008-08-21
申请号：US12043398
申请日：2008-03-06
申请人： Jim Chin-Nan Ni , Charles C. Lee , Frank Yu , Abraham C. Ma , Ming-Shiang Shen
发明人： Jim Chin-Nan Ni , Charles C. Lee , Frank Yu , Abraham C. Ma , Ming-Shiang Shen
IPC分类号： G06F1/16
CPC分类号： G06F12/1416 , G06F3/0658 , G06F3/0679 , G06F21/32 , G06F21/78
摘要： An open-frame flash-memory drive has a printed-circuit board assembly (PCBA) with flash-memory chips, a controller chip, and a Serial AT-Attachment (SATA) connector soldered to it. The PCBA is only partially encased by left and right frames or by a U-shaped bracket frame. The frames have PCBA supports and guide posts that fit near edges of the PCBA. The frames do not cover the top and bottom of the PCBA, allowing chips on the PCBA to be ventilated by unblocked air flow. Screws that attach the PCBA to the frame have metal collars that ground the frame to the PCBA's ground plane. The screws form a current path to draw any electro-static-discharge (ESD) current off the frame and onto a PCBA ground. When the SATA connector is inserted into a host, the host ground sinks ESD currents collected by the open frame.
摘要翻译：开放式闪存驱动器具有焊接到其上的具有闪存芯片的印刷电路板组件（PCBA），控制器芯片和串行AT附件（SATA）连接器。 PCBA仅部分地被左右框架或U形支架框架包围。这些框架具有PCBA支撑和适合PCBA边缘附近的导向柱。框架不覆盖PCBA的顶部和底部，允许PCBA上的芯片通过未阻塞的气流通风。将PCBA连接到框架上的螺钉具有金属套环，将框架接地到PCBA的接地平面。螺钉形成电流通道，以将任何静电放电（ESD）电流从框架上取出并插入PCBA接地。当SATA连接器插入主机时，主机接地会吸收由开放框架收集的ESD电流。

13. 发明授权

US07333364B2 Cell-downgrading and reference-voltage adjustment for a multi-bit-cell flash memory 失效
标题翻译：针对多位单元闪存的单元降级和参考电压调整
公开(公告)号：US07333364B2
公开(公告)日：2008-02-19
申请号：US11737336
申请日：2007-04-19
申请人： Frank Yu , Charles C. Lee , Abraham C. Ma , Ming-Shiang Shen
发明人： Frank Yu , Charles C. Lee , Abraham C. Ma , Ming-Shiang Shen
IPC分类号： G11C16/06
CPC分类号： G11C11/5621 , G11C11/5642 , G11C29/00 , G11C2211/5634 , G11C2211/5641
摘要： A flash memory has multi-level cells (MLC) that can each store multiple bits per cell. Blocks of cells can be downgraded to fewer bits/cell when errors occur, or for storing critical data such as boot code. The bits from a single MLC are partitioned among multiple pages to improve error correctability using Error Correction Code (ECC). An upper reference voltage is generated by a voltage reference generator in response to calibration registers that can be programmed to alter the upper reference voltage. A series of decreasing references are generated from the upper reference voltage and are compared to a bit-line voltage. Compare results are translated by translation logic that generates read data and over- and under-programming signals. Downgraded cells use the same truth table but generate fewer read data bits. Noise margins are asymmetrically improved by using the same sub-states for reading downgraded and full-density MLC cells.
摘要翻译：闪存具有多级单元（MLC），每个单元可以存储多个位。当发生错误时，单元块可以降级到较少的位/单元，或用于存储关键数据（如引导代码）。来自单个MLC的位在多个页面之间进行分区，以使用错误校正码（ECC）来提高错误的可校正性。响应于校准寄存器，由参考电压发生器产生较高的参考电压，校准寄存器可编程为改变上参考电压。从较高参考电压产生一系列减小的参考值，并将其与位线电压进行比较。比较结果由翻译逻辑翻译，生成读取数据和编程过程中和编程不足的信号。降级的单元格使用相同的真值表，但生成较少的读取数据位。通过使用相同的子状态来读取降级和全密度MLC单元，噪声余量被不对称地改善。

14. 发明授权

US07620769B2 Recycling partially-stale flash blocks using a sliding window for multi-level-cell (MLC) flash memory 失效
标题翻译：使用多层单元（MLC）闪存的滑动窗口回收部分陈旧的闪存块
公开(公告)号：US07620769B2
公开(公告)日：2009-11-17
申请号：US11674645
申请日：2007-02-13
申请人： Charles C. Lee , Frank Yu , Abraham C. Ma , Ming-Shiang Shen
发明人： Charles C. Lee , Frank Yu , Abraham C. Ma , Ming-Shiang Shen
IPC分类号： G06F12/02
CPC分类号： H01R13/629 , G06F12/0246 , G06F12/1416 , G06F21/32 , G06F21/78 , G06F2212/1044 , G06F2212/7201 , G06F2212/7205 , G06F2212/7209 , G06K9/00087 , G06K19/07 , G06K19/07354 , G07C9/00087
摘要： A sliding window of flash blocks is used to reduce wasted space occupied by stale data in a flash memory. The sliding window slides downward over a few flash blocks. The oldest block is examined for valid pages of data, and the valid pages are copied to the end of the sliding window so that the first block has only stale pages. The first block can then be erased and eventually re-used. A RAM usage table contains valid bits for pages in each block in the sliding window. A page's valid bit is changed from an erased, unwritten state to a valid state when data is written to the page. Later, when new host data replaces that data, the old page's valid bit is set to the stale state. A RAM stale-flags table keeps track of pages that are full of stale pages.
摘要翻译：闪存块的滑动窗口用于减少闪存中过时数据占用的浪费空间。滑动窗口向下滑过几个闪光块。检查最旧的块是否有效的数据页面，有效的页面被复制到滑动窗口的末尾，以便第一个块只有过时的页面。然后可以擦除第一个块并最终重新使用。 RAM使用表包含滑动窗口中每个块中页面的有效位。当数据写入页面时，页面的有效位从擦除的未写入状态更改为有效状态。之后，当新的主机数据替换该数据时，旧页面的有效位被设置为陈旧状态。 RAM陈旧标记表可以跟踪页面中已经有过时的页面。

15. 发明授权

US07649743B2 Open-frame solid-state drive housing with intrinsic grounding to protect exposed chips 失效
标题翻译：开放式固态驱动器外壳，具有固有的接地保护裸露的芯片
公开(公告)号：US07649743B2
公开(公告)日：2010-01-19
申请号：US12043398
申请日：2008-03-06
申请人： Jim Chin-Nan Ni , Charles C. Lee , Frank Yu , Abraham C. Ma , Ming-Shiang Shen
发明人： Jim Chin-Nan Ni , Charles C. Lee , Frank Yu , Abraham C. Ma , Ming-Shiang Shen
IPC分类号： H05K5/00
CPC分类号： G06F12/1416 , G06F3/0658 , G06F3/0679 , G06F21/32 , G06F21/78
摘要： An open-frame flash-memory drive has a printed-circuit board assembly (PCBA) with flash-memory chips, a controller chip, and a Serial AT-Attachment (SATA) connector soldered to it. The PCBA is only partially encased by left and right frames or by a U-shaped bracket frame. The frames have PCBA supports and guide posts that fit near edges of the PCBA. The frames do not cover the top and bottom of the PCBA, allowing chips on the PCBA to be ventilated by unblocked air flow. Screws that attach the PCBA to the frame have metal collars that ground the frame to the PCBA's ground plane. The screws form a current path to draw any electro-static-discharge (ESD) current off the frame and onto a PCBA ground. When the SATA connector is inserted into a host, the host ground sinks ESD currents collected by the open frame.
摘要翻译：开放式闪存驱动器具有焊接到其上的具有闪存芯片的印刷电路板组件（PCBA），控制器芯片和串行AT附件（SATA）连接器。 PCBA仅部分地被左右框架或U形支架框架包围。这些框架具有PCBA支撑和适合PCBA边缘附近的导向柱。框架不覆盖PCBA的顶部和底部，允许PCBA上的芯片通过未阻塞的气流通风。将PCBA连接到框架上的螺钉具有金属套环，将框架接地到PCBA的接地平面。螺钉形成电流通道，以将任何静电放电（ESD）电流从框架上取出并插入PCBA接地。当SATA连接器插入主机时，主机接地会吸收由开放框架收集的ESD电流。

16. 发明申请

US20080320214A1 Multi-Level Controller with Smart Storage Transfer Manager for Interleaving Multiple Single-Chip Flash Memory Devices 有权
标题翻译：具有智能存储传输管理器的多级控制器，用于交错多个单片闪存器件
公开(公告)号：US20080320214A1
公开(公告)日：2008-12-25
申请号：US12186471
申请日：2008-08-05
申请人： Abraham C. Ma , David Q. Chow , Charles C. Lee , Frank Yu
发明人： Abraham C. Ma , David Q. Chow , Charles C. Lee , Frank Yu
IPC分类号： G06F12/02
CPC分类号： G06F12/0246 , G06F3/0613 , G06F3/0616 , G06F3/064 , G06F3/0658 , G06F3/0664 , G06F3/0688 , G06F2212/7201 , G06F2212/7208 , G06F2212/7211 , G11C13/0004
摘要： A solid-state disk (SSD) has a smart storage switch with a smart storage transaction manager that re-orders host commands for accessing downstream single-chip flash-memory devices. Each single-chip flash-memory device has a lower-level controller that converts logical block addresses (LBA) to physical block addresses (PBA) that access flash memory blocks in the single-chip flash-memory device. Wear-leveling and bad block remapping are preformed by each single-chip flash-memory device, and at a higher level by a virtual storage processor in the smart storage switch. Virtual storage bridges between the smart storage transaction manager and the single-chip flash-memory devices bridge LBA transactions over LBA buses to the single-chip flash-memory devices. Data striping and interleaving among multiple channels of the single-chip flash-memory device is controlled at a high level by the smart storage transaction manager, while further interleaving and remapping may be performed within each single-chip flash-memory device.
摘要翻译：固态磁盘（SSD）具有智能存储交换机，智能存储交易管理器重新命令用于访问下游单芯片闪存设备的主机命令。每个单芯片闪存设备具有将逻辑块地址（LBA）转换为访问单芯片闪存设备中的闪存块的物理块地址（PBA）的较低级别的控制器。磨损均衡和坏块重映射由每个单芯片闪存设备执行，并且在智能存储交换机中的虚拟存储处理器处于更高级别。智能存储事务管理器和单芯片闪存设备之间的虚拟存储网桥将LBA总线上的LBA交易桥接到单芯片闪存设备。单芯片闪速存储器件的多个通道之间的数据条带化和交错由智能存储事务管理器控制在高电平，而可以在每个单芯片闪速存储器件内执行进一步的交错和重新映射。

17. 发明授权

US08341332B2 Multi-level controller with smart storage transfer manager for interleaving multiple single-chip flash memory devices 有权
标题翻译：具有智能存储传输管理器的多电平控制器，用于交错多个单芯片闪存设备
公开(公告)号：US08341332B2
公开(公告)日：2012-12-25
申请号：US12186471
申请日：2008-08-05
申请人： Abraham C. Ma , David Q. Chow , Charles C. Lee , Frank Yu
发明人： Abraham C. Ma , David Q. Chow , Charles C. Lee , Frank Yu
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28
CPC分类号： G06F12/0246 , G06F3/0613 , G06F3/0616 , G06F3/064 , G06F3/0658 , G06F3/0664 , G06F3/0688 , G06F2212/7201 , G06F2212/7208 , G06F2212/7211 , G11C13/0004
摘要： A solid-state disk (SSD) has a smart storage switch with a smart storage transaction manager that re-orders host commands for accessing downstream single-chip flash-memory devices. Each single-chip flash-memory device has a lower-level controller that converts logical block addresses (LBA) to physical block addresses (PBA) that access flash memory blocks in the single-chip flash-memory device. Wear-leveling and bad block remapping are preformed by each single-chip flash-memory device, and at a higher level by a virtual storage processor in the smart storage switch. Virtual storage bridges between the smart storage transaction manager and the single-chip flash-memory devices bridge LBA transactions over LBA buses to the single-chip flash-memory devices. Data striping and interleaving among multiple channels of the single-chip flash-memory device is controlled at a high level by the smart storage transaction manager, while further interleaving and remapping may be performed within each single-chip flash-memory device.
摘要翻译：固态磁盘（SSD）具有智能存储交换机，智能存储交易管理器重新命令用于访问下游单芯片闪存设备的主机命令。每个单芯片闪存设备具有将逻辑块地址（LBA）转换为访问单芯片闪存设备中的闪存块的物理块地址（PBA）的较低级别的控制器。磨损均衡和坏块重映射由每个单芯片闪存设备执行，并且在智能存储交换机中的虚拟存储处理器处于更高级别。智能存储事务管理器和单芯片闪存设备之间的虚拟存储网桥将LBA总线上的LBA交易桥接到单芯片闪存设备。单芯片闪速存储器件的多个通道之间的数据条带化和交错由智能存储事务管理器控制在高电平，而可以在每个单芯片闪速存储器件内执行进一步的交错和重新映射。

18. 发明申请

US20100027329A1 Synchronous Page-Mode Phase-Change Memory with ECC and RAM Cache 失效
标题翻译：具有ECC和RAM缓存的同步页模式相变存储器
公开(公告)号：US20100027329A1
公开(公告)日：2010-02-04
申请号：US12579695
申请日：2009-10-15
申请人： Charles C. Lee , Frank Yu , David Q. Chow
发明人： Charles C. Lee , Frank Yu , David Q. Chow
IPC分类号： G11C11/00 , G11C7/10 , G11C7/00
CPC分类号： G11C8/08 , G11C8/06 , G11C8/12 , G11C11/5678 , G11C13/0004 , G11C13/0023 , G11C13/0028 , G11C13/0061 , G11C13/0069 , G11C2013/0071 , G11C2013/0085 , G11C2213/79
摘要： Phase-change memory (PCM) cells store data using alloy resistors in high-resistance amorphous and low-resistance crystalline states. The time of the memory cell's set-current pulse can be 100 ns, much longer than read or reset times. The write time thus depends on the write data and is relatively long. A page-mode caching PCM device has a lookup table (LUT) that caches write data that is later written to an array of PCM banks. Host data is latched into a line FIFO and written into the LUT, reducing write delays to the relatively slow PCM. Host read data can be supplied by the LUT or fetched from the PCM banks. A multi-line page buffer between the PCM banks and LUT allows for larger block transfers using the LUT. Error-correction code (ECC) checking and generation is performed for data in the LUT, hiding ECC delays for data writes into the PCM banks.
摘要翻译：相变存储器（PCM）单元使用高电阻非晶和低电阻晶体状态的合金电阻存储数据。存储单元的设定电流脉冲的时间可以是100 ns，比读取或复位时间长得多。因此，写入时间取决于写入数据并且相对较长。页面模式缓存PCM设备具有高速缓存写入数据的查找表（LUT），该数据稍后被写入PCM存储体阵列。主机数据被锁存到行FIFO中并写入LUT中，从而将写入延迟减少到相对较慢的PCM。主机读取数据可由LUT提供或从PCM存储区中提取。 PCM组和LUT之间的多行页面缓冲区允许使用LUT进行更大的块传输。对LUT中的数据执行纠错码（ECC）检查和生成，将ECC数据写入PCM存储体中隐藏ECC延迟。

19. 发明申请

US20080266991A1 Synchronous Page-Mode Phase-Change Memory with ECC and RAM Cache 失效
标题翻译：具有ECC和RAM缓存的同步页模式相变存储器
公开(公告)号：US20080266991A1
公开(公告)日：2008-10-30
申请号：US11769324
申请日：2007-06-27
申请人： Charles C. Lee , Frank Yu , David Q. Chow
发明人： Charles C. Lee , Frank Yu , David Q. Chow
IPC分类号： G11C29/00
CPC分类号： G11C7/1006 , G06F11/1044 , G11C7/1072 , G11C13/0004 , G11C13/004 , G11C13/0061 , G11C13/0069 , G11C2013/0085 , G11C2213/79
摘要： Phase-change memory (PCM) cells store data using alloy resistors in high-resistance amorphous and low-resistance crystalline states. The time of the memory cell's set-current pulse can be 100 ns, much longer than read or reset times. The write time thus depends on the write data and is relatively long. A page-mode caching PCM device has a lookup table (LUT) that caches write data that is later written to an array of PCM banks. Host data is latched into a line FIFO and written into the LUT, reducing write delays to the relatively slow PCM. Host read data can be supplied by the LUT or fetched from the PCM banks. A multi-line page buffer between the PCM banks and LUT allows for larger block transfers using the LUT. Error-correction code (ECC) checking and generation is performed for data in the LUT, hiding ECC delays for data writes into the PCM banks.
摘要翻译：相变存储器（PCM）单元使用高电阻非晶和低电阻晶体状态的合金电阻存储数据。存储单元的设定电流脉冲的时间可以是100 ns，比读取或复位时间长得多。因此，写入时间取决于写入数据并且相对较长。页面模式缓存PCM设备具有高速缓存写入数据的查找表（LUT），该数据稍后被写入PCM存储体阵列。主机数据被锁存到行FIFO中并写入LUT中，从而将写入延迟减少到相对较慢的PCM。主机读取数据可由LUT提供或从PCM存储区中提取。 PCM组和LUT之间的多行页面缓冲区允许使用LUT进行更大的块传输。对LUT中的数据执行纠错码（ECC）检查和生成，将ECC数据写入PCM存储体中隐藏ECC延迟。

20. 发明授权

US08452912B2 Flash-memory system with enhanced smart-storage switch and packed meta-data cache for mitigating write amplification by delaying and merging writes until a host read 有权
标题翻译：闪存系统具有增强的智能存储交换机和打包的元数据缓存，用于通过延迟和合并写入来缓解写入，直到主机读取
公开(公告)号：US08452912B2
公开(公告)日：2013-05-28
申请号：US12576216
申请日：2009-10-08
申请人： Charles C. Lee , Frank Yu , Abraham C. Ma
发明人： Charles C. Lee , Frank Yu , Abraham C. Ma
IPC分类号： G06F12/00
CPC分类号： G06F12/0246 , G06F12/0866 , G06F2212/1036 , G06F2212/214 , G06F2212/7203 , G06F2212/7207 , G11C13/0004 , G11C16/102 , G11C19/0808 , G11C2211/5641 , G11C2216/30
摘要： A flash memory solid-state-drive (SSD) has a smart storage switch that reduces write acceleration that occurs when more data is written to flash memory than is received from the host. Page mapping rather than block mapping reduces write acceleration. Host commands are loaded into a Logical-Block-Address (LBA) range FIFO. Entries are sub-divided and portions invalidated when a new command overlaps an older command in the FIFO. Host data is aligned to page boundaries with pre- and post-fetched data filling in to the boundaries. Repeated data patterns are detected and encoded by compressed meta-data codes that are stored in meta-pattern entries in a meta-pattern cache of a meta-pattern flash block. The sector data is not written to flash. The meta-pattern entries are located using a meta-data mapping table. Storing host CRC's for comparison to incoming host data can detect identical data writes that can be skipped, avoiding a write to flash.
摘要翻译：闪存固态驱动器（SSD）具有智能存储交换机，可以减少写入快速写入的速度，而写入速度会比从主机接收到的更多的数据写入闪存。页面映射而不是块映射减少写入加速。主机命令加载到逻辑块地址（LBA）范围FIFO中。当新命令与FIFO中的旧命令重叠时，条目被分割，部分无效。主机数据与页边界对齐，前后获取的数据填充到边界。通过存储在元模式闪存块的元模式高速缓存中的元模式条目中的压缩元数据代码来检测和编码重复的数据模式。扇区数据未写入闪存。使用元数据映射表定位元模式条目。存储主机CRC用于与传入主机数据进行比较可以检测可跳过的相同数据写入，避免写入闪存。

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