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11. 发明授权

US06781214B1 Metastable base in a high-performance HBT 有权
标题翻译：高性能HBT中的亚稳基础
公开(公告)号：US06781214B1
公开(公告)日：2004-08-24
申请号：US10313508
申请日：2002-12-06
申请人： Greg D. U'Ren , Klaus F. Schuegraf
发明人： Greg D. U'Ren , Klaus F. Schuegraf
IPC分类号： H01L27082
CPC分类号： H01L29/66242 , H01L21/8249 , H01L29/7378
摘要： According to one exemplary embodiment, a heterojunction bipolar transistor is fabricated by forming a metastable epitaxial silicon-germaniuim base on a collector. The metastable epitaxial silicon-germanium base, for example, may have a concentration of germanium greater than 20.0 atomic percent of germanium. The heterojunction bipolar transistor, for example, may be an NPN silicon-germanium heterojunction bipolar transistor. According to this exemplary embodiment, the heterojunction bipolar transistor is further fabricated by fabricating an emitter over the metastable epitaxial silicon-germanium base. The heterojunction bipolar transistor is further fabricated by doping the emitter with a first dopant. The first dopant, for example, may be arsenic. The heterojunction bipolar transistor is further fabricated by heating the metastable epitaxial silicon-germanium base in a spike anneal process so as to maintain the metastable epitaxial silicon-germanium base as a strained crystalline structure after the spike anneal process and so as to diffusion the first dopant to form emitter-base junction.
摘要翻译：根据一个示例性实施例，通过在集电极上形成亚稳态外延硅 - 锗化物基底来制造异质结双极晶体管。例如，亚稳态外延硅 - 锗基底可以具有大于锗原子％的锗的浓度。例如，异质结双极晶体管可以是NPN硅 - 锗异质结双极晶体管。根据该示例性实施例，通过在亚稳态外延硅 - 锗基底上制造发射极来进一步制造异质结双极晶体管。通过用第一掺杂剂掺杂发射极进一步制造异质结双极晶体管。例如，第一掺杂剂可以是砷。异质结双极晶体管通过在尖峰退火工艺中加热亚稳外延硅 - 锗基底进一步制造，以便在尖峰退火工艺之后将亚稳态外延硅 - 锗基底保持为应变结晶结构，并使第一掺杂剂以形成发射极 - 基极结。

12. 发明授权

US07291898B1 Selective and non-selective epitaxy for base integration in a BiCMOS process and related structure 有权
标题翻译：选择性和非选择性外延，用于BiCMOS工艺和相关结构中的基础整合
公开(公告)号：US07291898B1
公开(公告)日：2007-11-06
申请号：US11146537
申请日：2005-06-06
申请人： Greg D. U'Ren
发明人： Greg D. U'Ren
IPC分类号： H01L27/082 , H01L21/331
CPC分类号： H01L29/732 , H01L21/8249 , H01L29/1004 , H01L29/66287
摘要： According to one exemplary embodiment, a bipolar transistor includes an active area situated between first and second isolation regions in a substrate. The bipolar transistor further includes an epitaxial extension layer situated on the active area, where the epitaxial extension layer extends over the first and second isolation regions. The bipolar transistor further includes a base layer situated on the epitaxial extension layer, where the base layer includes an epitaxial base, and where the epitaxial base includes a usable emitter formation area. The active area has a first width and the usable emitter formation area has a second width, where the second width is at least as large as the first width.
摘要翻译：根据一个示例性实施例，双极晶体管包括位于衬底中的第一和第二隔离区之间的有源区。双极晶体管还包括位于有源区上的外延延伸层，其中外延延伸层在第一和第二隔离区上延伸。双极晶体管还包括位于外延延伸层上的基极层，其中基极层包括外延基极，并且其中外延基底包括可用的发射极形成区域。有源区域具有第一宽度，并且可用的发射体形成区域具有第二宽度，其中第二宽度至少与第一宽度一样大。

13. 发明授权

US06586297B1 Method for integrating a metastable base into a high-performance HBT and related structure 有权
标题翻译：将亚稳态基团整合为高性能HBT及相关结构的方法
公开(公告)号：US06586297B1
公开(公告)日：2003-07-01
申请号：US10160979
申请日：2002-06-01
申请人： Greg D. U'Ren , Klaus F. Schuegraf
发明人： Greg D. U'Ren , Klaus F. Schuegraf
IPC分类号： H01L218249
CPC分类号： H01L29/66242 , H01L21/8249 , H01L29/7378
摘要： According to one exemplary embodiment, a heterojunction bipolar transistor is fabricated by forming a metastable epitaxial silicon-germaniuim base on a collector. The metastable epitaxial silicon-gernaniuim base, for example, may have a concentration of germanium greater than 20.0 atomic percent of germanium. The heterojunction bipolar transistor, for example, may be an NPN silicon-germanium heterojunction bipolar transistor. According to this exemplary embodiment, the heterojunction bipolar transistor is further fabricated by fabricating an emitter over the metastable epitaxial silicongermanium base. The heterojunction bipolar transistor is further fabricated by doping the emitter with a first dopant. The first dopant, for example, may be arsenic. The heterojunction bipolar transistor is further fabricated by heating the metastable epitaxial silicon-germanium base in a spike anneal process so as to maintain the metastable epitaxial silicon-germanium base as a strained crystalline structure after the spike anneal process and so as to diffusion the first dopant to form emitter-base junction.
摘要翻译：根据一个示例性实施例，通过在集电极上形成亚稳态外延硅 - 锗化物基底来制造异质结双极晶体管。例如，亚稳态外延硅 - 锗镍基可以具有大于锗原子％的锗的浓度。例如，异质结双极晶体管可以是NPN硅 - 锗异质结双极晶体管。根据该示例性实施例，通过在亚稳态外延硅锗基底上制造发射极，进一步制造异质结双极晶体管。通过用第一掺杂剂掺杂发射极进一步制造异质结双极晶体管。例如，第一掺杂剂可以是砷。异质结双极晶体管通过在尖峰退火工艺中加热亚稳外延硅 - 锗基底进一步制造，以便在尖峰退火工艺之后将亚稳态外延硅 - 锗基底保持为应变结晶结构，并使第一掺杂剂以形成发射极 - 基极结。

14. 发明授权

US07795703B1 Selective and non-selective epitaxy for base intergration in a BiCMOS process 有权
标题翻译：选择性和非选择性外延，用于BiCMOS工艺中的基础整合
公开(公告)号：US07795703B1
公开(公告)日：2010-09-14
申请号：US12290987
申请日：2008-11-05
申请人： Greg D. U'Ren
发明人： Greg D. U'Ren
IPC分类号： H01L27/082
CPC分类号： H01L29/732 , H01L21/8249 , H01L29/1004 , H01L29/66287
摘要： According to one exemplary embodiment, a bipolar transistor includes an active area situated between first and second isolation regions in a substrate. The bipolar transistor further includes an epitaxial extension layer situated on the active area, where the epitaxial extension layer extends over the first and second isolation regions. The bipolar transistor further includes a base layer situated on the epitaxial extension layer, where the base layer includes an epitaxial base, and where the epitaxial base includes a usable emitter formation area. The active area has a first width and the usable emitter formation area has a second width, where the second width is at least as large as the first width.
摘要翻译：根据一个示例性实施例，双极晶体管包括位于衬底中的第一和第二隔离区之间的有源区。双极晶体管还包括位于有源区上的外延延伸层，其中外延延伸层在第一和第二隔离区上延伸。双极晶体管还包括位于外延延伸层上的基极层，其中基极层包括外延基极，并且其中外延基底包括可用的发射极形成区域。有源区域具有第一宽度，并且可用的发射体形成区域具有第二宽度，其中第二宽度至少与第一宽度一样大。

15. 发明授权

US07462923B1 Bipolar transistor formed using selective and non-selective epitaxy for base integration in a BiCMOS process 有权
标题翻译：使用选择性和非选择性外延法在BiCMOS工艺中进行基极整合形成的双极晶体管
公开(公告)号：US07462923B1
公开(公告)日：2008-12-09
申请号：US11899850
申请日：2007-09-08
申请人： Greg D. U'Ren
发明人： Greg D. U'Ren
IPC分类号： H01L27/082
CPC分类号： H01L29/732 , H01L21/8249 , H01L29/1004 , H01L29/66287
摘要： According to one exemplary embodiment, a bipolar transistor includes an active area situated between first and second isolation regions in a substrate. The bipolar transistor further includes an epitaxial extension layer situated on the active area, where the epitaxial extension layer extends over the first and second isolation regions. The bipolar transistor further includes a base layer situated on the epitaxial extension layer, where the base layer includes an epitaxial base, and where the epitaxial base includes a usable emitter formation area. The active area has a first width and the usable emitter formation area has a second width, where the second width is at least as large as the first width.
摘要翻译：根据一个示例性实施例，双极晶体管包括位于衬底中的第一和第二隔离区之间的有源区。双极晶体管还包括位于有源区上的外延延伸层，其中外延延伸层在第一和第二隔离区上延伸。双极晶体管还包括位于外延延伸层上的基极层，其中基极层包括外延基极，并且其中外延基底包括可用的发射极形成区域。有源区域具有第一宽度，并且可用的发射体形成区域具有第二宽度，其中第二宽度至少与第一宽度一样大。

16. 发明授权

US07335547B1 Method for effective BiCMOS process integration 有权
标题翻译：有效的BiCMOS过程集成方法
公开(公告)号：US07335547B1
公开(公告)日：2008-02-26
申请号：US11086168
申请日：2005-03-21
申请人： Greg D. U'Ren
发明人： Greg D. U'Ren
IPC分类号： H01L21/8238
CPC分类号： H01L21/8249 , H01L27/0623
摘要： According to an exemplary embodiment, a method for integrating bipolar and CMOS devices on a substrate, where the substrate includes bipolar and CMOS regions and has a sacrificial oxide layer situated thereon, includes removing a portion of the sacrificial oxide layer in the bipolar region of the substrate to expose a top surface of the substrate. The method includes forming a base layer on the top surface of the substrate in the bipolar region. The base layer forms a bipolar transistor base. The method further includes forming a sacrificial post on the base layer in the bipolar region and at least one gate electrode in the CMOS region of the substrate. A common mask is used to form the sacrificial post and the at least one gate electrode. The method further includes forming LDD regions adjacent to the at least one gate electrode in the CMOS region.
摘要翻译：根据示例性实施例，一种用于在衬底上积分双极和CMOS器件的方法，其中所述衬底包括双极和CMOS区域并且具有位于其上的牺牲氧化物层，包括去除所述牺牲氧化物层的一部分，衬底以暴露衬底的顶表面。该方法包括在双极区域中在衬底的顶表面上形成基底层。基极层形成双极晶体管基极。该方法还包括在双极区域的基底层上形成牺牲柱，以及在衬底的CMOS区域中形成至少一个栅电极。使用公共掩模来形成牺牲柱和至少一个栅电极。该方法还包括形成与CMOS区域中的至少一个栅电极相邻的LDD区域。

17. 发明授权

US07297992B1 Method and structure for integration of phosphorous emitter in an NPN device in a BiCMOS process 有权
标题翻译：在BiCMOS工艺中NPN器件中磷发生器的集成方法和结构
公开(公告)号：US07297992B1
公开(公告)日：2007-11-20
申请号：US10997534
申请日：2004-11-23
申请人： Greg D. U'Ren
发明人： Greg D. U'Ren
IPC分类号： H01L29/739
CPC分类号： H01L29/7378 , H01L21/8249 , H01L27/0623 , H01L29/0817 , H01L29/0821 , H01L29/66242
摘要： According to one exemplary embodiment, a heterojunction bipolar transistor includes a base situated on a substrate. The heterojunction bipolar transistor can be an NPN silicon-germanium heterojunction bipolar transistor, for example. The heterojunction bipolar transistor further includes a cap layer situated on the base, where the cap layer includes a barrier region. The barrier region can comprises carbon and has a thickness, where the thickness of the barrier region determines a depth of an emitter-junction of the heterojunction bipolar transistor. An increase in the thickness of the barrier region can cause a decrease in the depth of the emitter-base junction. According to this exemplary embodiment, the heterojunction bipolar transistor further includes an emitter situated over the cap layer, where the emitter comprises an emitter dopant, which can be phosphorus. A diffusion retardant in the barrier region of the cap layer impedes diffusion of the emitter dopant.
摘要翻译：根据一个示例性实施例，异质结双极晶体管包括位于衬底上的基极。例如，异质结双极晶体管可以是NPN硅 - 锗异质结双极晶体管。异质结双极晶体管还包括位于基底上的覆盖层，其中覆盖层包括阻挡区。阻挡区域可以包括碳并且具有厚度，其中阻挡区域的厚度确定异质结双极晶体管的发射极结的深度。阻挡区域的厚度的增加可能导致发射极 - 基极结的深度减小。根据该示例性实施例，异质结双极晶体管还包括位于覆盖层上方的发射极，其中发射极包括发射极掺杂剂，其可以是磷。盖层的阻挡区域中的扩散阻挡剂阻止发射体掺杂剂的扩散。

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