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11. 发明授权

US5701508A Executing different instructions that cause different data type operations to be performed on single logical register file 失效
标题翻译：执行导致在单个逻辑寄存器文件上执行不同数据类型操作的不同指令
公开(公告)号：US5701508A
公开(公告)日：1997-12-23
申请号：US574500
申请日：1995-12-19
申请人： Andrew F. Glew , Larry M. Mennemeier , Alexander D. Peleg , David Bistry , Millind Mittal , Carole Dulong , Eiichi Kowashi , Benny Eitan , Derrick Lin , Ramamohan R. Vakkalagadda
发明人： Andrew F. Glew , Larry M. Mennemeier , Alexander D. Peleg , David Bistry , Millind Mittal , Carole Dulong , Eiichi Kowashi , Benny Eitan , Derrick Lin , Ramamohan R. Vakkalagadda
IPC分类号： G06F9/30 , G06F9/318 , G06F9/455 , G06F9/46 , G06F9/00
CPC分类号： G06F9/3017 , G06F9/30036 , G06F9/30101 , G06F9/30105 , G06F9/30109 , G06F9/30112 , G06F9/30134 , G06F9/30189 , G06F9/384 , G06F9/45533 , G06F9/462
摘要： A method for executing different sets of instructions that cause a processor to perform different data type operations in a manner that is invisible to various operating system techniques, that promotes good programming practices, and that is invisible to existing software conventions. According to one aspect of the invention, a data processing apparatus executes a first set of instructions of a first instruction type on what at least logically appears to software as a single logical register file. While the data processing apparatus is executing the first set of instructions, the single logical register file appears to be operated as a flat register file. In addition, the data processing apparatus executes a first instruction of a second instruction type using the logical register file. However, while the data processing apparatus is executing the first instruction, the logical register file appears to be operated as a stack referenced register file. Furthermore, the data processing apparatus alters all tags in a set of tags corresponding to the single logical register file to a non-empty state sometime between starting the execution of the first set of instructions and completing the execution of the first instruction. The tags identifying whether registers in the single logical register file are empty or non-empty.
摘要翻译：一种用于执行不同的指令集的方法，其使得处理器以对于各种操作系统技术是不可见的方式执行不同的数据类型操作，其促进良好的编程实践，并且对于现有的软件约定是不可见的。根据本发明的一个方面，数据处理设备执行第一指令类型的第一组指令，至少在软件上逻辑上显示为单个逻辑寄存器文件。当数据处理装置正在执行第一组指令时，单个逻辑寄存器文件似乎被操作为平坦寄存器文件。此外，数据处理装置使用逻辑寄存器文件执行第二指令类型的第一指令。然而，当数据处理装置正在执行第一指令时，逻辑寄存器文件似乎被操作为堆栈引用的寄存器文件。此外，在开始执行第一组指令并完成第一指令的执行之前的某个时刻，数据处理装置将对应于单个逻辑寄存器文件的一组标签中的所有标签改变为非空状态。识别单个逻辑寄存器文件中的寄存器是空还是非空的标签。

12. 发明授权

US06792523B1 Processor with instructions that operate on different data types stored in the same single logical register file 失效
标题翻译：处理器具有对存储在同一个逻辑寄存器文件中的不同数据类型进行操作的指令
公开(公告)号：US06792523B1
公开(公告)日：2004-09-14
申请号：US09363116
申请日：1999-07-27
申请人： Andrew F. Glew , Larry M. Menneneier , Alexander D. Peleg , David Bistry , Millind Mittal , Carole Dulong , Eiichi Kowashi , Benny Eitan , Derrik Lin , Romamohan R. Vakkalagadda
发明人： Andrew F. Glew , Larry M. Menneneier , Alexander D. Peleg , David Bistry , Millind Mittal , Carole Dulong , Eiichi Kowashi , Benny Eitan , Derrik Lin , Romamohan R. Vakkalagadda
IPC分类号： G06F1200
CPC分类号： G06F9/3017 , G06F9/30036 , G06F9/30105 , G06F9/30109 , G06F9/30112 , G06F9/30134 , G06F9/30189 , G06F9/384 , G06F9/462
摘要： A processor with instructions to operate on different data types stored in a single logical register file. According to one aspect of the invention, a first set of instructions of a first instruction type operates on the contents of what at least logically appears to software as a single logical register file. The first set of instructions appears to access the single logical register file as a flat register file. In addition, a first instruction of a second instruction type operates on the logical register file. However, the first instruction appears to access the logical register file as a stack referenced register file. Furthermore, sometime between starting the execution of the first set of instructions and completing the execution of the first instruction, all tags in a set of tags indicating whether corresponding registers in the single logical register file are empty or non-empty are caused to indicate non-empty states.
摘要翻译：具有对存储在单个逻辑寄存器文件中的不同数据类型进行操作的指令的处理器。根据本发明的一个方面，第一指令类型的第一组指令对至少逻辑上显示为软件的内容进行操作，作为单个逻辑寄存器文件。第一组指令似乎以平坦寄存器文件的形式访问单个逻辑寄存器文件。此外，第二指令类型的第一指令对逻辑寄存器文件进行操作。但是，第一条指令似乎以堆栈引用的寄存器文件的形式访问逻辑寄存器文件。此外，在开始第一组指令的执行和完成第一指令的执行之间的某个时刻，引起一组标签中指示单个逻辑寄存器文件中的相应寄存器是空还是非空的所有标签，空状态。

13. 发明申请

US20120216018A1 PROCESSOR FOR PERFORMING MULTIPLY-ADD OPERATIONS ON PACKED DATA 失效
公开(公告)号：US20120216018A1
公开(公告)日：2012-08-23
申请号：US13456761
申请日：2012-04-26
申请人： Alexander D. Peleg , Millind Mittal , Larry M. Mennemeier , Benny Eitan , Carole Dulong , Eiichi Kowashi , Wolf Witt
发明人： Alexander D. Peleg , Millind Mittal , Larry M. Mennemeier , Benny Eitan , Carole Dulong , Eiichi Kowashi , Wolf Witt
IPC分类号： G06F15/76 , G06F9/302
CPC分类号： G06F7/60 , G06F7/4812 , G06F7/49921 , G06F7/5324 , G06F7/5338 , G06F7/5443 , G06F9/3001 , G06F9/30036 , G06F9/30112 , G06F15/7817 , G06F17/10 , G06F17/147 , G06F17/16 , G06F2207/3828 , G06T1/20
摘要： A method and apparatus for including in a processor instructions for performing multiply-add operations on packed data. In one embodiment, a processor is coupled to a memory. The memory has stored therein a first packed data and a second packed data. The processor performs operations on data elements in said first packed data and said second packed data to generate a third packed data in response to receiving an instruction. At least two of the data elements in this third packed data storing the result of performing multiply-add operations on data elements in the first and second packed data.

14. 发明授权

US07509367B2 Method and apparatus for performing multiply-add operations on packed data 有权
公开(公告)号：US07509367B2
公开(公告)日：2009-03-24
申请号：US10861167
申请日：2004-06-04
申请人： Alexander D. Peleg , Millind Mittal , Larry M. Mennemeier , Benny Eitan , Carole Dulong , Eiichi Kowashi , Wolf Witt
发明人： Alexander D. Peleg , Millind Mittal , Larry M. Mennemeier , Benny Eitan , Carole Dulong , Eiichi Kowashi , Wolf Witt
IPC分类号： G06F7/38
CPC分类号： G06F7/60 , G06F7/4812 , G06F7/49921 , G06F7/5324 , G06F7/5338 , G06F7/5443 , G06F9/3001 , G06F9/30036 , G06F9/30112 , G06F15/7817 , G06F17/10 , G06F17/147 , G06F17/16 , G06F2207/3828 , G06T1/20
摘要： A method and apparatus for including in a processor instructions for performing multiply-add operations on packed data. In one embodiment, a processor is coupled to a memory. The memory has stored therein a first packed data and a second packed data. The processor performs operations on data elements in said first packed data and said second packed data to generate a third packed data in response to receiving an instruction. At least two of the data elements in this third packed data storing the result of performing multiply-add operations on data elements in the first and second packed data.

15. 发明授权

US06385634B1 Method for performing multiply-add operations on packed data 失效
标题翻译：对打包数据进行乘法运算的方法
公开(公告)号：US06385634B1
公开(公告)日：2002-05-07
申请号：US08522067
申请日：1995-08-31
申请人： Alexander D. Peleg , Millind Mittal , Larry M. Mennemeier , Benny Eitan , Carole Dulong , Eiichi Kowashi , Wolf Witt
发明人： Alexander D. Peleg , Millind Mittal , Larry M. Mennemeier , Benny Eitan , Carole Dulong , Eiichi Kowashi , Wolf Witt
IPC分类号： G06F738
CPC分类号： G06F7/60 , G06F7/4812 , G06F7/49921 , G06F7/5324 , G06F7/5338 , G06F7/5443 , G06F9/3001 , G06F9/30036 , G06F9/30112 , G06F15/7817 , G06F17/10 , G06F17/147 , G06F17/16 , G06F2207/3828 , G06T1/20
摘要： A method and apparatus for including in a processor instructions for performing multiply-add operations on packed data. In one embodiment, a processor is coupled to a memory. The memory has stored therein a first packed data and a second packed data. The processor performs operations on data elements in said first packed data and said second packed data to generate a third packed data in response to receiving an instruction. At least two of the data elements in this third packed data storing the result of performing multiply-add operations on data elements in the first and second packed data.
摘要翻译：一种用于在处理器中包括用于对压缩数据进行乘法运算的指令的方法和装置。在一个实施例中，处理器耦合到存储器。存储器中存储有第一打包数据和第二打包数据。处理器对所述第一打包数据和所述第二打包数据中的数据元素执行操作，以响应于接收到指令而产生第三打包数据。该第三打包数据中的至少两个数据元素存储对第一和第二打包数据中的数据元素执行加法运算的结果。

16. 发明申请

US20120331028A1 PROCESSOR FOR PERFORMING MULTIPLY-ADD OPERATIONS ON PACKED DATA 失效
标题翻译：用于在包装数据上执行多重添加操作的处理器
公开(公告)号：US20120331028A1
公开(公告)日：2012-12-27
申请号：US13603370
申请日：2012-09-04
申请人： Alexander D. Peleg , Millind Mittal , Larry M. Mennemeier , Benny Eitan , Carole Dulong , Eiichi Kowashi , Wolf Witt
发明人： Alexander D. Peleg , Millind Mittal , Larry M. Mennemeier , Benny Eitan , Carole Dulong , Eiichi Kowashi , Wolf Witt
IPC分类号： G06F7/38
CPC分类号： G06F7/60 , G06F7/4812 , G06F7/49921 , G06F7/5324 , G06F7/5338 , G06F7/5443 , G06F9/3001 , G06F9/30036 , G06F9/30112 , G06F15/7817 , G06F17/10 , G06F17/147 , G06F17/16 , G06F2207/3828 , G06T1/20
摘要： A method and apparatus for including in a processor instructions for performing multiply-add operations on packed data. In one embodiment, a processor is coupled to a memory. The memory has stored therein a first packed data and a second packed data. The processor performs operations on data elements in said first packed data and said second packed data to generate a third packed data in response to receiving an instruction. At least two of the data elements in this third packed data storing the result of performing multiply-add operations on data elements in the first and second packed data.
摘要翻译：一种用于在处理器中包括用于对压缩数据进行乘法运算的指令的方法和装置。在一个实施例中，处理器耦合到存储器。存储器中存储有第一打包数据和第二打包数据。处理器对所述第一打包数据和所述第二打包数据中的数据元素执行操作，以响应于接收到指令而产生第三打包数据。该第三打包数据中的至少两个数据元素存储对第一和第二打包数据中的数据元素执行加法运算的结果。

17. 发明授权

US08185571B2 Processor for performing multiply-add operations on packed data 有权
标题翻译：用于对打包数据执行加法运算的处理器
公开(公告)号：US08185571B2
公开(公告)日：2012-05-22
申请号：US12409275
申请日：2009-03-23
申请人： Alexander D. Peleg , Millind Mittal , Larry M. Mennemeier , Benny Eitan , Carole Dulong , Eiichi Kowashi , Wolf Witt
发明人： Alexander D. Peleg , Millind Mittal , Larry M. Mennemeier , Benny Eitan , Carole Dulong , Eiichi Kowashi , Wolf Witt
IPC分类号： G06F7/38
CPC分类号： G06F7/60 , G06F7/4812 , G06F7/49921 , G06F7/5324 , G06F7/5338 , G06F7/5443 , G06F9/3001 , G06F9/30036 , G06F9/30112 , G06F15/7817 , G06F17/10 , G06F17/147 , G06F17/16 , G06F2207/3828 , G06T1/20
摘要： A method and apparatus for including in a processor instructions for performing multiply-add operations on packed data. In one embodiment, a processor is coupled to a memory. The memory has stored therein a first packed data and a second packed data. The processor performs operations on data elements in said first packed data and said second packed data to generate a third packed data in response to receiving an instruction. At least two of the data elements in this third packed data storing the result of performing multiply-add operations on data elements in the first and second packed data.
摘要翻译：一种用于在处理器中包括用于对压缩数据进行乘法运算的指令的方法和装置。在一个实施例中，处理器耦合到存储器。存储器中存储有第一打包数据和第二打包数据。处理器对所述第一打包数据和所述第二打包数据中的数据元素执行操作，以响应于接收到指令而产生第三打包数据。该第三打包数据中的至少两个数据元素存储对第一和第二打包数据中的数据元素执行加法运算的结果。

18. 发明授权

US07424505B2 Method and apparatus for performing multiply-add operations on packed data 有权
公开(公告)号：US07424505B2
公开(公告)日：2008-09-09
申请号：US09989736
申请日：2001-11-19
申请人： Alexander D. Peleg , Millind Mittal , Larry M. Mennemeier , Benny Eitan , Carole Dulong , Eiichi Kowashi , Wolf Witt
发明人： Alexander D. Peleg , Millind Mittal , Larry M. Mennemeier , Benny Eitan , Carole Dulong , Eiichi Kowashi , Wolf Witt
IPC分类号： G06F7/38
CPC分类号： G06F7/60 , G06F7/4812 , G06F7/49921 , G06F7/5324 , G06F7/5338 , G06F7/5443 , G06F9/3001 , G06F9/30036 , G06F9/30112 , G06F15/7817 , G06F17/10 , G06F17/147 , G06F17/16 , G06F2207/3828 , G06T1/20
摘要： A method and apparatus for including in a processor instructions for performing multiply-add operations on packed data. In one embodiment, a processor is coupled to a memory. The memory has stored therein a first packed data and a second packed data. The processor performs operations on data elements in said first packed data and said second packed data to generate a third packed data in response to receiving an instruction. At least two of the data elements in this third packed data storing the result of performing multiply-add operations on data elements in the first and second packed data.

19. 发明授权

US5984515A Computer implemented method for providing a two dimensional rotation of packed data 失效
标题翻译：用于提供打包数据的二维旋转的计算机实现的方法
公开(公告)号：US5984515A
公开(公告)日：1999-11-16
申请号：US917671
申请日：1997-08-21
申请人： Larry M. Mennemeier , Alexander D. Peleg , Carole Dulong , Eiichi Kowashi , Millind Mittal , Benny Eitan
发明人： Larry M. Mennemeier , Alexander D. Peleg , Carole Dulong , Eiichi Kowashi , Millind Mittal , Benny Eitan
IPC分类号： G06F9/302 , G06T3/60 , G06F17/14
CPC分类号： G06F9/30014 , G06F9/30036 , G06T3/60
摘要： In a computer system having stored therein a first and a second packed data having corresponding data elements, a method for generating a two dimensional rotation of said packed data. The method includes the steps of generating a first set of intermediate results in response to a first instruction by multiplying the data elements of the first packed data with corresponding elements of a third packed data. The elements of said third packed data represent either a sine or cosine function. A second step of generating a second set of intermediate results in response to a second instruction by multiplying the data elements of the second packed data with corresponding elements of a fourth packed data. The elements of the fourth packed data represent either a sine or cosine function. A third and final step of generating a set of final results in response to a third instruction by performing an arithmetic operation between corresponding elements of the first and second sets of intermediate results. The final results represent a two dimensional rotation of the elements of the first set of packed data.
摘要翻译：在其中存储有具有相应数据元素的第一和第二打包数据的计算机系统中，一种用于产生所述打包数据的二维旋转的方法。该方法包括以下步骤：通过将第一打包数据的数据元素与第三打包数据的相应元素相乘来响应于第一指令来生成第一组中间结果。所述第三打包数据的元素表示正弦或余弦函数。第二步骤，通过将第二打包数据的数据元素与第四打包数据的对应元素相乘来响应于第二指令来生成第二组中间结果。第四打包数据的元素表示正弦或余弦函数。通过在第一和第二组中间结果的相应元素之间执行算术运算来产生响应于第三指令的一组最终结果的第三和最后一步骤。最终结果表示第一组打包数据的元素的二维旋转。

20. 发明授权

US5983257A System for signal processing using multiply-add operations 失效
标题翻译：使用多重加法运算的信号处理系统
公开(公告)号：US5983257A
公开(公告)日：1999-11-09
申请号：US578829
申请日：1995-12-26
申请人： Carole Dulong , Larry M. Mennemeier , Tuan H. Bui , Eiichi Kowashi , Alexander D. Peleg , Benny Eitan , Stephen A. Fischer , Benny Maytal , Millind Mittal
发明人： Carole Dulong , Larry M. Mennemeier , Tuan H. Bui , Eiichi Kowashi , Alexander D. Peleg , Benny Eitan , Stephen A. Fischer , Benny Maytal , Millind Mittal
IPC分类号： G06F7/544 , G06F9/302 , G06F7/00 , G06F7/52
CPC分类号： G06F9/30036 , G06F7/5443 , G06F9/30014 , G06F2207/3828
摘要： A computer system which includes a multimedia input device which generates an audio or video input signal and a processor coupled to the multimedia input device. The system further includes a storage device coupled to the processor and having stored therein a signal processing routine for multiplying and accumulating input values representative of the audio or video input signal. The signal processing routine, when executed by the processor, causes the processor to perform several steps. These steps include performing a packed multiply add on a first set of values packed into a first source and a second set of values packed into a second source each representing input signals to generate a packed intermediate result. The packed intermediate result is added to an accumulator to generate a packed accumulated result in the accumulator. These steps may be iterated with the first set of values and portions of the second set of values to the accumulator to generate the packed accumulated result. Subsequent thereto, the packed accumulated result in the accumulator is unpacked into a first result and a second result and the first result and the second result are added together to generate an accumulated result.
摘要翻译：一种计算机系统，其包括产生音频或视频输入信号的多媒体输入设备和耦合到所述多媒体输入设备的处理器。该系统还包括耦合到处理器并且在其中存储有用于乘以和累加表示音频或视频输入信号的输入值的信号处理例程的存储装置。信号处理程序在由处理器执行时使处理器执行几个步骤。这些步骤包括对打包到第一源的第一组值进行压缩乘法加法，并将第二组值打包到表示输入信号的第二源中，以生成打包的中间结果。将打包的中间结果加到累加器中以在累加器中产生打包累计结果。这些步骤可以用第一组值和第二组值的部分迭代到累加器，以产生打包的累积结果。随后，将累加器中的打包累积结果解包成第一结果，将第二结果与第一结果和第二结果相加在一起以产生累积结果。

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