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11. 发明授权

US09712171B2 Clocked all-spin logic circuit 有权
公开(公告)号：US09712171B2
公开(公告)日：2017-07-18
申请号：US14129527
申请日：2013-09-11
申请人： Dmitri E. Nikonov , Sasikanth Manipatruni , Ian A. Young , Vehbi Calayir
发明人： Dmitri E. Nikonov , Sasikanth Manipatruni , Ian A. Young , Vehbi Calayir
IPC分类号： H03K19/16 , G06F7/501 , H03K19/20 , B82Y25/00 , H03K3/45
CPC分类号： H03K19/16 , B82Y25/00 , G06F7/501 , G11C11/161 , H03K3/45 , H03K19/20
摘要： Described is a latch comprising: a first all-spin logic (ASL) device; a second ASL device coupled to the first ASL device, the second ASL device controllable by a clock signal; and a third ASL device coupled to the second ASL device, wherein the first and third ASL devices have respective magnets coupled to a power supply terminal. Described is a flip-flop which comprises: a first ASL device; a second ASL device coupled to the first ASL device, the second ASL device controllable by a first clock signal; a third ASL device coupled to the second ASL device, the third ASL device controllable by a second clock signal, the second clock signal being out of phase relative to the first clock signal; and a fourth ASL device coupled to the third ASL device, wherein the first and fourth ASL devices have respective magnets coupled to a power supply terminal.

12. 发明申请

US20170093377A1 NON-BOOLEAN ASSOCIATIVE PROCESSOR DEGREE OF MATCH AND WINNER TAKE ALL CIRCUITS 审中-公开
公开(公告)号：US20170093377A1
公开(公告)日：2017-03-30
申请号：US14864241
申请日：2015-09-24
申请人： Dmitri E. Nikonov , Ian A. Young
发明人： Dmitri E. Nikonov , Ian A. Young
IPC分类号： H03K3/03 , G06K9/00
CPC分类号： H03K3/0315 , G06K9/0055
摘要： Embodiments include circuits, apparatuses, and systems for non-boolean associative processors. In embodiments, an electronic associative processor circuit may include first and second ring oscillators, each having an odd number of inverters, an input terminal, and an output terminal. A first capacitor may have a first terminal coupled with the output terminal of the first ring oscillator and a second capacitor may have a first terminal coupled with the output terminal of the second ring oscillator. Second terminals of the first and second capacitors may be coupled at an oscillator stage output terminal. The inverters of the first and second ring oscillators may be implemented with metal oxide semiconductor transistors. Other embodiments may be described and claimed.

13. 发明授权

US09070468B2 Magnetic state element and circuits 有权
标题翻译：磁状态元件和电路
公开(公告)号：US09070468B2
公开(公告)日：2015-06-30
申请号：US13996998
申请日：2012-03-29
申请人： Sasikanth Manipatruni , Dmitri E. Nikonov , Ian A. Young
发明人： Sasikanth Manipatruni , Dmitri E. Nikonov , Ian A. Young
IPC分类号： G11C11/00 , G11C11/16 , H03K19/16
CPC分类号： H01L29/66984 , G11C11/16 , G11C11/161 , G11C11/1653 , G11C11/1659 , G11C11/1673 , G11C11/1675 , G11C11/1697 , H01L27/226 , H01L43/08 , H01L43/10 , H01L43/12 , H03K19/16
摘要： Described is an apparatus, for spin state element device, which comprises: a variable resistive magnetic (VRM) device to receive a magnetic control signal to adjust resistance of the VRM device; and a magnetic logic gating (MLG) device, coupled to the VRM device, to receive a magnetic logic input and perform logic operation on the magnetic logic input and to drive an output magnetic signal based on the resistance of the VRM device. Described is a magnetic demultiplexer which comprises: a first VRM device to receive a magnetic control signal to adjust resistance of the first VRM; a second VRM device to receive the magnetic control signal to adjust resistance of the second VRM device; and an MLG device, coupled to the first and second VRM devices, the MLG device having at least two output magnets to output magnetic signals based on the resistances of the first and second VRM devices.
摘要翻译：描述了一种用于自旋状态元件器件的装置，其包括：可变电阻磁极（VRM）器件，用于接收磁控制信号以调节VRM器件的电阻; 以及耦合到VRM装置的磁逻辑门控（MLG）装置，以接收磁逻辑输入并对磁逻辑输入执行逻辑运算，并且基于VRM装置的电阻来驱动输出磁信号。描述了一种磁解多路复用器，其包括：第一VRM装置，用于接收磁控制信号以调整第一VRM的电阻; 第二VRM装置，用于接收所述磁控信号以调整所述第二VRM装置的电阻; 以及耦合到第一和第二VRM装置的MLG装置，MLG装置具有至少两个输出磁体，以基于第一和第二VRM装置的电阻输出磁信号。

14. 发明授权

US08274339B2 Automatic frequency control architecture with digital temperature compensation 有权
标题翻译：具有数字温度补偿功能的自动频率控制架构
公开(公告)号：US08274339B2
公开(公告)日：2012-09-25
申请号：US12770230
申请日：2010-04-29
申请人： Yongping Fan , Jing Li , Ian A. Young
发明人： Yongping Fan , Jing Li , Ian A. Young
IPC分类号： H03L1/02 , H03L7/085
CPC分类号： H03L1/02 , H03B5/1215 , H03B5/1228 , H03B5/1234 , H03B5/124 , H03B5/1265 , H03J2200/10 , H03L7/099 , H03L7/103 , H03L7/18
摘要： A mixed signal circuit architecture is disclosed for automatic frequency control and digital temperature compensation in an LC-PLL system. Some embodiments allow for high-volume manufacturing of products such as microprocessors and chipsets, and other circuits that employ LC-PLL technology. In some embodiments, various capacitor loadings can be selected to compensate for variation associated with process, voltage, temperature, and reference frequency. In addition, a multi-leg capacitor bank can be selectively used to further compensate for temperature variation post-lock, in accordance with some embodiments. A programmable timer can be used in some embodiments to allow for loop settling prior to assessing parameters of interest.
摘要翻译：公开了用于LC-PLL系统中的自动频率控制和数字温度补偿的混合信号电路架构。一些实施例允许诸如微处理器和芯片组的产品的大量制造以及采用LC-PLL技术的其它电路。在一些实施例中，可以选择各种电容器负载以补偿与过程，电压，温度和参考频率相关联的变化。此外，根据一些实施例，可以选择性地使用多支脚电容器组来进一步补偿温度变化后锁定。在一些实施例中可以使用可编程定时器，以便在评估感兴趣的参数之前允许循环结算。

15. 发明授权

US07729393B2 Surface emitting laser with an integrated absorber 失效
标题翻译：具有集成吸收体的表面发射激光器
公开(公告)号：US07729393B2
公开(公告)日：2010-06-01
申请号：US11725659
申请日：2007-03-19
申请人： Ian A. Young , Ursula Keller , Heiko Unold , Rüdiger Paschotta , Silke Schön
发明人： Ian A. Young , Ursula Keller , Heiko Unold , Rüdiger Paschotta , Silke Schön
IPC分类号： H01S3/113
CPC分类号： G06F1/105 , H01S3/0092 , H01S3/0604 , H01S3/0615 , H01S3/0627 , H01S3/094084 , H01S3/1115 , H01S3/1118 , H01S5/024 , H01S5/041 , H01S5/0609 , H01S5/0657 , H01S5/141 , H01S5/18302 , H01S5/18308 , H01S5/18341 , H01S5/18358 , H01S5/18388 , H01S5/423
摘要： A surface emitting laser (SEL) with an integrated absorber. A lower mirror and an output coupler define a laser cavity of the SEL. A monolithic gain structure positioned in the laser cavity includes a gain region and an absorber, wherein a saturation fluence of the absorber is less than a saturation fluence of the gain region.
摘要翻译：具有集成吸收体的表面发射激光器（SEL）。下反射镜和输出耦合器限定SEL的激光腔。位于激光腔中的单片增益结构包括增益区和吸收体，其中吸收体的饱和能量密度小于增益区的饱和能量密度。

16. 发明授权

US06856129B2 Current probe device having an integrated amplifier 失效
标题翻译：具有集成放大器的电流探头装置
公开(公告)号：US06856129B2
公开(公告)日：2005-02-15
申请号：US10190712
申请日：2002-07-09
申请人： Thomas P. Thomas , Douglas N. Stunkard , Miriam R. Reshotko , Brandon C. Barnett , Ian A. Young
发明人： Thomas P. Thomas , Douglas N. Stunkard , Miriam R. Reshotko , Brandon C. Barnett , Ian A. Young
IPC分类号： G01R1/067 , G01R31/00
CPC分类号： G01R1/06772 , G01R1/06766
摘要： A measurement system is provided that includes a probe device having an integrated amplifier. The integrated amplifier may be a transimpedence amplifier that amplifies input current to an output voltage.
摘要翻译：提供了一种包括具有集成放大器的探针装置的测量系统。集成放大器可以是将输入电流放大到输出电压的跨阻放大器。

17. 发明授权

US06650161B2 Clock distribution network having regulated power supply 有权
公开(公告)号：US06650161B2
公开(公告)日：2003-11-18
申请号：US09751942
申请日：2000-12-28
申请人： Thomas P. Thomas , Ian A. Young
发明人： Thomas P. Thomas , Ian A. Young
IPC分类号： H03K300
CPC分类号： G06F1/10
摘要： A clock distribution network for an integrated circuit is disclosed. The network includes a plurality of inverters that distribute a clock signal. The inverters are powered by a power supply. The power supply is supplied to the inverters through a source follower transistor that has its gate connected to a regulated DC voltage. The source follower transistor operates in the saturation region.

18. 发明授权

US06229861B1 Clock distribution network utilizing local deskewing clock generator circuitry 失效
标题翻译：时钟分配网络利用局部的歪斜时钟发生器电路
公开(公告)号：US06229861B1
公开(公告)日：2001-05-08
申请号：US08486935
申请日：1995-06-07
申请人： Ian A. Young
发明人： Ian A. Young
IPC分类号： H04L700
CPC分类号： G06F1/10
摘要： A clock signal distribution network for a high-speed microprocessor includes a clock synthesizer coupled to receive an externally generated clock signal. The clock synthesizer deskews the external clock to generate an internal clock signal, which is then distributed about the semiconductor die by a conductivity tree. A set of local deskewing clock generators are coupled to branch interconnects of the tree and function as a zero-delay buffers for driving proximally located circuitry.
摘要翻译：用于高速微处理器的时钟信号分配网络包括被耦合以接收外部产生的时钟信号的时钟合成器。时钟合成器对外部时钟进行校准以产生内部时钟信号，然后通过电导率树分布在半导体管芯周围。一组本地的偏移时钟发生器耦合到树的分支互连，并且用作用于驱动向近侧定位的电路的零延迟缓冲器。

19. 发明授权

US06172937B2 Multiple synthesizer based timing signal generation scheme 有权
标题翻译：基于多合成器的定时信号生成方案
公开(公告)号：US06172937B2
公开(公告)日：2001-01-09
申请号：US09309049
申请日：1999-05-10
申请人： Alper Ilkbahar , Simon M. Tam , Ian A. Young
发明人： Alper Ilkbahar , Simon M. Tam , Ian A. Young
IPC分类号： G11C800
CPC分类号： G06F1/06
摘要： A multiple synthesizer based timing signal generation scheme is described that allows accurate data and strobe generation in high speed source synchronous system interfaces. Multiple loop locked clock synthesizers (e.g., phase locked loops, delay locked loops) are used to generate multiple clock signals. Data and strobe signals are triggered off of transitions of one of the clock signals. Because multiple loop locked clock synthesizers are used to generate the clock signals, optimal or near optimal alignment of the data and strobe signals can be achieved. Improved alignment of the data and strobe signals provides improved data transmission rates.
摘要翻译：描述了基于多合成器的定时信号生成方案，其允许在高速源同步系统接口中进行准确的数据和频闪生成。多环路锁定时钟合成器（例如，锁相环，延迟锁定环）用于产生多个时钟信号。数据和选通信号从一个时钟信号的转换触发。由于使用多个环路锁定时钟合成器来产生时钟信号，所以可以实现数据和选通信号的最佳或接近最佳对准。改进的数据和选通信号的对准提供了改进的数据传输速率。

20. 发明授权

US6075908A Method and apparatus for optically modulating light through the back side of an integrated circuit die 失效
标题翻译：通过集成电路管芯的背侧对光进行光学调制的方法和装置
公开(公告)号：US6075908A
公开(公告)日：2000-06-13
申请号：US993786
申请日：1997-12-19
申请人： Mario J. Paniccia , Valluri R. M. Rao , Ian A. Young
发明人： Mario J. Paniccia , Valluri R. M. Rao , Ian A. Young
IPC分类号： G02B6/12 , G02F1/015 , G02F1/21
CPC分类号： G02F1/218 , G02B2006/12107 , G02B2006/12142 , G02F2001/0152 , G02F2201/307
摘要： An optical modulator that modulates light through the semiconductor substrate through the back side of a flip chip packaged integrated circuit. The optical modulator of the present invention enables integrated circuit signals to be extracted through the back side of the semiconductor substrate. In one embodiment, an optical modulator is disposed within a flip chip packaged integrated circuit die. The optical modulator includes a deflector and a diffraction grating. An infrared light beam is directed through the back side of a silicon substrate of the integrated circuit die, deflected off the deflector through the diffraction grating and back out the back side of the integrated circuit die. The diffraction grating modulates the phase of a portion of the deflected light beam in response to an integrated circuit signal. A resulting diffraction interference occurs between the phase modulated portions and non-phase modulated portions of the deflected light beam. The interference causes amplitude modulation of a zero order diffraction of the deflected light beam, from which the integrated circuit signal can be extracted.
摘要翻译：一种光学调制器，其通过倒装芯片封装集成电路的背面来调制通过半导体衬底的光。本发明的光调制器能够通过半导体基板的背面提取集成电路信号。在一个实施例中，光学调制器设置在倒装芯片封装集成电路管芯内。光学调制器包括偏转器和衍射光栅。红外光束被引导通过集成电路管芯的硅衬底的背面，通过衍射光栅偏转偏转器并从集成电路管芯的背面退出。衍射光栅响应于集成电路信号调制偏转光束的一部分的相位。在偏转光束的相位调制部分和非相位调制部分之间产生衍射干涉。干扰引起偏转光束的零级衍射的幅度调制，可从中提取集成电路信号。

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