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11. 发明授权

US5489790A Static-random-access memory cell 失效
标题翻译：静态随机存取存储单元
公开(公告)号：US5489790A
公开(公告)日：1996-02-06
申请号：US380772
申请日：1995-01-30
申请人： Craig S. Lage
发明人： Craig S. Lage
IPC分类号： H01L21/8244 , H01L29/76
CPC分类号： H01L27/11 , Y10S257/903
摘要： An SRAM cell includes a pair of cross-coupled inverters where each inverter includes vertical n-channel and p-channel transistors having a gate electrode that is shared between the transistors that make up each inverter. The gate electrodes for the inverters laterally surround the channel regions of the p-channel load transistors to achieve a relatively high beta ratio without occupying a large amount of substrate surface area. Also, the gate electrodes increase the amount of capacitance of the storage nodes and decreases the soft error rate. The active regions of the latch transistors are electrically isolated from the substrate by a buried oxide layer, thereby decreasing the chances of latch-up.
摘要翻译： SRAM单元包括一对交叉耦合的反相器，其中每个反相器包括垂直的n沟道和p沟道晶体管，其具有在构成每个反相器的晶体管之间共享的栅电极。用于逆变器的栅电极横向围绕p沟道负载晶体管的沟道区域，以实现相对高的β比例而不占据大量的衬底表面积。此外，栅电极增加了存储节点的电容量并降低了软错误率。锁存晶体管的有源区通过掩埋氧化物层与衬底电隔离，由此降低闩锁的可能性。

12. 发明授权

US5485420A Static-random-access memory cell and an integrated circuit having a static-random-access memory cell 失效
标题翻译：静态随机存取存储器单元和具有静态随机存取存储单元的集成电路
公开(公告)号：US5485420A
公开(公告)日：1996-01-16
申请号：US278465
申请日：1994-07-21
申请人： Craig S. Lage , Frank K. Baker , James D. Hayden , Kent J. Cooper
发明人： Craig S. Lage , Frank K. Baker , James D. Hayden , Kent J. Cooper
IPC分类号： G11C11/412 , H01L21/8244 , G11C11/00
CPC分类号： H01L27/11 , G11C11/412 , Y10S257/903
摘要： The present invention includes an integrated circuit having a self-aligned contact that makes contact to both a region within the substrate and a capacitor plate of a capacitor that is adjacent to the doped region. The present invention also includes a static-random-access memory cell with a capacitor having a first plate and a second plate. The first plate includes a first plate section of a gate electrode of a transistor, and the second plate includes a first conductive member that is substantially coincident with the first plate section. The second plate may be formed over a gate electrode of a latch transistor or over a word line. The disclosure includes methods of forming the integrated circuit and the static-random-access memory cell.
摘要翻译：本发明包括具有与衬底内的区域接触的自对准接触的集成电路和与掺杂区相邻的电容器的电容器板。本发明还包括具有第一板和第二板的电容器的静态随机存取存储单元。第一板包括晶体管的栅电极的第一板部分，第二板包括与第一板部分基本一致的第一导电部件。第二板可以形成在锁存晶体管的栅电极上或字线之上。本公开包括形成集成电路和静态随机存取存储器单元的方法。

13. 发明授权

US5377139A Process forming an integrated circuit 失效
标题翻译：工艺形成集成电路
公开(公告)号：US5377139A
公开(公告)日：1994-12-27
申请号：US990341
申请日：1992-12-11
申请人： Craig S. Lage , Frank K. Baker , James D. Hayden , Kent J. Cooper
发明人： Craig S. Lage , Frank K. Baker , James D. Hayden , Kent J. Cooper
IPC分类号： G11C11/412 , H01L21/8244 , G11C13/00
CPC分类号： H01L27/11 , G11C11/412 , Y10S257/903
摘要： The present invention includes an integrated circuit having a self-aligned contact that makes contact to both a region within the substrate and a capacitor plate of a capacitor that is adjacent to the doped region. The present invention also includes a static-random-access memory cell with a capacitor having a first plate and a second plate. The first plate includes a first plate section of a gate electrode of a transistor, and the second plate includes a first conductive member that is substantially coincident with the first plate section. The second plate may be formed over a gate electrode of a latch transistor or over a word line. The disclosure includes methods of forming the integrated circuit and the static-random-access memory cell.
摘要翻译：本发明包括具有与衬底内的区域接触的自对准接触的集成电路和与掺杂区相邻的电容器的电容器板。本发明还包括具有第一板和第二板的电容器的静态随机存取存储单元。第一板包括晶体管的栅电极的第一板部分，第二板包括与第一板部分基本一致的第一导电部件。第二板可以形成在锁存晶体管的栅电极上或字线之上。本公开包括形成集成电路和静态随机存取存储器单元的方法。

14. 发明授权

US5285093A Semiconductor memory cell having a trench structure 失效
标题翻译：具有沟槽结构的半导体存储单元
公开(公告)号：US5285093A
公开(公告)日：1994-02-08
申请号：US955781
申请日：1992-10-05
申请人： Craig S. Lage , Richard D. Sivan
发明人： Craig S. Lage , Richard D. Sivan
IPC分类号： H01L27/11 , H01L29/786 , H01L29/10 , H01L27/02 , H01L29/78
CPC分类号： H01L29/78642 , H01L27/1108 , Y10S257/903
摘要： In one embodiment, a semiconductor memory cell (10) having a trench (24) and access transistor (54) formed in a well region (20). The trench (24) substantially contains an inverter (60) which is electrically coupled to ground and power signals by buried layers (12, 18) in the substrate (11). The inverter (60) has a toroidal, shared-gate electrode (40) which electrically controls a driver transistor (32) in the wall (26) of the trench (24), and a thin-film load transistor (42) in the central portion of the trench (24). A portion of the toroidal, shared gate electrode extends to an adjacent well region (20') and contacts well region (20') at cell node (13'). A ground signal is provided to load transistor (42) at the bottom surface (28) of the trench (42). A supply signal is provided by a buried layer (18) which is integral with driver transistor (32).
摘要翻译：在一个实施例中，具有形成在阱区（20）中的沟槽（24）和存取晶体管（54）的半导体存储单元（10）。沟槽（24）基本上包含逆变器（60），其通过衬底（11）中的掩埋层（12,18）电耦合到接地和功率信号。逆变器（60）具有环形共用栅电极（40），其对沟槽（24）的壁（26）中的驱动晶体管（32）进行电控制，以及薄膜负载晶体管（42）沟槽（24）的中心部分。环形共享栅电极的一部分延伸到相邻的阱区（20'），并在单元节点（13'）处接触阱区（20'）。提供接地信号以在沟槽（42）的底表面（28）处负载晶体管（42）。电源信号由与驱动晶体管（32）成一体的掩埋层（18）提供。

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