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11. 发明授权

US08339183B2 Charge pump with reduced energy consumption through charge sharing and clock boosting suitable for high voltage word line in flash memories 有权
标题翻译：电荷泵通过电荷共享和时钟提升降低能耗，适用于闪存中的高电压字线
公开(公告)号：US08339183B2
公开(公告)日：2012-12-25
申请号：US12509367
申请日：2009-07-24
申请人： Khin Htoo , Feng Pan , Byungki Woo , Trung Pham , Yuxin Wang
发明人： Khin Htoo , Feng Pan , Byungki Woo , Trung Pham , Yuxin Wang
IPC分类号： G05F1/10
CPC分类号： H02M3/073
摘要： A charge pump circuit for generating an output voltage is described. Charge pump circuits typically have two branches. As the clocks supplying the branches of a charge pump circuit alternate, the output of each branch will alternately provide an output voltage, which are then combined to form the pump output. The techniques described here allow charge to be transferred between the two branches, so that as the capacitor of one branch discharges, it is used to charge up the capacitor in the other branch. An exemplary embodiment using a voltage doubler-type of circuit, with the charge transfer between the branches accomplished using a switch controller by a boosted version of the clock signal, which is provided by a one-sided voltage doubler.
摘要翻译：描述用于产生输出电压的电荷泵电路。电荷泵电路通常具有两个分支。当提供电荷泵电路的分支的时钟交替时，每个分支的输出将交替地提供输出电压，然后将其组合以形成泵输出。这里描述的技术允许在两个分支之间传输电荷，使得当一个分支的电容器放电时，它用于对另一个分支中的电容器充电。使用倍压型电路的示例性实施例，通过由单侧电压倍增器提供的时钟信号的升压版本，使用开关控制器实现分支之间的电荷转移。

12. 发明授权

US08263192B2 Methods for modifying surfaces 有权
标题翻译：修饰表面的方法
公开(公告)号：US08263192B2
公开(公告)日：2012-09-11
申请号：US11454652
申请日：2006-06-16
申请人： Jeffrey T. Koberstein , Peng Wang , Feng Pan
发明人： Jeffrey T. Koberstein , Peng Wang , Feng Pan
IPC分类号： B05D5/00 , B05D3/06 , C08J7/18
CPC分类号： C08J7/12 , A61L27/34 , A61L29/085 , B05D1/185 , B05D1/32 , B05D3/067 , B05D3/107 , B05D2401/90 , B82Y30/00 , B82Y40/00 , C03C17/32 , C07K17/00 , C08J7/047 , C08J7/18 , D06M23/005 , G03F7/0048 , G03F7/0392 , G03F7/165 , G03F7/265 , H05K3/389
摘要： The invention is directed to methods for coating monolayer films of surface-active polymers onto substrates of arbitrary shape, and molecular-based methods and processes to control the chemical and physical nature of surfaces and interfaces. The invention is also directed to methods for modifying a surface of a monolayer comprising a) coating a monolayer on a substrate, wherein the monolayer is formed by self-assembly of end-surfactant molecules, thereby positioning a photoactive functional group at the air-monolayer interface; and b) exposing the monolayer to radiation, wherein each organic group of the monolayer contains a first functionality that is not converted to a second functionality upon exposure to acid.
摘要翻译：本发明涉及将表面活性聚合物的单层膜涂覆到任意形状的基底上的方法，以及用于控制表面和界面的化学和物理性质的基于分子的方法和方法。本发明还涉及用于修饰单层表面的方法，其包括：a）在基底上涂覆单层，其中通过端表面活性剂分子的自组装形成单层，从而将光活性官能团定位在空气单层接口; 和b）将单层暴露于辐射，其中单层的每个有机基团含有当暴露于酸时不转化为第二官能团的第一官能度。

13. 发明授权

US08173347B2 Micropatterning of molecular surfaces via selective irradiation 有权
标题翻译：通过选择性辐射微分谱分子表面
公开(公告)号：US08173347B2
公开(公告)日：2012-05-08
申请号：US11201915
申请日：2005-08-11
申请人： Jeffrey T. Koberstein , Feng Pan , Kwangjoo Lee , Peng Wang
发明人： Jeffrey T. Koberstein , Feng Pan , Kwangjoo Lee , Peng Wang
IPC分类号： G03F7/00
CPC分类号： G03F7/095 , B05D1/185 , B05D5/005 , B29C59/16 , B29C2035/0827 , B29L2009/005 , B82Y30/00 , G03F7/165
摘要： A method for surface micropatterning includes forming on a surface containing a first polymer a first coating containing a second polymer having first functionalities capable of being converted to second functionalities by exposure to an acid. A second coating containing a photoacid generator is formed on the first coating. The second coating containing the photoacid generator is selectively irradiated in one or more regions thereof with radiation having a spatially varying internsity pattern to generate an acid in each irradiated region of the second coating. The acid converts the first functionalities of each region of the second polymer underlying a respective irradiated region of the second coating to second functionalities. A first molecular patterned surface having one or more regions of the first functionalities and one or more regions of the second functionalities is formed.
摘要翻译：表面微图案的方法包括在包含第一聚合物的表面上形成含有第一聚合物的第一涂层，所述第二聚合物具有通过暴露于酸而能够转化为第二官能团的第一官能度。在第一涂层上形成含有光致酸发生剂的第二涂层。含有光致酸产生剂的第二涂层在其一个或多个区域中用具有空间变化的内部结构图案的辐射选择性地照射，以在第二涂层的每个照射区域中产生酸。酸将第二涂层的相应照射区域下面的第二聚合物的每个区域的第一官能团转化为第二官能团。形成具有第一功能的一个或多个区域和第二功能的一个或多个区域的第一分子图案化表面。

14. 发明申请

US20120008410A1 Detection of Word-Line Leakage in Memory Arrays: Current Based Approach 有权
标题翻译：内存阵列中字线泄漏的检测：基于电流的方法
公开(公告)号：US20120008410A1
公开(公告)日：2012-01-12
申请号：US13016732
申请日：2011-01-28
申请人： Jonathan H. Huynh , Feng Pan , Viswakiran Popuri , Marco Cazzaniga
发明人： Jonathan H. Huynh , Feng Pan , Viswakiran Popuri , Marco Cazzaniga
IPC分类号： G11C16/06
CPC分类号： G11C29/02 , G11C16/04 , G11C29/025 , G11C29/028 , G11C2029/5006
摘要： Techniques and corresponding circuitry are presented for the detection of wordline leakage in a memory array. In an exemplary embodiment, a capacitive voltage divider is used to translate the high voltage drop to low voltage drop that can be compared with a reference voltage to determine the voltage drop due to leakage. An on-chip self calibration method can help assure the accuracy of this technique for detecting leakage limit. In other embodiments, the current drawn by a reference array, where a high voltage is applied to the array with all wordlines non-selected, is compared to the current drawn by an array where the high voltage is applied and one or more selected wordlines. In these current based embodiments, the reference array can be a different array, or the same array as that one selected for testing.
摘要翻译：提供技术和相应的电路用于检测存储器阵列中的字线泄漏。在示例性实施例中，使用电容分压器将高压降转换成可与参考电压进行比较的低电压降，以确定由于泄漏引起的电压降。片上自校准方法可以帮助确保这种检测泄漏极限的技术的准确性。在其他实施例中，将由未被选择的所有字线施加到阵列的高电压的参考阵列绘制的电流与施加高电压的阵列和一个或多个选定的字线所绘制的电流进行比较。在这些基于当前的实施例中，参考阵列可以是不同的阵列，或与用于测试所选择的阵列相同的阵列。

15. 发明授权

US08054681B2 Read, verify word line reference voltage to track source level 有权
标题翻译：读取，验证字线参考电压以跟踪源电平
公开(公告)号：US08054681B2
公开(公告)日：2011-11-08
申请号：US12715858
申请日：2010-03-02
申请人： Feng Pan , Trung Pham , Byungki Woo
发明人： Feng Pan , Trung Pham , Byungki Woo
IPC分类号： G11C11/34
CPC分类号： G11C16/08 , G11C16/30
摘要： A non-volatile memory device has individual pages of memory cells to be sensed in parallel. The memory device includes a source level tracking circuit coupled to receive a predetermined word line voltage from a word line voltage supply and the voltage level at the aggregate source node of one or more pages and coupled to provide to word lines of the memory an output voltage during the sensing operation, where the source level tracking circuit includes an op amp whereby the output voltage is the word line voltage offset by an amount to track the voltage level at the aggregate node and compensate for source bias errors due to a finite resistance in the ground loop.
摘要翻译：非易失性存储器件具有要并行感测的存储器单元的单独页面。存储器件包括源极电平跟踪电路，其被耦合以从字线电压源接收预定字线电压，并在一个或多个页面的聚合源节点处接收电压电平，并被耦合以向存储器的字线提供输出电压在感测操作期间，源电平跟踪电路包括运算放大器，由此输出电压是字线电压偏移量，以跟踪聚集节点处的电压电平，并补偿源极偏移误差，由于在接地回路。

16. 发明授权

US08021170B2 Electrical connector having improved terminal module 失效
标题翻译：电连接器具有改进的端子模块
公开(公告)号：US08021170B2
公开(公告)日：2011-09-20
申请号：US12381029
申请日：2009-03-05
申请人： Feng Pan
发明人： Feng Pan
IPC分类号： H01R13/648
CPC分类号： H01R12/712 , H01R12/724 , H01R13/514 , H01R13/6586
摘要： An electrical connector has an insulative housing (10) having a front face (14) and a rear face (12), a number of terminal modules (20) mounted to the insulative housing in a back-to-front direction. The terminal module has a base (20), a number of terminals (23) and grounding contacts (25) exposed from the base and located adjacent to one another. Each terminal has a mounting end (233) and a mating end (231). The grounding contact has a tail (253) and a contacting portion (251). The mounting ends of the terminals are positioned along a back-to-front mounting face. The mating ends of the terminals are located in a second plane parallel to said back-to-front mounting face. The contacting portions of the grounding contacts are lied in a third plane parallel to the second plane.
摘要翻译：电连接器具有绝缘壳体（10），其具有前表面（14）和后表面（12），多个端子模块（20）在背对背方向上安装到绝缘壳体上。端子模块具有底座（20），多个端子（23）和接地触头（25），从底座露出并彼此相邻。每个端子具有安装端（233）和配合端（231）。接地触点具有尾部（253）和接触部分（251）。端子的安装端沿着背对背安装面定位。端子的配合端位于平行于所述背对背安装面的第二平面中。接地触头的接触部分在平行于第二平面的第三平面中撒谎。

17. 发明授权

US07972172B2 Cable end connector assembly 失效
标题翻译：电缆端连接器总成
公开(公告)号：US07972172B2
公开(公告)日：2011-07-05
申请号：US12612708
申请日：2009-11-05
申请人： Jian-Lin Huang , Feng Pan , Chih-Ming Chien
发明人： Jian-Lin Huang , Feng Pan , Chih-Ming Chien
IPC分类号： H01R9/05
CPC分类号： H01R9/032 , H01R13/514
摘要： A cable connector assembly includes a cable (5) and a connector (100) terminated to the cable (5). The connector (100) further includes a connector body (20), a cover means (9) fastening the connector body (20) and connecting means (7) securing said cable (5) to the cover means (9). The connecting means (7) further includes an outer ferrule (73) having a first part (733) crimped onto the cable and a second part (731) crimped onto a shield (53) of the cable 5, and an inner ferrule (71) fastened substantially under the shield (53) to the outer ferrule (73) in the area of the second part (731) for making an axial locking between the outer ferrule (73) and the inner ferrule (71). The inner ferrule (71) forms a number of resilient tabs (719) flexibly abutting the cover means (9) thereby making firmly electrical connection to the cover means (9).
摘要翻译：电缆连接器组件包括电缆（5）和端接到电缆（5）的连接器（100）。连接器（100）还包括连接器主体（20），固定连接器主体（20）的盖装置（9）和将所述电缆（5）固定到盖装置（9）上的连接装置（7）。连接装置（7）还包括具有卷绕在电缆上的第一部分（733）和压接在电缆5的屏蔽（53）上的第二部分（731）的外部套圈（73）和内部套圈（71））在所述第二部分（731）的区域中基本上紧固在所述屏蔽（53）下方到所述外部套圈（73），以在所述外部套圈（73）和所述内部套圈（71）之间进行轴向锁定。内套圈（71）形成多个弹性突片（719），柔性地邻接盖装置（9），从而与盖装置（9）牢固地电连接。

18. 发明申请

US20110133820A1 Multi-Stage Charge Pump with Variable Number of Boosting Stages 审中-公开
标题翻译：具有可变数量的增压阶段的多级电荷泵
公开(公告)号：US20110133820A1
公开(公告)日：2011-06-09
申请号：US12634385
申请日：2009-12-09
申请人： Feng Pan
发明人： Feng Pan
IPC分类号： G05F1/10
CPC分类号： H02M3/073 , H02M1/12
摘要： A charge pump circuit for generating an output voltage is described. The charge pump includes multiple output generation stages connected in series, where the number of stages operating in a boosting mode is variable in order to regulate the pump. The number of stages arranged in series stays the same, but the last one or more of the stages can be operated in a filtering mode, with the number of boosting stages being lower as the regulation level goes lower. This improves the power consumption and reduces noise at lower regulated output levels.
摘要翻译：描述用于产生输出电压的电荷泵电路。电荷泵包括串联连接的多个输出发生级，其中以升压模式操作的级数是可变的，以便调节泵。串联布置的级数保持相同，但是最后一个或多个级可以以过滤模式操作，随着调节级别的降低，升压级的数量越来越少。这提高了功耗并降低了调节输出电平较低的噪声。

19. 发明申请

US20110080944A1 REAL-TIME VIDEO TRANSCODER AND METHODS FOR USE THEREWITH 审中-公开
标题翻译：实时视频转换器及其使用方法
公开(公告)号：US20110080944A1
公开(公告)日：2011-04-07
申请号：US12574802
申请日：2009-10-07
申请人： Feng Pan , Yang Liu
发明人： Feng Pan , Yang Liu
IPC分类号： H04N7/26
CPC分类号： H04N19/40 , H04N19/102 , H04N19/139 , H04N19/154 , H04N19/159 , H04N19/172 , H04N19/176 , H04N19/46 , H04N19/61
摘要： A transcoder includes a direct transcoder that generates a first portion of a transcoded video stream by reusing a plurality of encoding parameters of a compressed video stream. A cascaded transcoder generates a second portion of the transcoded video stream by decoding the compressed video stream into video data in an uncompressed video format and by re-encoding the video data. A transcoding decision generator generates a transcoding indicator, based on the compressed video stream. A switching module selects the direct transcoder for the first portion of the transcoded video stream and the cascaded transcoder for the second portion of the transcoded video stream, based on the transcoding indicator.
摘要翻译：代码转换器包括直接代码转换器，其通过重新使用压缩视频流的多个编码参数来生成代码转换的视频流的第一部分。级联代码转换器通过将压缩视频流解码为未压缩视频格式的视频数据并通过对视频数据进行重新编码来生成转码视频流的第二部分。代码转换决策发生器基于压缩的视频流生成代码转换指示符。基于代码转换指示符，切换模块为代码转换的视频流的第一部分和用于转码视频流的第二部分的级联代码转换器选择直接代码转换器。

20. 发明授权

US07889575B2 On-chip bias voltage temperature coefficient self-calibration mechanism 有权
标题翻译：片上偏置电压温度系数自校准机制
公开(公告)号：US07889575B2
公开(公告)日：2011-02-15
申请号：US12235474
申请日：2008-09-22
申请人： Yuxin Wang , Feng Pan , Byungki Woo , Trung Pham , Khin Htoo
发明人： Yuxin Wang , Feng Pan , Byungki Woo , Trung Pham , Khin Htoo
IPC分类号： G11C5/14
CPC分类号： H03K17/145 , G11C5/143 , G11C7/04 , G11C2207/2254 , H03K2217/0018
摘要： Techniques and corresponding circuitry for deriving a supply a bias voltage for a memory cell array from a received reference voltage is presented. The circuit includes a voltage determination circuit, which is connected to receive the reference voltage and generate from it the bias voltage, a temperature sensing circuit, and a calibration circuit. The calibration circuit is connected to receive the bias voltage and to receive a temperature indication from the temperature sensing circuit and determine from the bias voltage and temperature indication a compensation factor that is supplied to the voltage determination circuit, which adjusts the bias voltage based upon the compensation factor.
摘要翻译：提供了用于从接收的参考电压导出用于存储单元阵列的偏置电压的技术和相应的电路。该电路包括电压确定电路，其连接以接收参考电压并从其产生偏置电压，温度感测电路和校准电路。连接校准电路以接收偏置电压并从温度检测电路接收温度指示，并根据偏置电压和温度指示确定提供给电压确定电路的补偿因子，该电压确定电路基于补偿因子。

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