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11. 发明授权

US07227778B2 Semiconductor device and writing method 有权
标题翻译：半导体器件和写入方法
公开(公告)号：US07227778B2
公开(公告)日：2007-06-05
申请号：US11194023
申请日：2005-07-29
申请人： Shigekazu Yamada
发明人： Shigekazu Yamada
IPC分类号： G11C11/34 , G11C16/06
CPC分类号： G11C11/5628 , G11C16/10 , G11C2216/14
摘要： A semiconductor device has a memory cell array including a multi-level memory cell having multiple and different threshold values, a first latch circuit latching information of multiple-word of input information, a second latch circuit latching write information in which the information of the multiple-word of the input information is converted into information according to each level of the multi-level memory cell, a write circuit writing information into the multi-level memory cell on a group basis corresponding to the number of memory cells simultaneously programmable, according to the write information, and a control circuit controlling programming the memory cell array. The information is simultaneously programmed on the group basis into which multiple-word input information is divided, and makes it possible to shorten a program period substantially on a word basis. The program period is not increased, even if programming and verification are repeated several times in programming the multi-level memory cell.
摘要翻译：一种半导体器件具有存储单元阵列，该存储单元阵列包括具有多个和不同阈值的多电平存储单元，第一锁存电路锁存多字输入信息的信息，第二锁存电路锁存写信息，根据多级存储器单元的每个级别将输入信息的字转换为信息，写电路根据与可同时编程的存储单元的数量对应的组，将信息写入多级存储器单元，根据写入信息，以及控制对存储单元阵列进行编程的控制电路。该信息同时被编程在分组多字输入信息的组基础上，并且使得可以基本上基于单词缩短程序周期。即使编程和验证在编程多层存储单元中重复多次，程序周期也不会增加。

12. 发明申请

US20060002200A1 Voltage control circuit and semiconductor device 有权
标题翻译：电压控制电路和半导体器件
公开(公告)号：US20060002200A1
公开(公告)日：2006-01-05
申请号：US11166575
申请日：2005-06-24
申请人： Shigekazu Yamada
发明人： Shigekazu Yamada
IPC分类号： G11C7/00
CPC分类号： G11C16/30 , G11C5/14 , H02M3/07
摘要： A voltage control circuit includes capacitors, first switches that are respectively provided to the capacitors and selectively couple the capacitors with a given node, and second switches that are respectively provided between the first switches and the given node and selectively connect the first switches to the given node.
摘要翻译：电压控制电路包括电容器，分别提供给电容器并选择性地将电容器与给定节点耦合的第一开关以及分别设置在第一开关和给定节点之间并且选择性地将第一开关连接到给定节点的第二开关节点。

13. 发明授权

US06944057B1 Method to obtain temperature independent program threshold voltage distribution using temperature dependent voltage reference 有权
标题翻译：使用温度依赖电压参考获得温度独立程序阈值电压分布的方法
公开(公告)号：US06944057B1
公开(公告)日：2005-09-13
申请号：US10431065
申请日：2003-05-06
申请人： Edward F. Runnion , Tien-Chun Yang , Binh Quang Le , Shigekazu Yamada , Darlene G. Hamilton , Ming-Huei Shieh , Pau-Ling Chen , Kazuhiro Kurihara
发明人： Edward F. Runnion , Tien-Chun Yang , Binh Quang Le , Shigekazu Yamada , Darlene G. Hamilton , Ming-Huei Shieh , Pau-Ling Chen , Kazuhiro Kurihara
IPC分类号： G11C16/06
CPC分类号： G11C16/3418 , G11C16/10
摘要： A method for controlling gate voltage in a memory device is described. The method includes providing a circuit that is adapted to be coupled with the memory device. The circuit is for generating a reference voltage. The method further includes utilizing the reference voltage provided by the circuit to apply a voltage at a gate of the memory device. The voltage has a value corresponding to a temperature of the memory device. The method also includes retaining a proportional relationship between the reference voltage and the temperature of the memory device, regardless of the change in the temperature of the memory device. The reference voltage provides a substantially constant programming time for the memory device regardless of the temperature of the memory device.
摘要翻译：描述了一种用于控制存储器件中的栅极电压的方法。该方法包括提供适于与存储器件耦合的电路。该电路用于产生参考电压。该方法还包括利用由电路提供的参考电压来在存储器件的栅极处施加电压。电压具有对应于存储器件的温度的值。该方法还包括保持参考电压与存储器件的温度之间的比例关系，而与存储器件的温度变化无关。参考电压为存储器件提供基本上恒定的编程时间，而与存储器件的温度无关。

14. 发明授权

US06781884B2 System for setting memory voltage threshold 有权
标题翻译：用于设置存储器电压阈值的系统
公开(公告)号：US06781884B2
公开(公告)日：2004-08-24
申请号：US10096338
申请日：2002-03-11
申请人： Shigekazu Yamada
发明人： Shigekazu Yamada
IPC分类号： G11C1606
CPC分类号： G11C16/3459 , G11C16/10 , G11C16/3454 , G11C2216/14
摘要： System to set threshold voltages in a memory device. The system includes apparatus to set voltage threshold levels of a plurality of memory cells in a memory device. The plurality of memory cells are coupled to a common word line. The apparatus includes a plurality of gates that are coupled between a voltage source and the plurality of memory cells, the gates include control inputs that receive control signals that open and close each gate, so that when a selected gate is closed, the voltage source is coupled to a selected memory cell and when the selected gate is open the current source is uncoupled from the selected memory cell. The apparatus also includes control logic that generates the control signals to open and close the gates to individually enable and disable programming of the voltage threshold of each of the memory cells.
摘要翻译：用于设置存储器件中的阈值电压的系统。该系统包括用于设置存储器件中的多个存储器单元的电压阈值电平的装置。多个存储单元耦合到公共字线。该装置包括耦合在电压源和多个存储单元之间的多个栅极，门包括控制输入，其接收打开和关闭每个栅极的控制信号，使得当所选择的栅极闭合时，电压源为耦合到所选择的存储器单元，并且当所选择的栅极打开时，电流源与所选存储单元分离。该装置还包括控制逻辑，其产生控制信号以打开和关闭栅极以单独地启用和禁用每个存储单元的电压阈值的编程。

15. 外观设计

USD400182S Motor controller 失效
公开(公告)号：USD400182S
公开(公告)日：1998-10-27
申请号：US78466
申请日：1997-10-27
申请人： Shigekazu Yamada
设计人： Shigekazu Yamada

16. 发明授权

US09159452B2 Automatic word line leakage measurement circuitry 有权
标题翻译：自动字线泄漏测量电路
公开(公告)号：US09159452B2
公开(公告)日：2015-10-13
申请号：US12271140
申请日：2008-11-14
申请人： Shigekazu Yamada
发明人： Shigekazu Yamada
IPC分类号： G11C16/06 , G11C29/02 , G11C16/04 , G11C29/12 , G11C29/50
CPC分类号： G11C7/1006 , G11C7/062 , G11C16/04 , G11C16/08 , G11C29/02 , G11C29/025 , G11C2029/1202 , G11C2029/5006
摘要： The present invention is a circuit and method for measuring leakage on the plurality of word lines in a memory device. In one embodiment, a memory device may include a leakage measurement circuit that is coupled to a plurality of word lines of the memory device. The leakage measurement circuit may be operable to generate a reference current and to determine whether a leakage current on one of the plurality of word lines is acceptable relative to the reference current. In another embodiment, a method may include determining whether leakage on one of a plurality of word lines of a memory device is allowable using a circuit in the memory device.
摘要翻译：本发明是用于测量存储装置中的多条字线上的泄漏的电路和方法。在一个实施例中，存储器件可以包括耦合到存储器件的多个字线的泄漏测量电路。泄漏测量电路可以用于产生参考电流并且确定多个字线中的一个字线上的泄漏电流相对于参考电流是否可接受。在另一个实施例中，一种方法可以包括使用存储器件中的电路来确定存储器件的多个字线中的一个字线上的泄漏是否被允许。

17. 发明授权

US08482986B2 Word line drivers in non-volatile memory device and method having a shared power bank and processor-based systems using same 有权
标题翻译：具有共享电源组和使用其的基于处理器的系统的非易失性存储器件和方法中的字线驱动器
公开(公告)号：US08482986B2
公开(公告)日：2013-07-09
申请号：US13550241
申请日：2012-07-16
申请人： Shigekazu Yamada
发明人： Shigekazu Yamada
IPC分类号： G11C16/06
CPC分类号： G11C16/08 , G11C8/08
摘要： A word line driver system that utilizes a voltage selection circuit to supply one of several voltages to an output node coupled to a plurality of word line control circuits. Each word line control circuit is coupled to a respective word line in an array of non-volatile memory cells. The voltage selection circuit may include selectable low pass filters for filtering the supplied voltage supplied to the word lines in the array of memory cells without significantly increasing the overall die-size of the device.
摘要翻译：一种字线驱动器系统，其利用电压选择电路将多个电压中的一个提供给耦合到多个字线控制电路的输出节点。每个字线控制电路耦合到非易失性存储器单元阵列中的相应字线。电压选择电路可以包括可选择的低通滤波器，用于对提供给存储器单元阵列中的字线的提供的电压进行滤波，而不会显着增加器件的整体裸片尺寸。

18. 发明申请

US20130003464A1 CIRCUITS, SYSTEMS, AND METHODS FOR DRIVING HIGH AND LOW VOLTAGES ON BIT LINES IN NON-VOLATILE MEMORY 有权
标题翻译：用于在非易失性存储器中驱动位线上的高电压和低电压的电路，系统和方法
公开(公告)号：US20130003464A1
公开(公告)日：2013-01-03
申请号：US13610512
申请日：2012-09-11
申请人： Shigekazu Yamada
发明人： Shigekazu Yamada
IPC分类号： G11C16/06
CPC分类号： G11C7/12 , G11C16/24 , G11C16/30
摘要： An integrated circuit bit line driver system includes a plurality of bit line drivers coupled to respective bit lines of an array of non-volatile memory cells. Each of the bit line drivers includes a bias transistor through which an input signal is coupled to the respective bit line. The bit line driver system includes a bias voltage circuit that generates a bias voltage that is coupled to the respective gates of the bias transistors. The bias voltage circuit initially accelerates the charging of the transistor gates, and subsequently completes charging the gates at a slower rate. The bias voltage is generated using a diode-coupled transistor having electrical characteristics the match those of the bias transistors so that the bias voltage varies with process or temperature variations of the integrated circuit in the same manner as the threshold voltage of the bias transistors vary with process or temperature variations.
摘要翻译：集成电路位线驱动器系统包括耦合到非易失性存储器单元阵列的相应位线的多个位线驱动器。每个位线驱动器包括偏置晶体管，输入信号通过偏置晶体管耦合到相应的位线。位线驱动器系统包括偏置电压电路，其产生耦合到偏置晶体管的各个栅极的偏置电压。偏置电压电路最初加速晶体管栅极的充电，随后以较慢的速率完成对栅极的充电。使用具有与偏置晶体管的电特性匹配的电特性的二极管耦合晶体管产生偏置电压，使得偏置电压以与偏置晶体管的阈值电压变化相同的方式随集成电路的过程或温度变化而变化过程或温度变化。

19. 发明申请

US20120218833A1 LEAKAGE MEASUREMENT SYSTEMS 有权
标题翻译：泄漏测量系统
公开(公告)号：US20120218833A1
公开(公告)日：2012-08-30
申请号：US13036409
申请日：2011-02-28
申请人： Shigekazu Yamada
发明人： Shigekazu Yamada
IPC分类号： G11C7/00 , G11C5/14
CPC分类号： G11C7/06 , G11C16/00 , G11C16/0483 , G11C29/025 , G11C29/50008 , G11C2029/1202 , G11C2029/5006
摘要： Described examples include leakage measurement systems and methods for measuring leakage current between a word line at a boosted voltage and a word line at a supply voltage. The boosted voltage may be generated by charge pump circuitry. Examples of leakage measurement systems described herein may be included in memory devices.
摘要翻译：所描述的示例包括泄漏测量系统和用于测量升压电压的字线与电源电压下的字线之间的漏电流的方法。升压电压可能由电荷泵电路产生。这里描述的泄漏测量系统的示例可以包括在存储器设备中。

20. 发明授权

US08194446B2 Methods for programming a memory device and memory devices using inhibit voltages that are less than a supply voltage 有权
标题翻译：使用小于电源电压的禁止电压对存储器件和存储器件进行编程的方法
公开(公告)号：US08194446B2
公开(公告)日：2012-06-05
申请号：US13051380
申请日：2011-03-18
申请人： Shigekazu Yamada
发明人： Shigekazu Yamada
IPC分类号： G11C16/00
CPC分类号： G11C16/10 , G11C16/0433
摘要： Methods for programming a memory array and memory devices are disclosed. In one such method, inhibited bit lines are charged to an inhibit voltage that is less than a supply voltage. The word lines of memory cells to be programmed are biased at a programming preparation voltage that is less than a nominal programming preparation voltage as used in the conventional art. Programming pulses can be applied to selected word lines of the memory cells to be programmed when the uninhibited bit lines are at 0V.
摘要翻译：公开了用于编程存储器阵列和存储器件的方法。在一种这样的方法中，禁止的位线被充电到小于电源电压的抑制电压。要编程的存储器单元的字线被偏置在比常规技术中使用的小于标称编程准备电压的编程准备电压。当非禁止位线为0V时，编程脉冲可以施加到要编程的存储单元的选定字线。

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