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    • 13. 发明授权
    • Stacked-fringe integrated circuit capacitors
    • 堆叠边缘集成电路电容器
    • US5978206A
    • 1999-11-02
    • US940847
    • 1997-09-30
    • Ken A. NishimuraScott D. WillinghamWilliam J. McFarland
    • Ken A. NishimuraScott D. WillinghamWilliam J. McFarland
    • H01G4/33H01L21/02H01L21/822H01L23/522H01L27/04H01L27/08H01L29/92H01G4/005H01G4/228
    • H01L27/0805H01L23/5223H01L28/82H01L2924/0002
    • A capacitor that is adapted for construction over a substrate in the metal interconnect layers provided by conventional integrated circuit processes. The capacitor includes a first conducting layer separated from the substrate by a first dielectric layer and a second conducting layer separated from the first conduction layer by a second dielectric layer. The second conducting layer is divided into a plurality of electrically isolated conductors in an ordered array. Every other one of the conductors is connected to a first terminal, and the remaining conductors are connected to a second terminal. The first conducting layer includes at least one conductor which is connected to the first terminal. In one embodiment of the invention, the first conducting layer also includes a plurality of electrically isolated conductors in an ordered array, every other one of the conductors being connected to the first terminal and the remaining conductors being connected the second terminal.
    • 适用于通过常规集成电路工艺提供的金属互连层中的衬底上的结构的电容器。 电容器包括通过第一电介质层与衬底分离的第一导电层和通过第二电介质层与第一导电层分离的第二导电层。 第二导电层被分成多个以有序阵列的电绝缘导体。 导体中的每一根连接到第一端子,其余的导体连接到第二端子。 第一导电层包括连接到第一端子的至少一个导体。 在本发明的一个实施例中,第一导电层还包括有序阵列中的多个电绝缘导体,每个导体中的每一个连接到第一端子,其余的导体与第二端子连接。
    • 17. 发明申请
    • Method and system for dynamic supply voltage biasing of integrated circuit blocks
    • 集成电路块的动态电源电压偏置方法和系统
    • US20080150614A1
    • 2008-06-26
    • US11642335
    • 2006-12-20
    • Peter VancorenlandLawrence DerScott D. Willingham
    • Peter VancorenlandLawrence DerScott D. Willingham
    • G05F3/02
    • G05F3/24
    • A system and method are disclosed for using dynamic supply voltages to bias circuit blocks within integrated circuits. By considering current requirements for circuit blocks based upon process variations and environmental conditions, a dynamic supply voltage can be used such that operational integrity can be maintained while reducing power consumption. By using a dynamic supply voltage, circuit blocks can be operated at a desired speed while still reducing the power required for this operation. To implement this dynamic supply regulation, circuit elements are provided within a variable supply voltage circuit that cause the dynamic supply voltage to vary based upon operational parameters such as process variations and environment parameters. As such, circuit blocks can be provided a supply voltage high enough to allow operational integrity at required speeds but not so high as to waste power by unnecessarily increasing current consumption.
    • 公开了一种使用动态电源电压来偏置集成电路内的电路块的系统和方法。 通过考虑基于工艺变化和环境条件的电路块的当前要求,可以使用动态电源电压,从而可以在降低功耗的同时保持操作完整性。 通过使用动态电源电压,可以以期望的速度操作电路块,同时仍然减少该操作所需的功率。 为了实现这种动态电源调节,电路元件被提供在可变电源电压电路内,使得动态电源电压基于诸如工艺变化和环境参数的操作参数而变化。 因此,电路块可以被提供足够高的电源电压以允许在所需速度下的操作完整性,但不高于通过不必要地增加电流消耗来浪费功率。
    • 19. 发明授权
    • Wireless communication system and method using clock swapping during image rejection calibration
    • 无线通信系统和方法在镜像抑制校准期间使用时钟交换
    • US07583946B2
    • 2009-09-01
    • US11340941
    • 2006-01-27
    • Donald A. KerthSrihari AdireddyBrian Douglas GreenTod PaulusScott D. Willingham
    • Donald A. KerthSrihari AdireddyBrian Douglas GreenTod PaulusScott D. Willingham
    • H04B1/06
    • H04B1/28H04B17/21
    • A wireless communication receiver is disclosed that operates in a test mode to determine image correction information that is used to suppress undesired image signals when the receiver switches to a normal operational mode. In one embodiment, the receiver includes a frequency synthesizer coupled by a quadrature divider to an in-phase (I) mixer and a quadrature mixer. The mixers are coupled by respective analog to digital converters (ADCs) to respective I and Q channel inputs of a digital signal processor (DSP). In the test mode, a test tone is provided to the mixer inputs. The test tone is divided down further and provided to clock the frequency synthesizer, the ADCs and the DSP. This configuration locks together the mixers, frequency synthesizer, ADCs and DSP ratiometrically in frequency during the test mode while image correction information is being determined. When the receiver switches to a normal operating mode, the frequency synthesizer, ADCs and DSP are clocked by a main clock signal instead of the divided down test tone, and the test tone is removed from the mixers.
    • 公开了一种在测试模式下操作以确定当接收机切换到正常操作模式时用于抑制不期望的图像信号的图像校正信息的无线通信接收机。 在一个实施例中,接收机包括由正交分频器耦合到同相(I)混频器和正交混频器的频率合成器。 混频器由相应的模数转换器(ADC)耦合到数字信号处理器(DSP)的相应的I和Q通道输入端。 在测试模式下,向混音器输入提供测试音。 测试音被进一步分频并提供给时钟频率合成器,ADC和DSP。 该配置在确定图像校正信息期间在测试模式期间将混频器,频率合成器,ADC和DSP按比例的频率锁定在频率上。 当接收机切换到正常工作模式时,频率合成器,ADC和DSP由主时钟信号而不是分频测试音来计时,测试音从混频器中移除。