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11. 发明申请

US20130088927A1 SYSTEM AND METHOD FOR GENERATING A CLOCK 有权
标题翻译：用于产生时钟的系统和方法
公开(公告)号：US20130088927A1
公开(公告)日：2013-04-11
申请号：US13253822
申请日：2011-10-05
申请人： Annie-Li-Keow Lum , Derek C. Tao , Bing Wang
发明人： Annie-Li-Keow Lum , Derek C. Tao , Bing Wang
IPC分类号： G11C8/18 , G11C7/10 , G11C7/00
CPC分类号： G11C7/222 , G11C11/412 , G11C11/413
摘要： A first clock is received by a memory macro. In response to a first clock transition of the first clock, a first transition of a second clock and of a third clock is generated. A tracking transition of a tracking signal is caused by the second clock. Based on a later transition of a second clock transition of the first clock and the tracking transition of the tracking signal, a second transition of the third clock is generated. The third clock is for use by an input-output of the memory macro.
摘要翻译：存储器宏接收到第一个时钟。响应于第一时钟的第一时钟转换，产生第二时钟和第三时钟的第一转换。跟踪信号的跟踪转换是由第二个时钟引起的。基于第一时钟的第二时钟转换和跟踪信号的跟踪转变的稍后转换，产生第三时钟的第二转换。第三个时钟由内存宏的输入输出使用。

12. 发明授权

US09087565B2 Pre-charging a data line 有权
标题翻译：预充电数据线
公开(公告)号：US09087565B2
公开(公告)日：2015-07-21
申请号：US13793815
申请日：2013-03-11
申请人： Annie-Li-Keow Lum , Derek C. Tao
发明人： Annie-Li-Keow Lum , Derek C. Tao
IPC分类号： G11C7/00 , G11C7/12 , G11C7/10 , G11C11/419
CPC分类号： G11C11/419 , G11C7/1048 , G11C7/12
摘要： A control circuit includes a data driver, a charge circuit, and a first data line coupled with the data driver and the charge circuit. The charge circuit is configured to charge the first data line when the first data line is selected for accessing a memory cell corresponding to the first data line and to not charge the first data line when the first data line is not selected for accessing the memory cell. The data driver, based on a first control signal, is configured to transfer a signal on the first data line to an output of the data driver.
摘要翻译：控制电路包括数据驱动器，充电电路和与数据驱动器和充电电路耦合的第一数据线。所述充电电路被配置为当所述第一数据线被选择用于对与所述第一数据线相对应的存储单元进行访问时对所述第一数据线进行充电，并且当所述第一数据线未被选择用于访问所述存储器单元时，。基于第一控制信号的数据驱动器被配置为将第一数据线上的信号传送到数据驱动器的输出。

13. 发明授权

US08913440B2 Tracking mechanisms 有权
标题翻译：跟踪机制
公开(公告)号：US08913440B2
公开(公告)日：2014-12-16
申请号：US13253749
申请日：2011-10-05
申请人： Derek C. Tao , Annie-Li-Keow Lum , Yukit Tang , Kuoyuan (Peter) Hsu
发明人： Derek C. Tao , Annie-Li-Keow Lum , Yukit Tang , Kuoyuan (Peter) Hsu
IPC分类号： G11C7/10 , G11C11/419
CPC分类号： G11C7/222 , G11C7/10 , G11C7/1051 , G11C11/419
摘要： A tracking edge of a tracking signal is activated. A buffer is turned off and a latching circuit is turned on, based on the tracking edge of the tracking signal. A buffer output of the buffer is coupled to a latch output of the latching circuit at a node. The buffer receives a data line of a memory macro.
摘要翻译：跟踪信号的跟踪边缘被激活。基于跟踪信号的跟踪边缘，缓冲器被关闭并且锁存电路被接通。缓冲器的缓冲器输出耦合到节点处的锁存电路的锁存器输出。缓冲区接收一个内存宏的数据行。

14. 发明授权

US08619478B2 System and method for generating a clock 有权
标题翻译：用于产生时钟的系统和方法
公开(公告)号：US08619478B2
公开(公告)日：2013-12-31
申请号：US13253822
申请日：2011-10-05
申请人： Annie-Li-Keow Lum , Derek C. Tao , Bing Wang
发明人： Annie-Li-Keow Lum , Derek C. Tao , Bing Wang
IPC分类号： G11C7/10
CPC分类号： G11C7/222 , G11C11/412 , G11C11/413
摘要： A first clock is received by a memory macro. In response to a first clock transition of the first clock, a first transition of a second clock and of a third clock is generated. A tracking transition of a tracking signal is caused by the second clock. Based on a later transition of a second clock transition of the first clock and the tracking transition of the tracking signal, a second transition of the third clock is generated. The third clock is for use by an input-output of the memory macro.
摘要翻译：存储器宏接收到第一个时钟。响应于第一时钟的第一时钟转换，产生第二时钟和第三时钟的第一转换。跟踪信号的跟踪转换是由第二个时钟引起的。基于第一时钟的第二时钟转换和跟踪信号的跟踪转变的稍后转换，产生第三时钟的第二转换。第三个时钟由内存宏的输入输出使用。

15. 发明授权

US08605523B2 Tracking capacitive loads 有权
标题翻译：跟踪容性负载
公开(公告)号：US08605523B2
公开(公告)日：2013-12-10
申请号：US13399877
申请日：2012-02-17
申请人： Derek C. Tao , Young Seog Kim , Kuoyuan (Peter) Hsu , Bing Wang , Annie-Li-Keow Lum
发明人： Derek C. Tao , Young Seog Kim , Kuoyuan (Peter) Hsu , Bing Wang , Annie-Li-Keow Lum
IPC分类号： G11C7/00
CPC分类号： G11C29/24 , G11C7/222 , G11C11/41 , G11C29/50012 , G11C2029/5002
摘要： A time delay is determined to cover a timing of a memory cell in a memory macro having a tracking circuit. Based on the time delay, a capacitance corresponding to the time delay is determined. A capacitor having the determined capacitance is utilized. The capacitor is coupled to a first data line of a tracking cell of the tracking circuit. A first transition of the first data line causes a first transition of a second data line of the memory cell.
摘要翻译：确定时间延迟以覆盖具有跟踪电路的存储器宏中的存储器单元的定时。基于时间延迟，确定与时间延迟相对应的电容。使用具有确定的电容的电容器。电容器耦合到跟踪电路的跟踪单元的第一数据线。第一数据线的第一转变导致存储器单元的第二数据线的第一转变。

16. 发明授权

US08976614B2 Tracking scheme for memory 有权
标题翻译：内存跟踪方案
公开(公告)号：US08976614B2
公开(公告)日：2015-03-10
申请号：US13026021
申请日：2011-02-11
申请人： Yong Zhang , Derek C. Tao , Dongsik Jeong , Young Suk Kim , Kuoyuan (Peter) Hsu
发明人： Yong Zhang , Derek C. Tao , Dongsik Jeong , Young Suk Kim , Kuoyuan (Peter) Hsu
IPC分类号： G11C7/06 , G11C7/22 , G11C11/419
CPC分类号： G11C7/227 , G11C11/419
摘要： A memory has a tracking circuit for a read tracking operation. The memory includes a memory bit cell array, a tracking column, a tracking row, a sense amplifier row coupled to the memory bit cell array and the tracking row, and a sense amplifier enable logic. The memory further includes a tracking bit line coupled to the tracking column and the sense amplifier enable logic, and a tracking word line coupled to the tracking row and the sense amplifier enable logic. The tracking circuit is configured to track a column time delay along the tracking column before a row time delay along the tracking row.
摘要翻译：存储器具有用于读取跟踪操作的跟踪电路。存储器包括存储位单元阵列，跟踪列，跟踪行，耦合到存储器位单元阵列和跟踪行的读出放大器行以及读出放大器使能逻辑。存储器还包括耦合到跟踪列和读出放大器使能逻辑的跟踪位线，以及耦合到跟踪行和读出放大器使能逻辑的跟踪字线。跟踪电路被配置为沿着跟踪行在行时间延迟之前跟踪沿着跟踪列的列时间延迟。

17. 发明授权

US08619477B2 Two-port SRAM write tracking scheme 有权
标题翻译：双端口SRAM写入跟踪方案
公开(公告)号：US08619477B2
公开(公告)日：2013-12-31
申请号：US12839624
申请日：2010-07-20
申请人： Bing Wang , Kuoyuan (Peter) Hsu , Derek C. Tao
发明人： Bing Wang , Kuoyuan (Peter) Hsu , Derek C. Tao
IPC分类号： G11C7/10
CPC分类号： G11C11/419 , G11C11/413
摘要： A Static Random Access Memory (SRAM) includes at least two memory cells sharing a read bit line (RBL) and a write bit line (WBL). Each memory cell is coupled to a respective read word line (RWL) and a respective write word line (WWL). A write tracking control circuit is coupled to the memory cells for determining a write time of the memory cells. The write tracking control circuit is capable of receiving an input voltage and providing an output voltage. The respective RWL and the respective WWL of each memory cell are asserted during a write tracking operation.
摘要翻译：静态随机存取存储器（SRAM）包括共享读位线（RBL）和写位线（WBL）的至少两个存储器单元。每个存储单元耦合到相应的读字线（RWL）和相应的写字线（WWL）。写跟踪控制电路耦合到存储器单元，以确定存储器单元的写入时间。写跟踪控制电路能够接收输入电压并提供输出电压。在写跟踪操作期间，各存储单元的相应RWL和相应的WWL被断言。

18. 发明授权

US08964492B2 Tracking mechanism for writing to a memory cell 有权
标题翻译：用于写入存储单元的跟踪机制
公开(公告)号：US08964492B2
公开(公告)日：2015-02-24
申请号：US13560461
申请日：2012-07-27
申请人： Kuoyuan (Peter) Hsu , Bing Wang , Derek C. Tao , Yukit Tang , Kai Fan
发明人： Kuoyuan (Peter) Hsu , Bing Wang , Derek C. Tao , Yukit Tang , Kai Fan
IPC分类号： G11C7/00 , G11C7/02
CPC分类号： G11C7/222 , G11C7/12 , G11C7/227 , G11C11/419
摘要： A circuit includes a tracking write circuit and a write circuit. Various write signals of the write circuit are generated based on tracking signals of the tracking write circuit. The write signals are used in a write operation of a memory cell.
摘要翻译：电路包括跟踪写入电路和写入电路。基于跟踪写入电路的跟踪信号产生写入电路的各种写入信号。写信号用于存储单元的写入操作。

19. 发明授权

US08450778B2 Method and apparatus for memory cell layout 有权
标题翻译：用于存储单元布局的方法和装置
公开(公告)号：US08450778B2
公开(公告)日：2013-05-28
申请号：US12862387
申请日：2010-08-24
申请人： Jacklyn Chang , Kuoyuan Hsu , Derek C. Tao
发明人： Jacklyn Chang , Kuoyuan Hsu , Derek C. Tao
IPC分类号： H01L27/11
CPC分类号： H01L27/1104 , G11C11/412 , H01L27/0207
摘要： A semiconductor device has first and second interconnect structures in first and second columns, respectively, of an array. Each of the first and second interconnect structures has a reference voltage node and first, second, third, and fourth conductors that are coupled to each other and formed at a first layer, a second layer, a third layer, and a fourth layer, respectively, over a substrate having a plurality of devices defining a plurality of bit cells. The reference voltage node of each interconnect structure provides a respectively separate reference voltage to a bit cell corresponding to said interconnect structure. None of the first, second, third, and fourth conductors in either interconnect structure is connected to a corresponding conductor in the other interconnect structure. The second layer is above the first layer, the third layer is above the second layer, and the fourth layer is above the third layer.
摘要翻译：半导体器件分别在阵列的第一和第二列中具有第一和第二互连结构。第一和第二互连结构中的每一个具有参考电压节点和彼此耦合并分别形成在第一层，第二层，第三层和第四层上的第一，第二，第三和第四导体在具有限定多个位单元的多个器件的衬底上。每个互连结构的参考电压节点向对应于所述互连结构的位单元提供分别分离的参考电压。在互连结构中的第一，第二，第三和第四导体中的任一个都不连接到另一个互连结构中的相应导体。第二层在第一层之上，第三层位于第二层之上，第四层位于第三层之上。

20. 发明授权

US08159862B2 Recycling charges 有权
标题翻译：回收费用
公开(公告)号：US08159862B2
公开(公告)日：2012-04-17
申请号：US12843366
申请日：2010-07-26
申请人： Young Seog Kim , Kuoyuan (Peter) Hsu , Derek C. Tao , Young Suk Kim
发明人： Young Seog Kim , Kuoyuan (Peter) Hsu , Derek C. Tao , Young Suk Kim
IPC分类号： G11C11/00 , G11C7/00 , G11C5/14
CPC分类号： G11C11/412
摘要： A circuit includes a first node; a second node; a first PMOS transistor having a source coupled to the first node, a drain coupled to a first control transistor, and a gate driven by a first voltage; and a first NMOS transistor having a source coupled to the second node, a drain coupled to the first control transistor, and a gate driven by a second voltage. The first PMOS transistor is configured to automatically turn off based on the first voltage and a first node voltage at the first node. The first NMOS transistor is configured to automatically turn off based on the second voltage and a second node voltage at the second node. When the first PMOS transistor, the control transistor, and the first NMOS transistor are on, the first node voltage is lowered while the second voltage is raised.
摘要翻译：电路包括第一节点; 第二个节点; 具有耦合到第一节点的源极的第一PMOS晶体管，耦合到第一控制晶体管的漏极和由第一电压驱动的栅极; 以及第一NMOS晶体管，其具有耦合到第二节点的源极，耦合到第一控制晶体管的漏极和由第二电压驱动的栅极。第一PMOS晶体管被配置为基于第一节点处的第一电压和第一节点电压自动关闭。第一NMOS晶体管被配置为基于第二节点处的第二电压和第二节点电压自动关闭。当第一PMOS晶体管，控制晶体管和第一NMOS晶体管导通时，第一节点电压降低，而第二电压升高。

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