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11. 发明申请

US20120175023A1 SELF-ALIGNED COMPOSITE M-MOx/DIELECTRIC CAP FOR Cu INTERCONNECT STRUCTURES 有权
标题翻译：用于Cu互连结构的自对准复合材料M-MOx /电介质盖
公开(公告)号：US20120175023A1
公开(公告)日：2012-07-12
申请号：US13420728
申请日：2012-03-15
申请人： Son Van Nguyen , Alfred Grill , Thomas J. Haigh, JR. , Hosadurga Shobha , Tuan A. Vo
发明人： Son Van Nguyen , Alfred Grill , Thomas J. Haigh, JR. , Hosadurga Shobha , Tuan A. Vo
IPC分类号： C23C8/00 , C23C28/04
CPC分类号： H01L21/76849 , H01L21/76846 , H01L21/76864 , H01L21/76867
摘要： An interconnect structure is provided that has improved electromigration resistance as well as methods of forming such an interconnect structure. The interconnect structure includes a composite M-MOx cap located at least on the upper surface of the Cu-containing material within the at least one opening. The composite M-MOx cap includes an upper region that is composed of the metal having a higher affinity for oxygen than copper and copper oxide and a lower region that is composed of a non-stoichiometric oxide of said metal.
摘要翻译：提供了具有改进的电迁移阻力的互连结构以及形成这种互连结构的方法。互连结构包括至少位于至少一个开口内的含Cu材料的上表面上的复合M-MOx帽。复合M-MOx帽包括由与氧和氧化铜相比具有比氧更高的亲和性的金属构成的上部区域和由所述金属的非化学计量氧化物构成的下部区域。

12. 发明授权

US07892648B2 SiCOH dielectric material with improved toughness and improved Si-C bonding 有权
标题翻译： SiCOH介电材料具有改善的韧性和改善的Si-C键合
公开(公告)号：US07892648B2
公开(公告)日：2011-02-22
申请号：US11040778
申请日：2005-01-21
申请人： Daniel C. Edelstein , Stephen M. Gates , Alfred Grill , Michael Lane , Robert D. Miller , Deborah A. Neumayer , Son Van Nguyen
发明人： Daniel C. Edelstein , Stephen M. Gates , Alfred Grill , Michael Lane , Robert D. Miller , Deborah A. Neumayer , Son Van Nguyen
IPC分类号： B32B9/04
CPC分类号： H01L31/103 , Y10T428/31663
摘要： A low-k dielectric material with increased cohesive strength for use in electronic structures including interconnect and sensing structures is provided that includes atoms of Si, C, O, and H in which a fraction of the C atoms are bonded as Si—CH3 functional groups, and another fraction of the C atoms are bonded as Si—R—Si, wherein R is phenyl, —[CH2]n— where n is greater than or equal to 1, HC═CH, C═CH2, C≡C or a [S]n linkage, where n is a defined above.
摘要翻译：提供了一种用于包括互连和感测结构的电子结构中具有增强的内聚强度的低k电介质材料，其包括其中一部分C原子键合为Si-CH 3官能团的Si，C，O和H的原子，并且C原子的另一部分键合为Si-R-Si，其中R是苯基， - [CH 2] n - ，其中n大于或等于1，HC = CH，C = CH 2，C≡C或一个[S] n连接，其中n是上面定义的。

13. 发明授权

US07479306B2 SiCOH dielectric material with improved toughness and improved Si-C bonding, semiconductor device containing the same, and method to make the same 失效
标题翻译： SiCOH介电材料具有改善的韧性和改善的Si-C键合，含有其的半导体器件及其制造方法
公开(公告)号：US07479306B2
公开(公告)日：2009-01-20
申请号：US11132108
申请日：2005-05-18
申请人： Daniel C. Edelstein , Stephen M. Gates , Alfred Grill , Michael Lane , Qinghuang Lin , Robert D. Miller , Deborah A. Neumayer , Son Van Nguyen
发明人： Daniel C. Edelstein , Stephen M. Gates , Alfred Grill , Michael Lane , Qinghuang Lin , Robert D. Miller , Deborah A. Neumayer , Son Van Nguyen
IPC分类号： C23C16/22
CPC分类号： H01L31/103 , Y10T428/31663
摘要： A low-k dielectric material with increased cohesive strength for use in electronic structures including interconnect and sensing structures is provided that includes atoms of Si, C, O, and H in which a fraction of the C atoms are bonded as Si—CH3 functional groups, and another fraction of the C atoms are bonded as Si—R—Si, wherein R is phenyl, —[CH2]n— where n is greater than or equal to 1, HC═CH, C═CH2, C≡C or a [S]n linkage, where n is a defined above.
摘要翻译：提供了一种用于包括互连和感测结构的电子结构中具有增强的内聚强度的低k电介质材料，其包括其中一部分C原子键合为Si-CH 3官能团的Si，C，O和H的原子，另一部分C原子键合为Si-R-Si，其中R为苯基， - [CH2] n-，其中n大于或等于1，HC-CH，C-CH2，C≡C或一个[S] n连接，其中n是上面定义的。

14. 发明授权

US08779600B2 Interlevel dielectric stack for interconnect structures 有权
标题翻译：用于互连结构的层间电介质叠层
公开(公告)号：US08779600B2
公开(公告)日：2014-07-15
申请号：US13344009
申请日：2012-01-05
申请人： Son Van Nguyen , Griselda Bonilla , Alfred Grill , Thomas J. Haigh, Jr. , Satyanarayana V. Nitta
发明人： Son Van Nguyen , Griselda Bonilla , Alfred Grill , Thomas J. Haigh, Jr. , Satyanarayana V. Nitta
IPC分类号： H01L29/40
CPC分类号： H01L23/5384 , H01L21/02167 , H01L21/02274 , H01L21/76801 , H01L21/76825 , H01L21/76832 , H01L21/76834 , H01L23/5329 , H01L23/53295 , H01L2924/0002 , Y10T428/249969 , H01L2924/00
摘要： A dielectric stack and method of depositing the stack to a substrate using a single step deposition process. The dielectric stack includes a dense layer and a porous layer of the same elemental compound with different compositional atomic percentage, density, and porosity. The stack enhances mechanical modulus strength and enhances oxidation and copper diffusion barrier properties. The dielectric stack has inorganic or hybrid inorganic-organic random three-dimensional covalent bonding throughout the network, which contain different regions of different chemical compositions such as a cap component adjacent to a low-k component of the same type of material but with higher porosity.
摘要翻译：一种电介质堆叠和使用单步沉积工艺将叠层沉积到衬底的方法。电介质堆叠包括具有不同组成原子百分比，密度和孔隙率的相同元素化合物的致密层和多孔层。该堆叠增强机械模量强度并增强氧化和铜扩散阻挡性能。电介质叠层在整个网络中具有无机或杂化的无机 - 有机随机三维共价键，其含有不同化学组成的不同区域，例如与相同类型材料的低k组分相邻但具有较高孔隙率的盖组分。

15. 发明授权

US08637412B2 Process to form an adhesion layer and multiphase ultra-low k dielectric material using PECVD 有权
标题翻译：使用PECVD形成粘合层和多相超低k电介质材料的工艺
公开(公告)号：US08637412B2
公开(公告)日：2014-01-28
申请号：US13214157
申请日：2011-08-19
申请人： Alfred Grill , Thomas Jasper Haigh, Jr. , Kelly Malone , Son Van Nguyen , Vishnubhai Vitthalbhai Patel , Hosadurga Shobha
发明人： Alfred Grill , Thomas Jasper Haigh, Jr. , Kelly Malone , Son Van Nguyen , Vishnubhai Vitthalbhai Patel , Hosadurga Shobha
IPC分类号： H01L21/31 , H01L21/469
CPC分类号： H01L29/511 , C08J9/26 , C08J2201/042 , C08J2383/04 , H01L21/02126 , H01L21/02203 , H01L21/02216 , H01L21/02274 , H01L21/02304 , H01L21/02337 , H01L21/02348 , H01L21/02351 , H01L21/76801 , H01L21/76825 , H01L21/76829 , H01L21/76832 , H01L23/5329 , H01L29/515 , H01L2924/0002 , H01L2924/00
摘要： A first PECVD process incorporating a silicon oxide precursor alone and then with an organo-silicon precursor with increasing flow while the flow of the silicon oxide precursor is reduced to zero provides a graded carbon adhesion layer whereby the content of C increases with layer thickness and a second PECVD process incorporating an organo-silicon precursor including an organic porogen provides a multiphase ultra-low k dielectric. The multiphase ultra-low k PECVD process uses high frequency radio frequency power just above plasma initiation in a PECVD chamber. An energy post treatment is also provided. A porous SiCOH dielectric material having a k less than 2.7 and a modulus of elasticity greater than 7 GPa is formed.
摘要翻译：第一PECVD工艺，其单独掺入氧化硅前体，然后与有机硅前驱物同时增加流动，同时氧化硅前体的流动减少至零，从而提供渐变的碳粘附层，由此C的含量随层的厚度而增加，结合包含有机致孔剂的有机硅前体的第二PECVD工艺提供了多相超低k电介质。多相超低k PECVD工艺在PECVD室中使用高于等离子体起始的高频射频功率。还提供了能量后处理。形成k小于2.7且弹性模量大于7GPa的多孔SiCOH电介质材料。

16. 发明申请

US20110162874A1 SELF-ALIGNED COMPOSITE M-MOx/DIELECTRIC CAP FOR Cu INTERCONNECT STRUCTURES 有权
标题翻译：用于Cu互连结构的自对准复合材料M-MOx /电介质盖
公开(公告)号：US20110162874A1
公开(公告)日：2011-07-07
申请号：US12683590
申请日：2010-01-07
申请人： Son Van Nguyen , Alfred Grill , Thomas J. Haigh, JR. , Hosadurga Shobha , Tuan A. Vo
发明人： Son Van Nguyen , Alfred Grill , Thomas J. Haigh, JR. , Hosadurga Shobha , Tuan A. Vo
IPC分类号： H05K1/09 , B05D5/12 , B05D3/06 , B05D3/04
CPC分类号： H01L21/76849 , H01L21/76846 , H01L21/76864 , H01L21/76867
摘要： An interconnect structure is provided that has improved electromigration resistance as well as methods of forming such an interconnect structure. The interconnect structure includes an interconnect dielectric material having a dielectric constant of about 4.0 or less. The interconnect dielectric material has at least one opening therein that is filled with a Cu-containing material. The Cu-containing material within the at least one opening has an exposed upper surface that is co-planar with an upper surface of the interconnect dielectric material. The interconnect structure further includes a composite M-MOx cap located at least on the upper surface of the Cu-containing material within the at least one opening. The composite M-MOx cap includes an upper region that is composed of the metal having a higher affinity for oxygen than copper and copper oxide and a lower region that is composed of a non-stoichiometric oxide of said metal. The interconnect structure further includes a dielectric cap located on at least an upper surface of the composite M-MOx cap.
摘要翻译：提供了具有改进的电迁移阻力的互连结构以及形成这种互连结构的方法。互连结构包括具有约4.0或更小的介电常数的互连电介质材料。互连电介质材料在其中具有填充有含Cu材料的至少一个开口。至少一个开口内的含Cu材料具有与互连电介质材料的上表面共面的暴露的上表面。互连结构还包括至少位于至少一个开口内的含Cu材料的上表面上的复合M-MOx帽。复合M-MOx帽包括由与氧和氧化铜相比具有比氧更高的亲和性的金属构成的上部区域和由所述金属的非化学计量氧化物构成的下部区域。互连结构还包括位于复合M-MOx帽的至少上表面上的介电帽。

17. 发明申请

US20090224374A1 ADVANCED MULTILAYER DIELECTRIC CAP WITH IMPROVED MECHANICAL AND ELECTRICAL PROPERTIES 失效
标题翻译：具有改进的机械和电气特性的高级多层电介质盖
公开(公告)号：US20090224374A1
公开(公告)日：2009-09-10
申请号：US12042873
申请日：2008-03-05
申请人： Ritwik Bhatia , Griselda Bonilla , Alfred Grill , Joshua L. Herman , Son Van Nguyen , E. Todd Ryan , Hosadurga Shobha
发明人： Ritwik Bhatia , Griselda Bonilla , Alfred Grill , Joshua L. Herman , Son Van Nguyen , E. Todd Ryan , Hosadurga Shobha
IPC分类号： H01L23/538 , H01L23/58 , H01L21/31 , H01L21/768
CPC分类号： H01L21/76834 , H01L21/02348 , H01L21/76832
摘要： A dielectric cap, interconnect structure containing the same and related methods are disclosed. The inventive dielectric cap includes a multilayered dielectric material stack wherein at least one layer of the stack has good oxidation resistance, Cu diffusion and/or substantially higher mechanical stability during a post-deposition curing treatment, and including Si—N bonds at the interface of a conductive material such as, for example, Cu. The dielectric cap exhibits a high compressive stress and high modulus and is still remain compressive stress under post-deposition curing treatments for, for example: copper low k back-end-of-line (BEOL) nanoelectronic devices, leading to less film and device cracking and improved reliability.
摘要翻译：公开了包含相同方法和相关方法的电介质盖，互连结构。本发明的电介质盖包括多层介电材料堆叠，其中叠层的至少一层在后沉积固化处理期间具有良好的抗氧化性，Cu扩散和/或显着更高的机械稳定性，并且包括Si-N键在导电材料，例如Cu。电介质盖表现出高压缩应力和高模量，并且在后沉积固化处理时仍然保持压应力，例如：铜低k后端（BEOL）纳米电子器件，导致较少的膜和器件开裂和可靠性提高。

18. 发明授权

US07312524B2 Method for fabricating an ultralow dielectric constant material as an intralevel or interlevel dielectric in a semiconductor device and electronic device made 有权
标题翻译：在半导体器件和电子器件中制造超低介电常数材料作为层间或层间电介质的方法
公开(公告)号：US07312524B2
公开(公告)日：2007-12-25
申请号：US11324479
申请日：2006-01-03
申请人： Stephen M. Gates , Alfred Grill , David R. Medeiros , Deborah Newmayer , Son Van Nguyen , Vishnubhai V. Patel , Xinhui Wang
发明人： Stephen M. Gates , Alfred Grill , David R. Medeiros , Deborah Newmayer , Son Van Nguyen , Vishnubhai V. Patel , Xinhui Wang
IPC分类号： H01L23/12 , H01L23/053
CPC分类号： H01L21/3122 , H01L21/02126 , H01L21/02216 , H01L21/02274 , H01L21/0234 , H01L21/02348 , H01L21/02351 , H01L21/02362 , H01L21/31633 , H01L21/31695
摘要： A method for fabricating a thermally stable ultralow dielectric constant film including Si, C, O and H atoms in a parallel plate chemical vapor deposition process utilizing a plasma enhanced chemical vapor deposition (“PECVD”) process is disclosed. Electronic devices containing insulating layers of thermally stable ultralow dielectric constant materials that are prepared by the method are further disclosed. To enable the fabrication of a thermally stable ultralow dielectric constant film, specific precursor materials are used, such as, silane derivatives, for instance, diethoxymethylsilane (DEMS) and organic molecules, for instance, bicycloheptadiene and cyclopentene oxide.
摘要翻译：公开了一种在使用等离子体增强化学气相沉积（“PECVD”）工艺的平行板化学气相沉积工艺中制造包括Si，C，O和H原子的热稳定超低介电常数膜的方法。还公开了通过该方法制备的包含热稳定的超低介电常数材料的绝缘层的电子器件。为了制造热稳定的超低介电常数膜，使用特定的前体材料，例如硅烷衍生物，例如二乙氧基甲基硅烷（DEMS）和有机分子，例如双环庚二烯和环戊烯氧化物。

19. 发明授权

US07049247B2 Method for fabricating an ultralow dielectric constant material as an intralevel or interlevel dielectric in a semiconductor device and electronic device made 有权
标题翻译：在半导体器件和电子器件中制造超低介电常数材料作为层间或层间电介质的方法
公开(公告)号：US07049247B2
公开(公告)日：2006-05-23
申请号：US10838849
申请日：2004-05-03
申请人： Stephen M. Gates , Alfred Grill , David R. Medeiros , Deborah Neumayer , Son Van Nguyen , Vishnubhai V. Patel , Xinhui Wang
发明人： Stephen M. Gates , Alfred Grill , David R. Medeiros , Deborah Neumayer , Son Van Nguyen , Vishnubhai V. Patel , Xinhui Wang
IPC分类号： H01L21/31
CPC分类号： H01L21/3122 , H01L21/02126 , H01L21/02216 , H01L21/02274 , H01L21/0234 , H01L21/02348 , H01L21/02351 , H01L21/02362 , H01L21/31633 , H01L21/31695
摘要： A method for fabricating a thermally stable ultralow dielectric constant film comprising Si, C, O and H atoms in a parallel plate chemical vapor deposition process utilizing a plasma enhanced chemical vapor deposition (“PECVD”) process is disclosed. Electronic devices containing insulating layers of thermally stable ultralow dielectric constant materials that are prepared by the method are further disclosed. To enable the fabrication of a thermally stable ultralow dielectric constant film, specific precursor materials are used, such as, silane derivatives, for instance, diethoxymethylsilane (DEMS) and organic molecules, for instance, bicycloheptadiene and cyclopentene oxide.
摘要翻译：公开了一种使用等离子体增强化学气相沉积（“PECVD”）工艺在平行板化学气相沉积工艺中制造包含Si，C，O和H原子的热稳定超低介电常数膜的方法。还公开了通过该方法制备的包含热稳定的超低介电常数材料的绝缘层的电子器件。为了制造热稳定的超低介电常数膜，使用特定的前体材料，例如硅烷衍生物，例如二乙氧基甲基硅烷（DEMS）和有机分子，例如双环庚二烯和环戊烯氧化物。

20. 发明申请

US20130175697A1 Interlevel Dielectric Stack for Interconnect Structures 有权
标题翻译：用于互连结构的层间介质堆叠
公开(公告)号：US20130175697A1
公开(公告)日：2013-07-11
申请号：US13344009
申请日：2012-01-05
申请人： Son Van Nguyen , Griselda Bonilla , Alfred Grill , Thomas J. Haigh, JR. , Satyanarayana V. Nitta
发明人： Son Van Nguyen , Griselda Bonilla , Alfred Grill , Thomas J. Haigh, JR. , Satyanarayana V. Nitta
IPC分类号： H01L23/538 , H01L21/31 , B32B9/04
CPC分类号： H01L23/5384 , H01L21/02167 , H01L21/02274 , H01L21/76801 , H01L21/76825 , H01L21/76832 , H01L21/76834 , H01L23/5329 , H01L23/53295 , H01L2924/0002 , Y10T428/249969 , H01L2924/00
摘要： A dielectric stack and method of depositing the stack to a substrate using a single step deposition process. The dielectric stack includes a dense layer and a porous layer of the same elemental compound with different compositional atomic percentage, density, and porosity. The stack enhances mechanical modulus strength and enhances oxidation and copper diffusion barrier properties. The dielectric stack has inorganic or hybrid inorganic-organic random three-dimensional covalent bonding throughout the network, which contain different regions of different chemical compositions such as a cap component adjacent to a low-k component of the same type of material but with higher porosity.
摘要翻译：一种电介质堆叠和使用单步沉积工艺将叠层沉积到衬底的方法。电介质堆叠包括具有不同组成原子百分比，密度和孔隙率的相同元素化合物的致密层和多孔层。该堆叠增强机械模量强度并增强氧化和铜扩散阻挡性能。电介质叠层在整个网络中具有无机或杂化的无机 - 有机随机三维共价键，其含有不同化学组成的不同区域，例如与相同类型材料的低k组分相邻但具有较高孔隙率的盖组分。

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