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11. 发明授权

US06475871B1 Passive multiplexor test structure for integrated circuit manufacturing 失效
标题翻译：无源多路复用器集成电路制造测试结构
公开(公告)号：US06475871B1
公开(公告)日：2002-11-05
申请号：US09715851
申请日：2000-11-17
申请人： Brian E. Stine , Christopher Hess , Larg H. Weiland
发明人： Brian E. Stine , Christopher Hess , Larg H. Weiland
IPC分类号： H02L2120
CPC分类号： H01L22/34 , H01L2924/0002 , H01L2924/00
摘要： A test structure for analyzing failures due to fabrication induced defects in integrated circuits includes a matrix of bit cells formed by word lines and bit lines. An associated word line probe pad is electrically connected to each word line and an associated bit line probe pad electrically connected to each bit line. A test structure is electrically connected between a word line and a bit line of an associated bit cell. Each test structure has at least one variable attribute which is used to detect defects and create yield models.
摘要翻译：用于分析由于集成电路中的制造引起的缺陷导致的故障的测试结构包括由字线和位线形成的位单元的矩阵。相关联的字线探针焊盘电连接到每个字线和电连接到每个位线的相关联的位线探针焊盘。测试结构电连接在相关位单元的字线和位线之间。每个测试结构具有至少一个变量属性，用于检测缺陷并创建产量模型。

12. 发明授权

US06787800B2 Test vehicle with zig-zag structures 有权
标题翻译：测试具有锯齿形结构的车辆
公开(公告)号：US06787800B2
公开(公告)日：2004-09-07
申请号：US10202278
申请日：2002-07-24
申请人： Larg H. Weiland , Christopher Hess
发明人： Larg H. Weiland , Christopher Hess
IPC分类号： H01L2910
CPC分类号： G01R1/073
摘要： A test vehicle has a plurality of the zig-zag structures which include: a first layer having a plurality of first elongated patterns oriented in a first direction; a second layer having a plurality of second elongated patterns oriented in a second direction substantially perpendicular to the first direction; and a plurality of vias or contacts conductively coupling ones of the first patterns to respective ones of the second patterns.
摘要翻译：测试车辆具有多个之字形结构，其包括：具有沿第一方向定向的多个第一细长图案的第一层; 第二层，具有在基本上垂直于第一方向的第二方向上定向的多个第二细长图案; 以及多个通孔或触点将第一图案之一导电地耦合到相应的第二图案。

13. 发明申请

US20070268731A1 Layout compiler 审中-公开
标题翻译：布局编译器
公开(公告)号：US20070268731A1
公开(公告)日：2007-11-22
申请号：US11438777
申请日：2006-05-22
申请人： Larg H. Weiland , Stefan Drapatz , Markus R. Decker
发明人： Larg H. Weiland , Stefan Drapatz , Markus R. Decker
IPC分类号： G11C5/02
CPC分类号： G11C5/025 , G01R31/31707 , G01R31/318314 , H01L22/34
摘要： For methods of creating pluralities of semiconductor test structure layouts from a graphical specification, systems include a GUI to draw objects representing shapes of such layout, and to parameterize those objects to size and interrelate those objects. The GUI supports placement of cells in hierarchical layers. The graphical specification is parsed into an ASCII descriptor file from which node information is extracted and connection information among nodes preserved in separate graphs for an X direction and a Y direction of the layout. That node and connection information is further processed to obtain equations having variables (parameters) that relate points in the layout a defined point, and those equations used in forming source code that can be executed with values for the variables in the source code.
摘要翻译：对于从图形规范创建多个半导体测试结构布局的方法，系统包括GUI来绘制表示这种布局的形状的对象，并且对这些对象进行参数化以对这些对象进行尺寸和相互关联。 GUI支持在层次结构中放置单元格。将图形规范解析为ASCII描述符文件，从中提取节点信息，并将节点之间的连接信息保存在布局的X方向和Y方向的分离图中。该节点和连接信息被进一步处理以获得具有将布局中的点定义为点的变量（参数）的等式，以及用于形成可以用源代码中的变量的值执行的源代码的等式。

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