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11. 发明授权

US08694721B2 Memory buffer with one or more auxiliary interfaces 有权
标题翻译：具有一个或多个辅助接口的内存缓冲区
公开(公告)号：US08694721B2
公开(公告)日：2014-04-08
申请号：US13359877
申请日：2012-01-27
申请人： Christopher Haywood
发明人： Christopher Haywood
IPC分类号： G06F12/00
CPC分类号： G06F3/0685 , G06F3/0604 , G06F3/0659 , G06F13/1642 , G06F13/1694
摘要： The present memory system includes a memory buffer having an interface arranged to buffer data and/or command bytes being written to or read from the RAM chips residing on a DIMM by a host controller. The memory buffer further includes at least one additional interface arranged to buffer data and/or command bytes between the host controller or RAM chips and one or more external devices coupled to the at least one additional interface. For example, the memory buffer may include a SATA interface and be arranged to convey data between the host controller or RAM chips and FLASH memory devices coupled to the SATA interface. The additional interfaces may include, for example, a SATA interface, an Ethernet interface, an optical interface, and/or a radio interface.
摘要翻译：本存储器系统包括存储器缓冲器，其具有被布置为缓冲由主机控制器写入或存储在DIMM上的RAM芯片的数据和/或命令字节的接口。存储器缓冲器还包括至少一个额外的接口，其布置成在主机控制器或RAM芯片与耦合到至少一个附加接口的一个或多个外部设备之间缓冲数据和/或命令字节。例如，存储器缓冲器可以包括SATA接口，并且被布置成在主机控制器或RAM芯片与耦合到SATA接口的闪存设备之间传送数据。附加接口可以包括例如SATA接口，以太网接口，光接口和/或无线电接口。

12. 发明申请

US20120260024A1 MEMORY BUFFER WITH ONE OR MORE AUXILIARY INTERFACES 有权
标题翻译：具有一个或多个辅助界面的内存缓冲区
公开(公告)号：US20120260024A1
公开(公告)日：2012-10-11
申请号：US13359877
申请日：2012-01-27
申请人： Christopher Haywood
发明人： Christopher Haywood
IPC分类号： G06F12/02 , G06F12/00
CPC分类号： G06F3/0685 , G06F3/0604 , G06F3/0659 , G06F13/1642 , G06F13/1694
摘要： The present memory system includes a memory buffer having an interface arranged to buffer data and/or command bytes being written to or read from the RAM chips residing on a DIMM by a host controller. The memory buffer further includes at least one additional interface arranged to buffer data and/or command bytes between the host controller or RAM chips and one or more external devices coupled to the at least one additional interface. For example, the memory buffer may include a SATA interface and be arranged to convey data between the host controller or RAM chips and FLASH memory devices coupled to the SATA interface. The additional interfaces may include, for example, a SATA interface, an Ethernet interface, an optical interface, and/or a radio interface.
摘要翻译：本存储器系统包括存储器缓冲器，其具有被布置为缓冲由主机控制器写入或存储在DIMM上的RAM芯片的数据和/或命令字节的接口。存储器缓冲器还包括至少一个额外的接口，其布置成在主机控制器或RAM芯片与耦合到至少一个附加接口的一个或多个外部设备之间缓冲数据和/或命令字节。例如，存储器缓冲器可以包括SATA接口，并且被布置成在主机控制器或RAM芯片与耦合到SATA接口的闪存设备之间传送数据。附加接口可以包括例如SATA接口，以太网接口，光接口和/或无线电接口。

13. 发明授权

US07586849B2 Dedicated bandwidth data communication switch backplane 有权
标题翻译：专用带宽数据通信交换机背板
公开(公告)号：US07586849B2
公开(公告)日：2009-09-08
申请号：US11231920
申请日：2005-09-21
申请人： Christopher Haywood , Geoffrey C. Stone
发明人： Christopher Haywood , Geoffrey C. Stone
IPC分类号： H04L12/26 , H04L12/28
CPC分类号： H04L49/351 , H04L12/4641 , H04L45/7453 , H04L49/354
摘要： A LAN switch has a backplane matrix in which each controller has a dedicated packet bus for propagating packet data. Each bus has a root interfacing with the transmitting (root) controller and a plurality of leaves interfacing with receiving (leaf) controllers. This configuration enables each controller to simultaneously transmit packet data on the root of a bus and receive packet data off a plurality of leaves of other buses without contention. An efficient filtering and stalling system employed at the receive side of the backplane prevents the highly parallel traffic from causing receive side congestion.
摘要翻译： LAN交换机具有背板矩阵，其中每个控制器具有用于传播分组数据的专用分组总线。每个总线具有与传输（根）控制器的根接口以及与接收（叶）控制器接口的多个叶。该配置使得每个控制器能够在总线的根部上同时发送分组数据，并且在没有争用的情况下从多个其他总线的叶片接收分组数据。在背板的接收侧使用的有效的滤波和停止系统防止高度并行的业务造成接收端拥塞。

14. 发明授权

US06931019B2 Receive processing for dedicated bandwidth data communication switch backplane 失效
标题翻译：接收处理专用带宽数据通信交换机背板
公开(公告)号：US06931019B2
公开(公告)日：2005-08-16
申请号：US09871868
申请日：2001-06-01
申请人： Wai King , Geoffrey C. Stone , Christopher Haywood
发明人： Wai King , Geoffrey C. Stone , Christopher Haywood
IPC分类号： H04L12/46 , H04L12/56 , G06F3/00 , G06F13/00
CPC分类号： H04L49/351 , H04L45/7453 , H04L49/101 , H04L49/254 , H04L49/3018
摘要： A dedicated bandwidth switch backplane has efficient receive processing capable of handling highly parallel traffic. Packets must pass a filtering check and a watermark check before the receive port is allowed to release them to a queue. Highly efficient algorithms are applied to conduct the checks on the packets in a way which expedites receive processing and avoids contention. A hybrid priority/port-based arbitration algorithm is used to sequence filtering checks on pending packets. A watermark comparison algorithm performs preliminary calculations on the current packet using “projected” output queue write addresses for each possible outcome of the queueing decision on the preceding packet and using the actual outcome to select from among preliminary calculations to efficiently address the outcome-dependence of the current packet's watermark check on the queueing decision made on the preceding packet. Receive ports are operatively divided into full-write receive ports and selective-write receive ports for delivering their packets to the output queue. On the clock cycles where the selective-write receive port is assigned writing privileges, data is read from the queue, unless the selective-write receive port has indicated it wishes to write to the queue, in which case the selective-write receive port writes to the queue. The full-write receive ports always write data, if available, to the queue on the clock cycles where they are assigned writing privileges.
摘要翻译：专用带宽交换机背板具有能够处理高度并行流量的高效接收处理。在允许接收端口将其释放到队列之前，数据包必须通过过滤检查和水印检查。应用高效算法，以加快接收处理的方式对数据包进行检查，避免争用。混合优先级/基于端口的仲裁算法用于对未决数据包进行过滤检查。水印比较算法使用“投影”输出队列写地址对前一分组的排队决策的每个可能结果执行对当前分组的初步计算，并使用实际结果从初步计算中选择以有效地解决结果依赖性当前数据包的水印检查对上一个数据包进行排队决定。接收端口可操作地分为全写接收端口和选择性写入接收端口，用于将其数据包传送到输出队列。在选择性写入接收端口被分配写入特权的时钟周期中，从队列中读取数据，除非选择性写入接收端口已经表示希望写入队列，在这种情况下，选择性写入接收端口写入到队列全写入接收端口始终将数据（如果可用）写入队列，在它们被分配写入权限的时钟周期中。

15. 发明授权

US6006306A Integrated circuit with stage-implemented content-addressable memory cell 失效
标题翻译：具有阶段实现内容可寻址存储单元的集成电路
公开(公告)号：US6006306A
公开(公告)日：1999-12-21
申请号：US887359
申请日：1997-07-02
申请人： Christopher Haywood , Michael de la Garrigue
发明人： Christopher Haywood , Michael de la Garrigue
IPC分类号： G11C15/00
CPC分类号： G11C15/00
摘要： A CAM integrated circuit has a stage-implemented CAM cell which operationally separates CAM read operations into distinct stages, including look-up, prioritization and encoding, that execute independently. The staged implementation is achieved by placing registers between operational logic blocks in the CAM cell. The integrated circuit prioritizes inputs received simultaneously on dual input buses to avoid contention.
摘要翻译： CAM集成电路具有阶段实现的CAM单元，其将CAM读取操作分离成独立执行的不同阶段，包括查找，优先级和编码。分阶段实现是通过在CAM单元中的操作逻辑块之间放置寄存器来实现的。集成电路优先考虑双输入总线同时接收的输入，以避免争用。

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