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11. 发明授权

US6013570A LDD transistor using novel gate trim technique 失效
标题翻译： LDD晶体管采用新颖的栅极贴装技术
公开(公告)号：US6013570A
公开(公告)日：2000-01-11
申请号：US118389
申请日：1998-07-17
申请人： Allen S. Yu , Patrick K. Cheung , Paul J. Steffan
发明人： Allen S. Yu , Patrick K. Cheung , Paul J. Steffan
IPC分类号： H01L21/28 , H01L21/336
CPC分类号： H01L29/6659 , H01L21/28123 , H01L29/66659
摘要： An ultra-large scale MOS integrated circuit semiconductor device is processed after the formation of the gate oxide and polysilicon layer by forming a forming a first mask layer over the polysilicon layer followed by a second mask layer over the first mask layer. The first mask layer and the second mask layer are patterned to form first gate mask and second gate mask respectively. The polysilicon gate is then formed by anisotropically etching the polysilicon layer. The second gate mask is then removed. The polysilicon gate is then etched isotropically to reduce its width using the gate oxide layer and the patterned first gate mask as hard masks. The first gate mask is then used as a mask for dopant implantation to form source and drain extensions which are spaced away from the edges of the polysilicon gate. Thereafter, the first gate mask is removed and a spacer is formed dopant implantation to form deep source and drain junctions. A higher temperature rapid thermal anneal then optimizes the source and drain extension junctions and junctions, and the spacer is removed. Since the source and drain extension junctions are spaced away from the edges of the polysilicon gate, the displacement of the source/drain extension junctions into the channel is reduced. This results in a device with reduced parasitic capacitance.
摘要翻译：在形成栅极氧化物和多晶硅层之后，通过在多晶硅层上形成第一掩模层，然后在第一掩模层上形成第二掩模层，来处理超大规模MOS集成电路半导体器件。图案化第一掩模层和第二掩模层以分别形成第一栅极掩模和第二栅极掩模。然后通过各向异性蚀刻多晶硅层形成多晶硅栅极。然后删除第二个门屏蔽。然后使用栅极氧化物层和图案化的第一栅极掩模作为硬掩模，各向异性腐蚀多晶硅栅极以减小其宽度。然后将第一栅极掩模用作掺杂剂注入的掩模，以形成与多晶硅栅极的边缘间隔开的源极和漏极延伸部。此后，去除第一栅极掩模并且形成衬垫以形成掺杂剂注入以形成深的源极和漏极结。然后，较高温度的快速热退火优化源极和漏极延伸接合部和接合部，并且移除间隔物。由于源极和漏极延伸接头与多晶硅栅极的边缘间隔开，所以源极/漏极延伸接合部分到沟道的位移被减小。这导致具有降低的寄生电容的器件。

12. 发明授权

US07220985B2 Self aligned memory element and wordline 有权
标题翻译：自对准存储元件和字线
公开(公告)号：US07220985B2
公开(公告)日：2007-05-22
申请号：US10314591
申请日：2002-12-09
申请人： Patrick K. Cheung , Ashok M. Khathuria
发明人： Patrick K. Cheung , Ashok M. Khathuria
IPC分类号： H01L21/00 , H01L29/08 , H01L35/24 , H01L51/00
CPC分类号： H01L27/28
摘要： An organic polymer memory cell is provided having an organic polymer layer and an electrode layer formed over a first conductive (e.g., copper) layer (e.g., bitline). The memory cells are connected to a second conductive layer (e.g., forming a wordline), and more particularly the top of the electrode layer of the memory cells to the second conductive layer. Optionally, a conductivity facilitating layer is formed over the conductive layer. Dielectric material separates the memory cells. The memory cells are self-aligned with the bitlines formed in the first conductive layer and the wordlines formed in the second conductive layer.
摘要翻译：提供了一种有机聚合物记忆单元，其具有形成在第一导电（例如铜）层（例如位线）上的有机聚合物层和电极层。存储单元连接到第二导电层（例如，形成字线），更具体地，将存储器单元的电极层的顶部连接到第二导电层。可选地，导电促进层形成在导电层上。电介质材料分离存储单元。存储单元与形成在第一导电层中的位线和形成在第二导电层中的字线自对准。

13. 发明授权

US06287922B1 Method for fabricating graded LDD transistor using controlled polysilicon gate profile 有权
标题翻译：使用受控多晶硅栅极型材制造分级LDD晶体管的方法
公开(公告)号：US06287922B1
公开(公告)日：2001-09-11
申请号：US09162426
申请日：1998-09-28
申请人： Allen S. Yu , Patrick K. Cheung , Paul J. Steffan
发明人： Allen S. Yu , Patrick K. Cheung , Paul J. Steffan
IPC分类号： H01L21336
CPC分类号： H01L29/66598 , H01L21/28114 , H01L21/823814 , H01L21/82385 , H01L29/665 , H01L29/66545 , H01L29/6659 , Y10S438/978
摘要： An ultra-large scale CMOS integrated circuit semiconductor device with LDD structures having gradual doping profiles and reduced process complexity is manufactured by forming a gate oxide layer over the semiconductor substrate; forming a polysilicon layer over the gate oxide layer, forming a first mask layer over the polysilicon layer; patterning and etching the first mask layer to form a first gate mask; anisotropically etching the polysilicon layer to form a first polysilicon gate, wherein the first polysilicon gate has sidewalls with sloped profiles, and implanting the semiconductor substrate with a dopant to penetrate portions of the sidewalls to form one or more graded shallow junctions with gradual doping profiles.
摘要翻译：通过在半导体衬底上形成栅氧化层，制造具有逐渐掺杂分布和降低工艺复杂度的LDD结构的超大规模CMOS集成电路半导体器件; 在所述栅极氧化物层上形成多晶硅层，在所述多晶硅层上形成第一掩模层; 图案化和蚀刻第一掩模层以形成第一栅极掩模; 各向异性蚀刻所述多晶硅层以形成第一多晶硅栅极，其中所述第一多晶硅栅极具有倾斜轮廓的侧壁，以及用掺杂剂注入所述半导体衬底以穿透所述侧壁的部分以形成具有逐渐掺杂分布的一个或多个渐变浅结。

14. 发明授权

US06191044B1 Method for forming graded LDD transistor using controlled polysilicon gate profile 失效
标题翻译：使用受控多晶硅栅极分布形成渐变LDD晶体管的方法
公开(公告)号：US06191044B1
公开(公告)日：2001-02-20
申请号：US09169275
申请日：1998-10-08
申请人： Allen S. Yu , Patrick K. Cheung , Paul J. Steffan
发明人： Allen S. Yu , Patrick K. Cheung , Paul J. Steffan
IPC分类号： H01L21302
CPC分类号： H01L29/6659 , H01L21/266 , H01L21/32137 , H01L29/36 , H01L29/42376 , H01L29/7833
摘要： An ultra-large scale CMOS integrated circuit semiconductor device with LDD structures having reduced polysilicon gate length, reduced parasitic capacitance and gradual doping profiles is manufactured by forming a gate oxide layer over the semiconductor substrate; forming a polysilicon layer over the gate oxide layer; forming a first mask layer over the polysilicon layer; patterning and etching the first mask layer to form a first gate mask; anisotropically etching the polysilicon layer to form a polysilicon gate, wherein the polysilicon gate comprises sidewalls with re-entrant profiles, and implanting the semiconductor substrate with a dopant to penetrate portions of the sidewalls to form one or more graded shallow junctions with gradual doping profiles. The gradual doping profiles reduce parasitic capacitance and minimize hot carrier injections. Portions of the polysilicon gates with re-entrant profiles are used as mask during the ion implantation of the LDD structures to space the resultant LDD structures away from the edges of the bottom portion of the polysilicon gates. Since the LDD structures are spaced away from the edges of the polysilicon gates, the lateral diffusion of the LDD structures into the channel due to rapid thermal annealing is reduced. This results in CMOS devices with reduced parasitic capacitance.
摘要翻译：通过在半导体衬底上形成栅极氧化层，制造具有降低的多晶硅栅极长度，降低的寄生电容和逐渐掺杂分布的LDD结构的超大规模CMOS集成电路半导体器件; 在所述栅极氧化物层上形成多晶硅层; 在所述多晶硅层上形成第一掩模层; 图案化和蚀刻第一掩模层以形成第一栅极掩模; 各向异性地蚀刻所述多晶硅层以形成多晶硅栅极，其中所述多晶硅栅极包括具有重入曲线的侧壁，以及用掺杂剂注入所述半导体衬底以穿透所述侧壁的部分以形成具有逐渐掺杂分布的一个或多个渐变浅结。逐渐的掺杂分布减少寄生电容并最大限度地减少热载流子注入。在LDD结构的离子注入期间，将具有重入分布的多晶硅栅极的部分用作掩模，以将所得到的LDD结构远离多晶硅栅极的底部的边缘。由于LDD结构与多晶硅栅极的边缘间隔开，所以LDD结构由于快速热退火而向沟道中的横向扩散减少。这导致具有降低的寄生电容的CMOS器件。

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